1 # Copyright (C) 2008-2024 Free Software Foundation, Inc. 2 # 3 # This program is free software; you can redistribute it and/or modify 4 # it under the terms of the GNU General Public License as published by 5 # the Free Software Foundation; either version 3 of the License, or 6 # (at your option) any later version. 7 # 8 # This program is distributed in the hope that it will be useful, 9 # but WITHOUT ANY WARRANTY; without even the implied warranty of 10 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 # GNU General Public License for more details. 12 # 13 # You should have received a copy of the GNU General Public License 14 # along with this program. If not, see <http://www.gnu.org/licenses/>. 15 # 16 17 # 18 # Test the vsr registers print values in float128 bit format. 19 # 20 21 require {istarget "powerpc*"} allow_vsx_tests 22 23 standard_testfile 24 25 set compile_flags {debug nowarnings quiet} 26 if [test_compiler_info gcc*] { 27 set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec" 28 } elseif [test_compiler_info xlc*] { 29 set compile_flags "$compile_flags additional_flags=-qaltivec" 30 } else { 31 warning "unknown compiler" 32 return -1 33 } 34 35 if { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } { 36 untested "failed to compile" 37 return -1 38 } 39 40 gdb_start 41 gdb_reinitialize_dir $srcdir/$subdir 42 gdb_load ${binfile} 43 44 # Run to `main' where we begin our tests. 45 46 if {![runto_main]} { 47 return 0 48 } 49 50 set endianness [get_endianness] 51 52 # Data sets used throughout the test 53 54 set vector_field ".*float128 = -2.25,.*" 55 56 # The vsx registers now contain a 128-bit floating point field. The following tests 57 # setting a vsr register with a 128-bit floating point value and then printing the 58 # register contents using the float format to verify the value is correctly printed 59 # as a 128-bit value. 60 61 # the following corresponds to a 128-bit float value of -2.25 62 if {$endianness == "big"} { 63 gdb_test_no_output "set \$vs1.v4_int32\[3\] = 0x0" 64 gdb_test_no_output "set \$vs1.v4_int32\[2\] = 0x0" 65 gdb_test_no_output "set \$vs1.v4_int32\[1\] = 0x0" 66 gdb_test_no_output "set \$vs1.v4_int32\[0\] = 0xc0002000" 67 } else { 68 gdb_test_no_output "set \$vs1.v4_int32\[0\] = 0x0" 69 gdb_test_no_output "set \$vs1.v4_int32\[1\] = 0x0" 70 gdb_test_no_output "set \$vs1.v4_int32\[2\] = 0x0" 71 gdb_test_no_output "set \$vs1.v4_int32\[3\] = 0xc0002000" 72 } 73 74 # check the contents of the register 75 gdb_test "p/f \$vs1" "$vector_field" 76 77 gdb_exit 78 79 80 81