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      1 /* Main header for the Hitachi h8/300 architecture.  */
      2 
      3 #ifndef H8300_SIM_H
      4 #define H8300_SIM_H
      5 
      6 #define DEBUG
      7 
      8 /* These define the size of main memory for the simulator.
      9 
     10    Note the size of main memory for the H8/300H is only 256k.  Keeping it
     11    small makes the simulator run much faster and consume less memory.
     12 
     13    The linker knows about the limited size of the simulator's main memory
     14    on the H8/300H (via the h8300h.sc linker script).  So if you change
     15    H8300H_MSIZE, be sure to fix the linker script too.
     16 
     17    Also note that there's a separate "eightbit" area aside from main
     18    memory.  For simplicity, the simulator assumes any data memory reference
     19    outside of main memory refers to the eightbit area (in theory, this
     20    can only happen when simulating H8/300H programs).  We make no attempt
     21    to catch overlapping addresses, wrapped addresses, etc etc.  */
     22 
     23 #define H8300_MSIZE (1 << 16)
     24 
     25 /* avolkov:
     26    Next 2 macros are ugly for any workstation, but while they're work.
     27    Memory size MUST be configurable.  */
     28 #define H8300H_MSIZE (1 << 24)
     29 #define H8300S_MSIZE (1 << 24)
     30 
     31 #define CSIZE 1024
     32 
     33 enum h8_regnum {
     34   R0_REGNUM = 0,
     35   R1_REGNUM = 1,
     36   R2_REGNUM = 2,
     37   R3_REGNUM = 3,
     38   R4_REGNUM = 4,
     39   R5_REGNUM = 5,
     40   R6_REGNUM = 6,
     41   R7_REGNUM = 7,
     42 
     43   SP_REGNUM = R7_REGNUM,	/* Contains address of top of stack */
     44   FP_REGNUM = R6_REGNUM,	/* Contains address of executing
     45 				   stack frame */
     46   CCR_REGNUM = 8,		/* Contains processor status */
     47   PC_REGNUM  = 9,		/* Contains program counter */
     48   CYCLE_REGNUM = 10,
     49   EXR_REGNUM  = 11,
     50   INST_REGNUM = 12,
     51   TICK_REGNUM = 13,
     52   MACH_REGNUM = 14,
     53   MACL_REGNUM = 15,
     54   SBR_REGNUM =  16,
     55   VBR_REGNUM =  17,
     56 
     57   ZERO_REGNUM = 18
     58 };
     59 
     60 enum h8_typecodes {
     61   OP_NULL,
     62   OP_REG,		/* Register direct.  */
     63   OP_LOWREG,		/* Special reg syntax for "bra".  */
     64   OP_DISP,		/* Register indirect w/displacement.  */
     65   /* Note: h8300, h8300h, and h8300s permit only pre-decr and post-incr.  */
     66   OP_PREDEC,		/* Register indirect w/pre-decrement.  */
     67   OP_POSTDEC,		/* Register indirect w/post-decrement.  */
     68   OP_PREINC,		/* Register indirect w/pre-increment.  */
     69   OP_POSTINC,		/* Register indirect w/post-increment.  */
     70   OP_PCREL,		/* PC Relative.  */
     71   OP_MEM,		/* Absolute memory address.  */
     72   OP_CCR,		/* Condition Code Register.  */
     73   OP_IMM,		/* Immediate value.  */
     74   /*OP_ABS*/		/* Un-used (duplicates op_mem?).  */
     75   OP_EXR,		/* EXtended control Register.  */
     76   OP_SBR, 		/* Vector Base Register.  */
     77   OP_VBR,		/* Short-address Base Register.  */
     78   OP_MACH,		/* Multiply Accumulator - high.  */
     79   OP_MACL,		/* Multiply Accumulator - low.   */
     80   /* FIXME: memory indirect?  */
     81   OP_INDEXB,		/* Byte index mode */
     82   OP_INDEXW,		/* Word index mode */
     83   OP_INDEXL,		/* Long index mode */
     84   OP_REG_DEC,		/* Register direct. affect address decrement. */
     85   OP_REG_INC,		/* Register direct. affect address increment. */
     86 };
     87 
     88 /* Structure used to describe addressing */
     89 
     90 typedef struct
     91 {
     92   int type;
     93   int reg;
     94   int literal;
     95 } ea_type;
     96 
     97 /* Struct for instruction decoder.  */
     98 typedef struct
     99 {
    100   ea_type src;
    101   ea_type dst;
    102   ea_type op3;
    103   int opcode;
    104   int next_pc;
    105   int oldpc;
    106   int cycles;
    107 #ifdef DEBUG
    108   struct h8_opcode *op;
    109 #endif
    110 } decoded_inst;
    111 
    112 struct h8300_sim_cpu {
    113   unsigned int regs[20];	/* 8 GR's plus ZERO, SBR, and VBR.  */
    114   unsigned int pc;
    115 
    116   int macS;			/* MAC Saturating mode */
    117   int macV;			/* MAC Overflow */
    118   int macN;			/* MAC Negative */
    119   int macZ;			/* MAC Zero     */
    120 
    121   int delayed_branch;
    122   char **command_line;		/* Pointer to command line arguments.  */
    123 
    124   unsigned char *memory;
    125   int mask;
    126 };
    127 #define H8300_SIM_CPU(sd) ((struct h8300_sim_cpu *) CPU_ARCH_DATA (sd))
    128 
    129 struct h8300_sim_state {
    130   unsigned long memory_size;
    131 #ifdef ADEBUG
    132   int stats[O_LAST];
    133 #endif
    134 };
    135 #define H8300_SIM_STATE(sd) ((struct h8300_sim_state *) STATE_ARCH_DATA (sd))
    136 
    137 /* The current state of the processor; registers, memory, etc.  */
    138 
    139 #define cpu_set_pc(cpu, val)	(H8300_SIM_CPU (cpu)->pc = (val))
    140 #define cpu_get_pc(cpu)		(H8300_SIM_CPU (cpu)->pc)
    141 
    142 /* Magic numbers used to distinguish an exit from a breakpoint.  */
    143 #define LIBC_EXIT_MAGIC1 0xdead
    144 #define LIBC_EXIT_MAGIC2 0xbeef
    145 /* Local version of macros for decoding exit status.
    146    (included here rather than try to find target version of wait.h)
    147 */
    148 #define SIM_WIFEXITED(V)	(((V) & 0xff) == 0)
    149 #define SIM_WIFSTOPPED(V)	(!SIM_WIFEXITED (V))
    150 #define SIM_WEXITSTATUS(V)	(((V) >> 8) & 0xff)
    151 #define SIM_WSTOPSIG(V)		((V) & 0x7f)
    152 
    153 #endif /* H8300_SIM_H */
    154