1 # e500 core instructions, for PSIM, the PowerPC simulator. 2 3 # Copyright 2003-2024 Free Software Foundation, Inc. 4 5 # Contributed by Red Hat Inc; developed under contract from Motorola. 6 # Written by matthew green <mrg (a] redhat.com>. 7 8 # This file is part of GDB. 9 10 # This program is free software; you can redistribute it and/or modify 11 # it under the terms of the GNU General Public License as published by 12 # the Free Software Foundation; either version 3 of the License, or 13 # (at your option) any later version. 14 15 # This program is distributed in the hope that it will be useful, 16 # but WITHOUT ANY WARRANTY; without even the implied warranty of 17 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 # GNU General Public License for more details. 19 20 # You should have received a copy of the GNU General Public License 21 # along with this program. If not, see <http://www.gnu.org/licenses/>. 22 23 # 24 # e500 Core Complex Instructions 25 # 26 27 :cache:e500::signed_word *:rAh:RA:(cpu_registers(processor)->e500.gprh + RA) 28 :cache:e500::signed_word *:rSh:RS:(cpu_registers(processor)->e500.gprh + RS) 29 :cache:e500::signed_word *:rBh:RB:(cpu_registers(processor)->e500.gprh + RB) 30 31 # Flags for model.h 32 ::model-macro::: 33 #define PPC_INSN_INT_SPR(OUT_MASK, IN_MASK, SPR) \ 34 do { \ 35 if (CURRENT_MODEL_ISSUE > 0) \ 36 ppc_insn_int_spr(MY_INDEX, cpu_model(processor), OUT_MASK, IN_MASK, SPR); \ 37 } while (0) 38 39 # Schedule an instruction that takes 2 integer register and produces a special purpose output register plus an integer output register 40 void::model-function::ppc_insn_int_spr:itable_index index, model_data *model_ptr, const uint32_t out_mask, const uint32_t in_mask, const unsigned nSPR 41 const uint32_t int_mask = out_mask | in_mask; 42 model_busy *busy_ptr; 43 44 while ((model_ptr->int_busy & int_mask) != 0 || model_ptr->spr_busy[nSPR] != 0) { 45 if (WITH_TRACE && ppc_trace[trace_model]) 46 model_trace_busy_p(model_ptr, int_mask, 0, 0, nSPR); 47 48 model_ptr->nr_stalls_data++; 49 model_new_cycle(model_ptr); 50 } 51 52 busy_ptr = model_wait_for_unit(index, model_ptr, &model_ptr->timing[index]); 53 busy_ptr->int_busy |= out_mask; 54 model_ptr->int_busy |= out_mask; 55 busy_ptr->spr_busy = nSPR; 56 model_ptr->spr_busy[nSPR] = 1; 57 busy_ptr->nr_writebacks = (PPC_ONE_BIT_SET_P(out_mask)) ? 3 : 2; 58 TRACE(trace_model,("Making register %s busy.\n", spr_name(nSPR))); 59 61 # 62 # SPE Modulo Fractional Multiplication handling support 63 # 64 :function:e500::uint64_t:ev_multiply16_smf:int16_t a, int16_t b, int *sat 65 int32_t a32 = a, b32 = b, rv32; 66 rv32 = a * b; 67 *sat = (rv32 & (3<<30)) == (3<<30); 68 return (int64_t)rv32 << 1; 69 70 :function:e500::uint64_t:ev_multiply32_smf:int32_t a, int32_t b, int *sat 71 int64_t rv64, a64 = a, b64 = b; 72 rv64 = a64 * b64; 73 *sat = (rv64 & ((int64_t)3<<62)) == ((int64_t)3<<62); 74 /* Loses top sign bit. */ 75 return rv64 << 1; 76 # 77 # SPE Saturation handling support 78 # 79 :function:e500::int32_t:ev_multiply16_ssf:int16_t a, int16_t b, int *sat 80 int32_t rv32; 81 if (a == 0xffff8000 && b == 0xffff8000) 82 { 83 rv32 = 0x7fffffffL; 84 * sat = 1; 85 return rv32; 86 } 87 else 88 { 89 int32_t a32 = a, b32 = b; 90 91 rv32 = a * b; 92 * sat = (rv32 & (3<<30)) == (3<<30); 93 return (int64_t)rv32 << 1; 94 } 95 96 :function:e500::int64_t:ev_multiply32_ssf:int32_t a, int32_t b, int *sat 97 int64_t rv64; 98 if (a == 0x80000000 && b == 0x80000000) 99 { 100 rv64 = 0x7fffffffffffffffLL; 101 * sat = 1; 102 return rv64; 103 } 104 else 105 { 106 int64_t a64 = a, b64 = b; 107 rv64 = a64 * b64; 108 *sat = (rv64 & ((int64_t)3<<62)) == ((int64_t)3<<62); 109 /* Loses top sign bit. */ 110 return rv64 << 1; 111 } 112 114 # 115 # SPE FP handling support 116 # 117 118 :function:e500::void:ev_check_guard:sim_fpu *a, int fg, int fx, cpu *processor 119 uint64_t guard; 120 guard = sim_fpu_guard(a, 0); 121 if (guard & 1) 122 EV_SET_SPEFSCR_BITS(fg); 123 if (guard & ~1) 124 EV_SET_SPEFSCR_BITS(fx); 125 126 :function:e500::void:booke_sim_fpu_32to:sim_fpu *dst, uint32_t packed 127 sim_fpu_32to (dst, packed); 128 129 /* Set normally unused fields to allow booke arithmetic. */ 130 if (dst->class == sim_fpu_class_infinity) 131 { 132 dst->normal_exp = 128; 133 dst->fraction = ((uint64_t)1 << 60); 134 } 135 else if (dst->class == sim_fpu_class_qnan 136 || dst->class == sim_fpu_class_snan) 137 { 138 dst->normal_exp = 128; 139 /* This is set, but without the implicit bit, so we have to or 140 in the implicit bit. */ 141 dst->fraction |= ((uint64_t)1 << 60); 142 } 143 144 :function:e500::int:booke_sim_fpu_add:sim_fpu *d, sim_fpu *a, sim_fpu *b, int inv, int over, int under, cpu *processor 145 int invalid_operand, overflow_result, underflow_result; 146 int dest_exp; 147 148 invalid_operand = 0; 149 overflow_result = 0; 150 underflow_result = 0; 151 152 /* Treat NaN, Inf, and denorm like normal numbers, and signal invalid 153 operand if it hasn't already been done. */ 154 if (EV_IS_INFDENORMNAN (a)) 155 { 156 a->class = sim_fpu_class_number; 157 158 EV_SET_SPEFSCR_BITS (inv); 159 invalid_operand = 1; 160 } 161 if (EV_IS_INFDENORMNAN (b)) 162 { 163 b->class = sim_fpu_class_number; 164 165 if (! invalid_operand) 166 { 167 EV_SET_SPEFSCR_BITS (inv); 168 invalid_operand = 1; 169 } 170 } 171 172 sim_fpu_add (d, a, b); 173 174 dest_exp = booke_sim_fpu_exp (d); 175 /* If this is a denorm, force to zero, and signal underflow if 176 we haven't already indicated invalid operand. */ 177 if (dest_exp <= -127) 178 { 179 int sign = d->sign; 180 181 *d = sim_fpu_zero; 182 d->sign = sign; 183 if (! invalid_operand) 184 { 185 EV_SET_SPEFSCR_BITS (under); 186 underflow_result = 1; 187 } 188 } 189 /* If this is Inf/NaN, force to pmax/nmax, and signal overflow if 190 we haven't already indicated invalid operand. */ 191 else if (dest_exp >= 127) 192 { 193 int sign = d->sign; 194 195 *d = sim_fpu_max32; 196 d->sign = sign; 197 if (! invalid_operand) 198 { 199 EV_SET_SPEFSCR_BITS (over); 200 overflow_result = 1; 201 } 202 } 203 /* Destination sign is sign of operand with larger magnitude, or 204 the sign of the first operand if operands have the same 205 magnitude. Thus if the result is zero, we force it to have 206 the sign of the first operand. */ 207 else if (d->fraction == 0) 208 d->sign = a->sign; 209 210 return invalid_operand || overflow_result || underflow_result; 211 212 :function:e500::uint32_t:ev_fs_add:uint32_t aa, uint32_t bb, int inv, int over, int under, int fg, int fx, cpu *processor 213 sim_fpu a, b, d; 214 uint32_t w; 215 int exception; 216 217 booke_sim_fpu_32to (&a, aa); 218 booke_sim_fpu_32to (&b, bb); 219 220 exception = booke_sim_fpu_add (&d, &a, &b, inv, over, under, 221 processor); 222 223 sim_fpu_to32 (&w, &d); 224 if (! exception) 225 ev_check_guard(&d, fg, fx, processor); 226 return w; 227 228 :function:e500::uint32_t:ev_fs_sub:uint32_t aa, uint32_t bb, int inv, int over, int under, int fg, int fx, cpu *processor 229 sim_fpu a, b, d; 230 uint32_t w; 231 int exception; 232 233 booke_sim_fpu_32to (&a, aa); 234 booke_sim_fpu_32to (&b, bb); 235 236 /* Invert sign of second operand, and add. */ 237 b.sign = ! b.sign; 238 exception = booke_sim_fpu_add (&d, &a, &b, inv, over, under, 239 processor); 240 241 sim_fpu_to32 (&w, &d); 242 if (! exception) 243 ev_check_guard(&d, fg, fx, processor); 244 return w; 245 246 # sim_fpu_exp leaves the normal_exp field undefined for Inf and NaN. 247 # The booke algorithms require exp values, so we fake them here. 248 # fixme: It also apparently does the same for zero, but should not. 249 :function:e500::uint32_t:booke_sim_fpu_exp:sim_fpu *x 250 int y = sim_fpu_is (x); 251 if (y == SIM_FPU_IS_PZERO || y == SIM_FPU_IS_NZERO) 252 return 0; 253 else if (y == SIM_FPU_IS_SNAN || y == SIM_FPU_IS_QNAN 254 || y == SIM_FPU_IS_NINF || y == SIM_FPU_IS_PINF) 255 return 128; 256 else 257 return sim_fpu_exp (x); 258 259 :function:e500::uint32_t:ev_fs_mul:uint32_t aa, uint32_t bb, int inv, int over, int under, int fg, int fx, cpu *processor 260 sim_fpu a, b, d; 261 uint32_t w; 262 int sa, sb, ea, eb, ei; 263 sim_fpu_32to (&a, aa); 264 sim_fpu_32to (&b, bb); 265 sa = sim_fpu_sign(&a); 266 sb = sim_fpu_sign(&b); 267 ea = booke_sim_fpu_exp(&a); 268 eb = booke_sim_fpu_exp(&b); 269 ei = ea + eb + 127; 270 if (sim_fpu_is_zero (&a) || sim_fpu_is_zero (&b)) 271 w = 0; 272 else if (sa == sb) { 273 if (ei >= 254) { 274 w = EV_PMAX; 275 EV_SET_SPEFSCR_BITS(over); 276 } else if (ei < 1) { 277 d = sim_fpu_zero; 278 sim_fpu_to32 (&w, &d); 279 w &= 0x7fffffff; /* Clear sign bit. */ 280 } else { 281 goto normal_mul; 282 } 283 } else { 284 if (ei >= 254) { 285 w = EV_NMAX; 286 EV_SET_SPEFSCR_BITS(over); 287 } else if (ei < 1) { 288 d = sim_fpu_zero; 289 sim_fpu_to32 (&w, &d); 290 w |= 0x80000000; /* Set sign bit. */ 291 } else { 292 normal_mul: 293 if (EV_IS_INFDENORMNAN(&a) || EV_IS_INFDENORMNAN(&b)) 294 EV_SET_SPEFSCR_BITS(inv); 295 sim_fpu_mul (&d, &a, &b); 296 sim_fpu_to32 (&w, &d); 297 } 298 } 299 return w; 300 301 :function:e500::uint32_t:ev_fs_div:uint32_t aa, uint32_t bb, int inv, int over, int under, int dbz, int fg, int fx, cpu *processor 302 sim_fpu a, b, d; 303 uint32_t w; 304 int sa, sb, ea, eb, ei; 305 306 sim_fpu_32to (&a, aa); 307 sim_fpu_32to (&b, bb); 308 sa = sim_fpu_sign(&a); 309 sb = sim_fpu_sign(&b); 310 ea = booke_sim_fpu_exp(&a); 311 eb = booke_sim_fpu_exp(&b); 312 ei = ea - eb + 127; 313 314 /* Special cases to handle behaviour of e500 hardware. 315 cf case 107543. */ 316 if (sim_fpu_is_nan (&a) || sim_fpu_is_nan (&b) 317 || sim_fpu_is_zero (&a) || sim_fpu_is_zero (&b)) 318 { 319 if (sim_fpu_is_snan (&a) || sim_fpu_is_snan (&b)) 320 { 321 if (bb == 0x3f800000) 322 w = EV_PMAX; 323 else if (aa == 0x7fc00001) 324 w = 0x3fbffffe; 325 else 326 goto normal_div; 327 } 328 else 329 goto normal_div; 330 } 331 else if (sim_fpu_is_infinity (&a) && sim_fpu_is_infinity (&b)) 332 { 333 if (sa == sb) 334 sim_fpu_32to (&d, 0x3f800000); 335 else 336 sim_fpu_32to (&d, 0xbf800000); 337 sim_fpu_to32 (&w, &d); 338 } 339 else if (sa == sb) { 340 if (ei > 254) { 341 w = EV_PMAX; 342 EV_SET_SPEFSCR_BITS(over); 343 } else if (ei <= 1) { 344 d = sim_fpu_zero; 345 sim_fpu_to32 (&w, &d); 346 w &= 0x7fffffff; /* Clear sign bit. */ 347 } else { 348 goto normal_div; 349 } 350 } else { 351 if (ei > 254) { 352 w = EV_NMAX; 353 EV_SET_SPEFSCR_BITS(over); 354 } else if (ei <= 1) { 355 d = sim_fpu_zero; 356 sim_fpu_to32 (&w, &d); 357 w |= 0x80000000; /* Set sign bit. */ 358 } else { 359 normal_div: 360 if (EV_IS_INFDENORMNAN(&a) || EV_IS_INFDENORMNAN(&b)) 361 EV_SET_SPEFSCR_BITS(inv); 362 if (sim_fpu_is_zero (&b)) 363 { 364 if (sim_fpu_is_zero (&a)) 365 EV_SET_SPEFSCR_BITS(dbz); 366 else 367 EV_SET_SPEFSCR_BITS(inv); 368 w = sa ? EV_NMAX : EV_PMAX; 369 } 370 else 371 { 372 sim_fpu_div (&d, &a, &b); 373 sim_fpu_to32 (&w, &d); 374 ev_check_guard(&d, fg, fx, processor); 375 } 376 } 377 } 378 return w; 379 380 382 # 383 # A.2.7 Integer SPE Simple Instructions 384 # 385 386 0.4,6.RS,11.RA,16.RB,21.512:X:e500:evaddw %RS,%RA,%RB:Vector Add Word 387 uint32_t w1, w2; 388 w1 = *rBh + *rAh; 389 w2 = *rB + *rA; 390 EV_SET_REG2(*rSh, *rS, w1, w2); 391 //printf("evaddw: *rSh = %08x; *rS = %08x; w1 = %08x w2 = %08x\n", *rSh, *rS, w1, w2); 392 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 393 394 0.4,6.RS,11.IMM,16.RB,21.514:X:e500:evaddiw %RS,%RB,%IMM:Vector Add Immediate Word 395 uint32_t w1, w2; 396 w1 = *rBh + IMM; 397 w2 = *rB + IMM; 398 EV_SET_REG2(*rSh, *rS, w1, w2); 399 //printf("evaddiw: *rSh = %08x; *rS = %08x; w1 = %08x w2 = %08x\n", *rSh, *rS, w1, w2); 400 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 401 402 0.4,6.RS,11.RA,16.RB,21.516:X:e500:evsubfw %RS,%RA,%RB:Vector Subtract from Word 403 uint32_t w1, w2; 404 w1 = *rBh - *rAh; 405 w2 = *rB - *rA; 406 EV_SET_REG2(*rSh, *rS, w1, w2); 407 //printf("evsubfw: *rSh = %08x; *rS = %08x; w1 = %08x w2 = %08x\n", *rSh, *rS, w1, w2); 408 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 409 410 0.4,6.RS,11.IMM,16.RB,21.518:X:e500:evsubifw %RS,%RB,%IMM:Vector Subtract Immediate from Word 411 uint32_t w1, w2; 412 w1 = *rBh - IMM; 413 w2 = *rB - IMM; 414 EV_SET_REG2(*rSh, *rS, w1, w2); 415 //printf("evsubifw: *rSh = %08x; *rS = %08x; IMM = %d\n", *rSh, *rS, IMM); 416 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 417 418 0.4,6.RS,11.RA,16.0,21.520:X:e500:evabs %RS,%RA:Vector Absolute Value 419 int32_t w1, w2; 420 w1 = *rAh; 421 if (w1 < 0 && w1 != 0x80000000) 422 w1 = -w1; 423 w2 = *rA; 424 if (w2 < 0 && w2 != 0x80000000) 425 w2 = -w2; 426 EV_SET_REG2(*rSh, *rS, w1, w2); 427 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 428 429 0.4,6.RS,11.RA,16.0,21.521:X:e500:evneg %RS,%RA:Vector Negate 430 int32_t w1, w2; 431 w1 = *rAh; 432 /* the negative most negative number is the most negative number */ 433 if (w1 != 0x80000000) 434 w1 = -w1; 435 w2 = *rA; 436 if (w2 != 0x80000000) 437 w2 = -w2; 438 EV_SET_REG2(*rSh, *rS, w1, w2); 439 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 440 441 0.4,6.RS,11.RA,16.0,21.522:X:e500:evextsb %RS,%RA:Vector Extend Signed Byte 442 uint64_t w1, w2; 443 w1 = *rAh & 0xff; 444 if (w1 & 0x80) 445 w1 |= 0xffffff00; 446 w2 = *rA & 0xff; 447 if (w2 & 0x80) 448 w2 |= 0xffffff00; 449 EV_SET_REG2(*rSh, *rS, w1, w2); 450 PPC_INSN_INT(RS_BITMASK, RA_BITMASK , 0); 451 452 0.4,6.RS,11.RA,16.0,21.523:X:e500:evextsb %RS,%RA:Vector Extend Signed Half Word 453 uint64_t w1, w2; 454 w1 = *rAh & 0xffff; 455 if (w1 & 0x8000) 456 w1 |= 0xffff0000; 457 w2 = *rA & 0xffff; 458 if (w2 & 0x8000) 459 w2 |= 0xffff0000; 460 EV_SET_REG2(*rSh, *rS, w1, w2); 461 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 462 463 0.4,6.RS,11.RA,16.RB,21.529:X:e500:evand %RS,%RA,%RB:Vector AND 464 uint32_t w1, w2; 465 w1 = *rBh & *rAh; 466 w2 = *rB & *rA; 467 EV_SET_REG2(*rSh, *rS, w1, w2); 468 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 469 470 0.4,6.RS,11.RA,16.RB,21.535:X:e500:evor %RS,%RA,%RB:Vector OR 471 uint32_t w1, w2; 472 w1 = *rBh | *rAh; 473 w2 = *rB | *rA; 474 EV_SET_REG2(*rSh, *rS, w1, w2); 475 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 476 477 0.4,6.RS,11.RA,16.RB,21.534:X:e500:evxor %RS,%RA,%RB:Vector XOR 478 uint32_t w1, w2; 479 w1 = *rBh ^ *rAh; 480 w2 = *rB ^ *rA; 481 EV_SET_REG2(*rSh, *rS, w1, w2); 482 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 483 484 0.4,6.RS,11.RA,16.RB,21.542:X:e500:evnand %RS,%RA,%RB:Vector NAND 485 uint32_t w1, w2; 486 w1 = ~(*rBh & *rAh); 487 w2 = ~(*rB & *rA); 488 EV_SET_REG2(*rSh, *rS, w1, w2); 489 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 490 491 0.4,6.RS,11.RA,16.RB,21.536:X:e500:evnor %RS,%RA,%RB:Vector NOR 492 uint32_t w1, w2; 493 w1 = ~(*rBh | *rAh); 494 w2 = ~(*rB | *rA); 495 EV_SET_REG2(*rSh, *rS, w1, w2); 496 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 497 498 0.4,6.RS,11.RA,16.RB,21.537:X:e500:eveqv %RS,%RA,%RB:Vector Equivalent 499 uint32_t w1, w2; 500 w1 = (~*rBh) ^ *rAh; 501 w2 = (~*rB) ^ *rA; 502 EV_SET_REG2(*rSh, *rS, w1, w2); 503 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 504 505 0.4,6.RS,11.RA,16.RB,21.530:X:e500:evandc %RS,%RA,%RB:Vector AND with Compliment 506 uint32_t w1, w2; 507 w1 = (~*rBh) & *rAh; 508 w2 = (~*rB) & *rA; 509 EV_SET_REG2(*rSh, *rS, w1, w2); 510 //printf("evandc: *rSh = %08x; *rS = %08x\n", *rSh, *rS); 511 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 512 513 0.4,6.RS,11.RA,16.RB,21.539:X:e500:evorc %RS,%RA,%RB:Vector OR with Compliment 514 uint32_t w1, w2; 515 w1 = (~*rBh) | *rAh; 516 w2 = (~*rB) | *rA; 517 EV_SET_REG2(*rSh, *rS, w1, w2); 518 //printf("evorc: *rSh = %08x; *rS = %08x\n", *rSh, *rS); 519 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 520 521 0.4,6.RS,11.RA,16.RB,21.552:X:e500:evrlw %RS,%RA,%RB:Vector Rotate Left Word 522 uint32_t nh, nl, w1, w2; 523 nh = *rBh & 0x1f; 524 nl = *rB & 0x1f; 525 w1 = ((uint32_t)*rAh) << nh | ((uint32_t)*rAh) >> (32 - nh); 526 w2 = ((uint32_t)*rA) << nl | ((uint32_t)*rA) >> (32 - nl); 527 EV_SET_REG2(*rSh, *rS, w1, w2); 528 //printf("evrlw: nh %d nl %d *rSh = %08x; *rS = %08x\n", nh, nl, *rSh, *rS); 529 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 530 531 0.4,6.RS,11.RA,16.UIMM,21.554:X:e500:evrlwi %RS,%RA,%UIMM:Vector Rotate Left Word Immediate 532 uint32_t w1, w2, imm; 533 imm = (uint32_t)UIMM; 534 w1 = ((uint32_t)*rAh) << imm | ((uint32_t)*rAh) >> (32 - imm); 535 w2 = ((uint32_t)*rA) << imm | ((uint32_t)*rA) >> (32 - imm); 536 EV_SET_REG2(*rSh, *rS, w1, w2); 537 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 538 539 0.4,6.RS,11.RA,16.RB,21.548:X:e500:evslw %RS,%RA,%RB:Vector Shift Left Word 540 uint32_t nh, nl, w1, w2; 541 nh = *rBh & 0x1f; 542 nl = *rB & 0x1f; 543 w1 = ((uint32_t)*rAh) << nh; 544 w2 = ((uint32_t)*rA) << nl; 545 EV_SET_REG2(*rSh, *rS, w1, w2); 546 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 547 548 0.4,6.RS,11.RA,16.UIMM,21.550:X:e500:evslwi %RS,%RA,%UIMM:Vector Shift Left Word Immediate 549 uint32_t w1, w2, imm = UIMM; 550 w1 = ((uint32_t)*rAh) << imm; 551 w2 = ((uint32_t)*rA) << imm; 552 EV_SET_REG2(*rSh, *rS, w1, w2); 553 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 554 555 0.4,6.RS,11.RA,16.RB,21.545:X:e500:evsrws %RS,%RA,%RB:Vector Shift Right Word Signed 556 int32_t w1, w2; 557 uint32_t nh, nl; 558 nh = *rBh & 0x1f; 559 nl = *rB & 0x1f; 560 w1 = ((int32_t)*rAh) >> nh; 561 w2 = ((int32_t)*rA) >> nl; 562 EV_SET_REG2(*rSh, *rS, w1, w2); 563 //printf("evsrws: nh %d nl %d *rSh = %08x; *rS = %08x\n", nh, nl, *rSh, *rS); 564 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 565 566 0.4,6.RS,11.RA,16.RB,21.544:X:e500:evsrwu %RS,%RA,%RB:Vector Shift Right Word Unsigned 567 uint32_t w1, w2, nh, nl; 568 nh = *rBh & 0x1f; 569 nl = *rB & 0x1f; 570 w1 = ((uint32_t)*rAh) >> nh; 571 w2 = ((uint32_t)*rA) >> nl; 572 EV_SET_REG2(*rSh, *rS, w1, w2); 573 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 574 575 0.4,6.RS,11.RA,16.UIMM,21.547:X:e500:evsrwis %RS,%RA,%UIMM:Vector Shift Right Word Immediate Signed 576 int32_t w1, w2; 577 uint32_t imm = UIMM; 578 w1 = ((int32_t)*rAh) >> imm; 579 w2 = ((int32_t)*rA) >> imm; 580 EV_SET_REG2(*rSh, *rS, w1, w2); 581 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 582 583 0.4,6.RS,11.RA,16.UIMM,21.546:X:e500:evsrwiu %RS,%RA,%UIMM:Vector Shift Right Word Immediate Unsigned 584 uint32_t w1, w2, imm = UIMM; 585 w1 = ((uint32_t)*rAh) >> imm; 586 w2 = ((uint32_t)*rA) >> imm; 587 EV_SET_REG2(*rSh, *rS, w1, w2); 588 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 589 590 0.4,6.RS,11.RA,16.0,21.525:X:e500:evcntlzw %RS,%RA:Vector Count Leading Zeros Word 591 uint32_t w1, w2, mask, c1, c2; 592 for (c1 = 0, mask = 0x80000000, w1 = *rAh; 593 !(w1 & mask) && mask != 0; mask >>= 1) 594 c1++; 595 for (c2 = 0, mask = 0x80000000, w2 = *rA; 596 !(w2 & mask) && mask != 0; mask >>= 1) 597 c2++; 598 EV_SET_REG2(*rSh, *rS, c1, c2); 599 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 600 601 0.4,6.RS,11.RA,16.0,21.526:X:e500:evcntlsw %RS,%RA:Vector Count Leading Sign Bits Word 602 uint32_t w1, w2, mask, sign_bit, c1, c2; 603 for (c1 = 0, mask = 0x80000000, w1 = *rAh, sign_bit = w1 & mask; 604 ((w1 & mask) == sign_bit) && mask != 0; 605 mask >>= 1, sign_bit >>= 1) 606 c1++; 607 for (c2 = 0, mask = 0x80000000, w2 = *rA, sign_bit = w2 & mask; 608 ((w2 & mask) == sign_bit) && mask != 0; 609 mask >>= 1, sign_bit >>= 1) 610 c2++; 611 EV_SET_REG2(*rSh, *rS, c1, c2); 612 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 613 614 0.4,6.RS,11.RA,16.0,21.524:X:e500:evrndw %RS,%RA:Vector Round Word 615 uint32_t w1, w2; 616 w1 = ((uint32_t)*rAh + 0x8000) & 0xffff0000; 617 w2 = ((uint32_t)*rA + 0x8000) & 0xffff0000; 618 EV_SET_REG2(*rSh, *rS, w1, w2); 619 //printf("evrndw: *rSh = %08x; *rS = %08x\n", *rSh, *rS); 620 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 621 622 0.4,6.RS,11.RA,16.RB,21.556:X:e500:evmergehi %RS,%RA,%RB:Vector Merge Hi 623 uint32_t w1, w2; 624 w1 = *rAh; 625 w2 = *rBh; 626 EV_SET_REG2(*rSh, *rS, w1, w2); 627 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 628 629 0.4,6.RS,11.RA,16.RB,21.557:X:e500:evmergelo %RS,%RA,%RB:Vector Merge Low 630 uint32_t w1, w2; 631 w1 = *rA; 632 w2 = *rB; 633 EV_SET_REG2(*rSh, *rS, w1, w2); 634 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 635 636 0.4,6.RS,11.RA,16.RB,21.559:X:e500:evmergelohi %RS,%RA,%RB:Vector Merge Low Hi 637 uint32_t w1, w2; 638 w1 = *rA; 639 w2 = *rBh; 640 EV_SET_REG2(*rSh, *rS, w1, w2); 641 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 642 643 0.4,6.RS,11.RA,16.RB,21.558:X:e500:evmergehilo %RS,%RA,%RB:Vector Merge Hi Low 644 uint32_t w1, w2; 645 w1 = *rAh; 646 w2 = *rB; 647 EV_SET_REG2(*rSh, *rS, w1, w2); 648 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 649 650 0.4,6.RS,11.SIMM,16.0,21.553:X:e500:evsplati %RS,%SIMM:Vector Splat Immediate 651 uint32_t w; 652 w = SIMM & 0x1f; 653 if (w & 0x10) 654 w |= 0xffffffe0; 655 EV_SET_REG2(*rSh, *rS, w, w); 656 PPC_INSN_INT(RS_BITMASK, 0, 0); 657 658 0.4,6.RS,11.SIMM,16.0,21.555:X:e500:evsplatfi %RS,%SIMM:Vector Splat Fractional Immediate 659 uint32_t w; 660 w = SIMM << 27; 661 EV_SET_REG2(*rSh, *rS, w, w); 662 PPC_INSN_INT(RS_BITMASK, 0, 0); 663 664 0.4,6.BF,9.0,11.RA,16.RB,21.561:X:e500:evcmpgts %BF,%RA,%RB:Vector Compare Greater Than Signed 665 int32_t ah, al, bh, bl; 666 int w, ch, cl; 667 ah = *rAh; 668 al = *rA; 669 bh = *rBh; 670 bl = *rB; 671 if (ah > bh) 672 ch = 1; 673 else 674 ch = 0; 675 if (al > bl) 676 cl = 1; 677 else 678 cl = 0; 679 w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 680 CR_SET(BF, w); 681 PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 682 683 0.4,6.BF,9.0,11.RA,16.RB,21.560:X:e500:evcmpgtu %BF,%RA,%RB:Vector Compare Greater Than Unsigned 684 uint32_t ah, al, bh, bl; 685 int w, ch, cl; 686 ah = *rAh; 687 al = *rA; 688 bh = *rBh; 689 bl = *rB; 690 if (ah > bh) 691 ch = 1; 692 else 693 ch = 0; 694 if (al > bl) 695 cl = 1; 696 else 697 cl = 0; 698 w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 699 CR_SET(BF, w); 700 PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 701 702 0.4,6.BF,9.0,11.RA,16.RB,21.563:X:e500:evcmplts %BF,%RA,%RB:Vector Compare Less Than Signed 703 int32_t ah, al, bh, bl; 704 int w, ch, cl; 705 ah = *rAh; 706 al = *rA; 707 bh = *rBh; 708 bl = *rB; 709 if (ah < bh) 710 ch = 1; 711 else 712 ch = 0; 713 if (al < bl) 714 cl = 1; 715 else 716 cl = 0; 717 w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 718 CR_SET(BF, w); 719 PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 720 721 0.4,6.BF,9.0,11.RA,16.RB,21.562:X:e500:evcmpltu %BF,%RA,%RB:Vector Compare Less Than Unsigned 722 uint32_t ah, al, bh, bl; 723 int w, ch, cl; 724 ah = *rAh; 725 al = *rA; 726 bh = *rBh; 727 bl = *rB; 728 if (ah < bh) 729 ch = 1; 730 else 731 ch = 0; 732 if (al < bl) 733 cl = 1; 734 else 735 cl = 0; 736 w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 737 CR_SET(BF, w); 738 PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 739 740 0.4,6.BF,9.0,11.RA,16.RB,21.564:X:e500:evcmpeq %BF,%RA,%RB:Vector Compare Equal 741 uint32_t ah, al, bh, bl; 742 int w, ch, cl; 743 ah = *rAh; 744 al = *rA; 745 bh = *rBh; 746 bl = *rB; 747 if (ah == bh) 748 ch = 1; 749 else 750 ch = 0; 751 if (al == bl) 752 cl = 1; 753 else 754 cl = 0; 755 w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 756 CR_SET(BF, w); 757 //printf("evcmpeq: ch %d cl %d BF %d, CR is now %08x\n", ch, cl, BF, CR); 758 PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 759 760 0.4,6.RS,11.RA,16.RB,21.79,29.CRFS:X:e500:evsel %RS,%RA,%RB,%CRFS:Vector Select 761 uint32_t w1, w2; 762 int cr; 763 cr = CR_FIELD(CRFS); 764 if (cr & 8) 765 w1 = *rAh; 766 else 767 w1 = *rBh; 768 if (cr & 4) 769 w2 = *rA; 770 else 771 w2 = *rB; 772 EV_SET_REG2(*rSh, *rS, w1, w2); 773 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 774 775 0.4,6.RS,11.RA,16.RB,21.527:X:e500:brinc %RS,%RA,%RB:Bit Reversed Increment 776 uint32_t w1, w2, a, d, mask; 777 mask = (*rB) & 0xffff; 778 a = (*rA) & 0xffff; 779 d = EV_BITREVERSE16(1 + EV_BITREVERSE16(a | ~mask)); 780 *rS = ((*rA) & 0xffff0000) | (d & 0xffff); 781 //printf("brinc: *rS = %08x\n", *rS); 782 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 783 784 # 785 # A.2.8 Integer SPE Complex Instructions 786 # 787 788 0.4,6.RS,11.RA,16.RB,21.1031:EVX:e500:evmhossf %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional 789 int16_t al, ah, bl, bh; 790 int32_t tl, th; 791 int movl, movh; 792 793 al = (int16_t) EV_LOHALF (*rA); 794 ah = (int16_t) EV_LOHALF (*rAh); 795 bl = (int16_t) EV_LOHALF (*rB); 796 bh = (int16_t) EV_LOHALF (*rBh); 797 tl = ev_multiply16_ssf (al, bl, &movl); 798 th = ev_multiply16_ssf (ah, bh, &movh); 799 EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th), 800 EV_SATURATE (movl, 0x7fffffff, tl)); 801 EV_SET_SPEFSCR_OV (movl, movh); 802 PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 803 804 0.4,6.RS,11.RA,16.RB,21.1063:EVX:e500:evmhossfa %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional Accumulate 805 int16_t al, ah, bl, bh; 806 int32_t tl, th; 807 int movl, movh; 808 809 al = (int16_t) EV_LOHALF (*rA); 810 ah = (int16_t) EV_LOHALF (*rAh); 811 bl = (int16_t) EV_LOHALF (*rB); 812 bh = (int16_t) EV_LOHALF (*rBh); 813 tl = ev_multiply16_ssf (al, bl, &movl); 814 th = ev_multiply16_ssf (ah, bh, &movh); 815 EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th), 816 EV_SATURATE (movl, 0x7fffffff, tl)); 817 EV_SET_SPEFSCR_OV (movl, movh); 818 PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 819 820 0.4,6.RS,11.RA,16.RB,21.1039:EVX:e500:evmhosmf %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional 821 int16_t al, ah, bl, bh; 822 int32_t tl, th; 823 int dummy; 824 825 al = (int16_t) EV_LOHALF (*rA); 826 ah = (int16_t) EV_LOHALF (*rAh); 827 bl = (int16_t) EV_LOHALF (*rB); 828 bh = (int16_t) EV_LOHALF (*rBh); 829 tl = ev_multiply16_smf (al, bl, & dummy); 830 th = ev_multiply16_smf (ah, bh, & dummy); 831 EV_SET_REG2 (*rSh, *rS, th, tl); 832 PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 833 834 0.4,6.RS,11.RA,16.RB,21.1071:EVX:e500:evmhosmfa %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional Accumulate 835 int32_t al, ah, bl, bh; 836 int32_t tl, th; 837 int dummy; 838 839 al = (int16_t) EV_LOHALF (*rA); 840 ah = (int16_t) EV_LOHALF (*rAh); 841 bl = (int16_t) EV_LOHALF (*rB); 842 bh = (int16_t) EV_LOHALF (*rBh); 843 tl = ev_multiply16_smf (al, bl, & dummy); 844 th = ev_multiply16_smf (ah, bh, & dummy); 845 EV_SET_REG2_ACC (*rSh, *rS, th, tl); 846 PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 847 848 0.4,6.RS,11.RA,16.RB,21.1037:EVX:e500:evmhosmi %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer 849 int32_t al, ah, bl, bh, tl, th; 850 al = (int32_t)(int16_t)EV_LOHALF(*rA); 851 ah = (int32_t)(int16_t)EV_LOHALF(*rAh); 852 bl = (int32_t)(int16_t)EV_LOHALF(*rB); 853 bh = (int32_t)(int16_t)EV_LOHALF(*rBh); 854 tl = al * bl; 855 th = ah * bh; 856 EV_SET_REG2(*rSh, *rS, th, tl); 857 //printf("evmhosmi: *rSh = %08x; *rS = %08x\n", *rSh, *rS); 858 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 859 860 0.4,6.RS,11.RA,16.RB,21.1069:EVX:e500:evmhosmia %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer Accumulate 861 int32_t al, ah, bl, bh, tl, th; 862 al = (int32_t)(int16_t)EV_LOHALF(*rA); 863 ah = (int32_t)(int16_t)EV_LOHALF(*rAh); 864 bl = (int32_t)(int16_t)EV_LOHALF(*rB); 865 bh = (int32_t)(int16_t)EV_LOHALF(*rBh); 866 tl = al * bl; 867 th = ah * bh; 868 EV_SET_REG2_ACC(*rSh, *rS, th, tl); 869 //printf("evmhosmia: ACC = %08x; *rSh = %08x; *rS = %08x\n", ACC, *rSh, *rS); 870 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 871 872 0.4,6.RS,11.RA,16.RB,21.1036:EVX:e500:evmhoumi %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer 873 uint32_t al, ah, bl, bh, tl, th; 874 al = (uint32_t)(uint16_t)EV_LOHALF(*rA); 875 ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh); 876 bl = (uint32_t)(uint16_t)EV_LOHALF(*rB); 877 bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh); 878 tl = al * bl; 879 th = ah * bh; 880 EV_SET_REG2(*rSh, *rS, th, tl); 881 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 882 883 0.4,6.RS,11.RA,16.RB,21.1068:EVX:e500:evmhoumia %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer Accumulate 884 uint32_t al, ah, bl, bh, tl, th; 885 al = (uint32_t)(uint16_t)EV_LOHALF(*rA); 886 ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh); 887 bl = (uint32_t)(uint16_t)EV_LOHALF(*rB); 888 bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh); 889 tl = al * bl; 890 th = ah * bh; 891 EV_SET_REG2_ACC(*rSh, *rS, th, tl); 892 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 893 894 0.4,6.RS,11.RA,16.RB,21.1027:EVX:e500:evmhessf %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional 895 int16_t al, ah, bl, bh; 896 int32_t tl, th; 897 int movl, movh; 898 899 al = (int16_t) EV_HIHALF (*rA); 900 ah = (int16_t) EV_HIHALF (*rAh); 901 bl = (int16_t) EV_HIHALF (*rB); 902 bh = (int16_t) EV_HIHALF (*rBh); 903 tl = ev_multiply16_ssf (al, bl, &movl); 904 th = ev_multiply16_ssf (ah, bh, &movh); 905 EV_SET_REG2 (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th), 906 EV_SATURATE (movl, 0x7fffffff, tl)); 907 EV_SET_SPEFSCR_OV (movl, movh); 908 PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 909 910 0.4,6.RS,11.RA,16.RB,21.1059:EVX:e500:evmhessfa %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional Accumulate 911 int16_t al, ah, bl, bh; 912 int32_t tl, th; 913 int movl, movh; 914 915 al = (int16_t) EV_HIHALF (*rA); 916 ah = (int16_t) EV_HIHALF (*rAh); 917 bl = (int16_t) EV_HIHALF (*rB); 918 bh = (int16_t) EV_HIHALF (*rBh); 919 tl = ev_multiply16_ssf (al, bl, &movl); 920 th = ev_multiply16_ssf (ah, bh, &movh); 921 EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE (movh, 0x7fffffff, th), 922 EV_SATURATE (movl, 0x7fffffff, tl)); 923 EV_SET_SPEFSCR_OV (movl, movh); 924 PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 925 926 0.4,6.RS,11.RA,16.RB,21.1035:EVX:e500:evmhesmf %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional 927 int16_t al, ah, bl, bh; 928 int64_t tl, th; 929 int movl, movh; 930 931 al = (int16_t) EV_HIHALF (*rA); 932 ah = (int16_t) EV_HIHALF (*rAh); 933 bl = (int16_t) EV_HIHALF (*rB); 934 bh = (int16_t) EV_HIHALF (*rBh); 935 tl = ev_multiply16_smf (al, bl, &movl); 936 th = ev_multiply16_smf (ah, bh, &movh); 937 EV_SET_REG2 (*rSh, *rS, th, tl); 938 EV_SET_SPEFSCR_OV (movl, movh); 939 PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 940 941 0.4,6.RS,11.RA,16.RB,21.1067:EVX:e500:evmhesmfa %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional Accumulate 942 int16_t al, ah, bl, bh; 943 int32_t tl, th; 944 int dummy; 945 946 al = (int16_t) EV_HIHALF (*rA); 947 ah = (int16_t) EV_HIHALF (*rAh); 948 bl = (int16_t) EV_HIHALF (*rB); 949 bh = (int16_t) EV_HIHALF (*rBh); 950 tl = ev_multiply16_smf (al, bl, & dummy); 951 th = ev_multiply16_smf (ah, bh, & dummy); 952 EV_SET_REG2_ACC (*rSh, *rS, th, tl); 953 PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 954 955 0.4,6.RS,11.RA,16.RB,21.1033:EVX:e500:evmhesmi %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer 956 int16_t al, ah, bl, bh; 957 int32_t tl, th; 958 959 al = (int16_t) EV_HIHALF (*rA); 960 ah = (int16_t) EV_HIHALF (*rAh); 961 bl = (int16_t) EV_HIHALF (*rB); 962 bh = (int16_t) EV_HIHALF (*rBh); 963 tl = al * bl; 964 th = ah * bh; 965 EV_SET_REG2 (*rSh, *rS, th, tl); 966 PPC_INSN_INT (RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 967 968 0.4,6.RS,11.RA,16.RB,21.1065:EVX:e500:evmhesmia %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer Accumulate 969 int32_t al, ah, bl, bh, tl, th; 970 al = (int32_t)(int16_t)EV_HIHALF(*rA); 971 ah = (int32_t)(int16_t)EV_HIHALF(*rAh); 972 bl = (int32_t)(int16_t)EV_HIHALF(*rB); 973 bh = (int32_t)(int16_t)EV_HIHALF(*rBh); 974 tl = al * bl; 975 th = ah * bh; 976 EV_SET_REG2_ACC(*rSh, *rS, th, tl); 977 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 978 979 0.4,6.RS,11.RA,16.RB,21.1032:EVX:e500:evmheumi %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer 980 uint32_t al, ah, bl, bh, tl, th; 981 al = (uint32_t)(uint16_t)EV_HIHALF(*rA); 982 ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh); 983 bl = (uint32_t)(uint16_t)EV_HIHALF(*rB); 984 bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh); 985 tl = al * bl; 986 th = ah * bh; 987 EV_SET_REG2(*rSh, *rS, th, tl); 988 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 989 990 0.4,6.RS,11.RA,16.RB,21.1064:EVX:e500:evmheumia %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer Accumulate 991 uint32_t al, ah, bl, bh, tl, th; 992 al = (uint32_t)(uint16_t)EV_HIHALF(*rA); 993 ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh); 994 bl = (uint32_t)(uint16_t)EV_HIHALF(*rB); 995 bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh); 996 tl = al * bl; 997 th = ah * bh; 998 EV_SET_REG2_ACC(*rSh, *rS, th, tl); 999 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1000 1001 0.4,6.RS,11.RA,16.RB,21.1287:EVX:e500:evmhossfaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional and Accumulate into Words 1002 int16_t al, ah, bl, bh; 1003 int32_t t1, t2; 1004 int64_t tl, th; 1005 int movl, movh, ovl, ovh; 1006 1007 al = (int16_t) EV_LOHALF (*rA); 1008 ah = (int16_t) EV_LOHALF (*rAh); 1009 bl = (int16_t) EV_LOHALF (*rB); 1010 bh = (int16_t) EV_LOHALF (*rBh); 1011 t1 = ev_multiply16_ssf (ah, bh, &movh); 1012 t2 = ev_multiply16_ssf (al, bl, &movl); 1013 th = EV_ACCHIGH + EV_SATURATE (movh, 0x7fffffff, t1); 1014 tl = EV_ACCLOW + EV_SATURATE (movl, 0x7fffffff, t2); 1015 ovh = EV_SAT_P_S32 (th); 1016 ovl = EV_SAT_P_S32 (tl); 1017 EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE_ACC (ovh, th, 0x80000000, 0x7fffffff, th), 1018 EV_SATURATE_ACC (ovl, tl, 0x80000000, 0x7fffffff, tl)); 1019 EV_SET_SPEFSCR_OV (movl | ovl, movh | ovh); 1020 PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1021 1022 0.4,6.RS,11.RA,16.RB,21.1285:EVX:e500:evmhossiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Integer and Accumulate into Words 1023 int32_t al, ah, bl, bh; 1024 int64_t t1, t2, tl, th; 1025 int ovl, ovh; 1026 al = (int32_t)(int16_t)EV_LOHALF(*rA); 1027 ah = (int32_t)(int16_t)EV_LOHALF(*rAh); 1028 bl = (int32_t)(int16_t)EV_LOHALF(*rB); 1029 bh = (int32_t)(int16_t)EV_LOHALF(*rBh); 1030 t1 = ah * bh; 1031 t2 = al * bl; 1032 th = EV_ACCHIGH + t1; 1033 tl = EV_ACCLOW + t2; 1034 ovh = EV_SAT_P_S32(th); 1035 ovl = EV_SAT_P_S32(tl); 1036 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), 1037 EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); 1038 //printf("evmhossiaaw: ovh %d ovl %d al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", ovh, ovl, al, ah, bl, bh, t1, t2, tl, th); 1039 //printf("evmhossiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 1040 EV_SET_SPEFSCR_OV(ovl, ovh); 1041 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1042 1043 0.4,6.RS,11.RA,16.RB,21.1295:EVX:e500:evmhosmfaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional and Accumulate into Words 1044 int32_t al, ah, bl, bh; 1045 int64_t t1, t2, tl, th; 1046 al = (int32_t)(int16_t)EV_LOHALF(*rA); 1047 ah = (int32_t)(int16_t)EV_LOHALF(*rAh); 1048 bl = (int32_t)(int16_t)EV_LOHALF(*rB); 1049 bh = (int32_t)(int16_t)EV_LOHALF(*rBh); 1050 t1 = ((int64_t)ah * bh) << 1; 1051 t2 = ((int64_t)al * bl) << 1; 1052 th = EV_ACCHIGH + (t1 & 0xffffffff); 1053 tl = EV_ACCLOW + (t2 & 0xffffffff); 1054 EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 1055 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1056 1057 0.4,6.RS,11.RA,16.RB,21.1293:EVX:e500:evmhosmiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer and Accumulate into Words 1058 int32_t al, ah, bl, bh; 1059 int64_t t1, t2, tl, th; 1060 al = (int32_t)(int16_t)EV_LOHALF(*rA); 1061 ah = (int32_t)(int16_t)EV_LOHALF(*rAh); 1062 bl = (int32_t)(int16_t)EV_LOHALF(*rB); 1063 bh = (int32_t)(int16_t)EV_LOHALF(*rBh); 1064 t1 = ah * bh; 1065 t2 = al * bl; 1066 th = EV_ACCHIGH + t1; 1067 tl = EV_ACCLOW + t2; 1068 EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 1069 //printf("evmhosmiaaw: al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", al, ah, bl, bh, t1, t2, tl, th); 1070 //printf("evmhosmiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 1071 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1072 1073 0.4,6.RS,11.RA,16.RB,21.1284:EVX:e500:evmhousiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Saturate Integer and Accumulate into Words 1074 uint32_t al, ah, bl, bh; 1075 uint64_t t1, t2; 1076 int64_t tl, th; 1077 int ovl, ovh; 1078 al = (uint32_t)(uint16_t)EV_LOHALF(*rA); 1079 ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh); 1080 bl = (uint32_t)(uint16_t)EV_LOHALF(*rB); 1081 bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh); 1082 t1 = ah * bh; 1083 t2 = al * bl; 1084 th = (int64_t)EV_ACCHIGH + (int64_t)t1; 1085 tl = (int64_t)EV_ACCLOW + (int64_t)t2; 1086 ovh = EV_SAT_P_U32(th); 1087 ovl = EV_SAT_P_U32(tl); 1088 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th), 1089 EV_SATURATE_ACC(ovl, tl, 0, 0xffffffff, tl)); 1090 //printf("evmhousiaaw: al %u ah %u bl %u bh %u t1 %qu t2 %qu tl %qu th %qu\n", al, ah, bl, bh, t1, t2, tl, th); 1091 //printf("evmhousiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 1092 EV_SET_SPEFSCR_OV(ovl, ovh); 1093 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1094 1095 0.4,6.RS,11.RA,16.RB,21.1292:EVX:e500:evmhoumiaaw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer and Accumulate into Words 1096 uint32_t al, ah, bl, bh; 1097 uint32_t t1, t2; 1098 int64_t tl, th; 1099 al = (uint32_t)(uint16_t)EV_LOHALF(*rA); 1100 ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh); 1101 bl = (uint32_t)(uint16_t)EV_LOHALF(*rB); 1102 bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh); 1103 t1 = ah * bh; 1104 t2 = al * bl; 1105 th = EV_ACCHIGH + t1; 1106 tl = EV_ACCLOW + t2; 1107 EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 1108 //printf("evmhoumiaaw: al %u ah %u bl %u bh %u t1 %qu t2 %qu tl %qu th %qu\n", al, ah, bl, bh, t1, t2, tl, th); 1109 //printf("evmhoumiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 1110 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1111 1112 0.4,6.RS,11.RA,16.RB,21.1283:EVX:e500:evmhessfaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional and Accumulate into Words 1113 int16_t al, ah, bl, bh; 1114 int32_t t1, t2; 1115 int64_t tl, th; 1116 int movl, movh, ovl, ovh; 1117 1118 al = (int16_t) EV_HIHALF (*rA); 1119 ah = (int16_t) EV_HIHALF (*rAh); 1120 bl = (int16_t) EV_HIHALF (*rB); 1121 bh = (int16_t) EV_HIHALF (*rBh); 1122 t1 = ev_multiply16_ssf (ah, bh, &movh); 1123 t2 = ev_multiply16_ssf (al, bl, &movl); 1124 th = EV_ACCHIGH + EV_SATURATE (movh, 0x7fffffff, t1); 1125 tl = EV_ACCLOW + EV_SATURATE (movl, 0x7fffffff, t2); 1126 ovh = EV_SAT_P_S32 (th); 1127 ovl = EV_SAT_P_S32 (tl); 1128 EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE_ACC (ovh, th, 0x80000000, 0x7fffffff, th), 1129 EV_SATURATE_ACC (ovl, tl, 0x80000000, 0x7fffffff, tl)); 1130 EV_SET_SPEFSCR_OV (movl | ovl, movh | ovh); 1131 PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1132 1133 0.4,6.RS,11.RA,16.RB,21.1281:EVX:e500:evmhessiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Integer and Accumulate into Words 1134 int32_t al, ah, bl, bh; 1135 int64_t t1, t2, tl, th; 1136 int ovl, ovh; 1137 al = (int32_t)(int16_t)EV_HIHALF(*rA); 1138 ah = (int32_t)(int16_t)EV_HIHALF(*rAh); 1139 bl = (int32_t)(int16_t)EV_HIHALF(*rB); 1140 bh = (int32_t)(int16_t)EV_HIHALF(*rBh); 1141 t1 = ah * bh; 1142 t2 = al * bl; 1143 th = EV_ACCHIGH + t1; 1144 tl = EV_ACCLOW + t2; 1145 ovh = EV_SAT_P_S32(th); 1146 ovl = EV_SAT_P_S32(tl); 1147 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), 1148 EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); 1149 //printf("evmhessiaaw: ovh %d ovl %d al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", ovh, ovl, al, ah, bl, bh, t1, t2, tl, th); 1150 //printf("evmhessiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 1151 EV_SET_SPEFSCR_OV(ovl, ovh); 1152 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1153 1154 0.4,6.RS,11.RA,16.RB,21.1291:EVX:e500:evmhesmfaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional and Accumulate into Words 1155 int16_t al, ah, bl, bh; 1156 int32_t t1, t2, th, tl; 1157 int dummy; 1158 1159 al = (int16_t)EV_HIHALF(*rA); 1160 ah = (int16_t)EV_HIHALF(*rAh); 1161 bl = (int16_t)EV_HIHALF(*rB); 1162 bh = (int16_t)EV_HIHALF(*rBh); 1163 t1 = ev_multiply16_smf (ah, bh, &dummy); 1164 t2 = ev_multiply16_smf (al, bl, &dummy); 1165 th = EV_ACCHIGH + t1; 1166 tl = EV_ACCLOW + t2; 1167 EV_SET_REG2_ACC(*rSh, *rS, th, tl); 1168 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1169 1170 0.4,6.RS,11.RA,16.RB,21.1289:EVX:e500:evmhesmiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer and Accumulate into Words 1171 int32_t al, ah, bl, bh; 1172 int64_t t1, t2, tl, th; 1173 al = (int32_t)(int16_t)EV_HIHALF(*rA); 1174 ah = (int32_t)(int16_t)EV_HIHALF(*rAh); 1175 bl = (int32_t)(int16_t)EV_HIHALF(*rB); 1176 bh = (int32_t)(int16_t)EV_HIHALF(*rBh); 1177 t1 = ah * bh; 1178 t2 = al * bl; 1179 th = EV_ACCHIGH + t1; 1180 tl = EV_ACCLOW + t2; 1181 EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 1182 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1183 1184 0.4,6.RS,11.RA,16.RB,21.1280:EVX:e500:evmheusiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Saturate Integer and Accumulate into Words 1185 uint32_t al, ah, bl, bh; 1186 uint64_t t1, t2; 1187 int64_t tl, th; 1188 int ovl, ovh; 1189 al = (uint32_t)(uint16_t)EV_HIHALF(*rA); 1190 ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh); 1191 bl = (uint32_t)(uint16_t)EV_HIHALF(*rB); 1192 bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh); 1193 t1 = ah * bh; 1194 t2 = al * bl; 1195 th = (int64_t)EV_ACCHIGH + (int64_t)t1; 1196 tl = (int64_t)EV_ACCLOW + (int64_t)t2; 1197 ovh = EV_SAT_P_U32(th); 1198 ovl = EV_SAT_P_U32(tl); 1199 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th), 1200 EV_SATURATE_ACC(ovl, tl, 0, 0xffffffff, tl)); 1201 EV_SET_SPEFSCR_OV(ovl, ovh); 1202 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1203 1204 0.4,6.RS,11.RA,16.RB,21.1288:EVX:e500:evmheumiaaw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer and Accumulate into Words 1205 uint32_t al, ah, bl, bh; 1206 uint32_t t1, t2; 1207 uint64_t tl, th; 1208 al = (uint32_t)(uint16_t)EV_HIHALF(*rA); 1209 ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh); 1210 bl = (uint32_t)(uint16_t)EV_HIHALF(*rB); 1211 bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh); 1212 t1 = ah * bh; 1213 t2 = al * bl; 1214 th = EV_ACCHIGH + t1; 1215 tl = EV_ACCLOW + t2; 1216 EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 1217 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1218 1219 1220 0.4,6.RS,11.RA,16.RB,21.1415:EVX:e500:evmhossfanw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Fractional and Accumulate Negative into Words 1221 int16_t al, ah, bl, bh; 1222 int32_t t1, t2; 1223 int64_t tl, th; 1224 int movl, movh, ovl, ovh; 1225 1226 al = (int16_t) EV_LOHALF (*rA); 1227 ah = (int16_t) EV_LOHALF (*rAh); 1228 bl = (int16_t) EV_LOHALF (*rB); 1229 bh = (int16_t) EV_LOHALF (*rBh); 1230 t1 = ev_multiply16_ssf (ah, bh, &movh); 1231 t2 = ev_multiply16_ssf (al, bl, &movl); 1232 th = EV_ACCHIGH - EV_SATURATE (movh, 0x7fffffff, t1); 1233 tl = EV_ACCLOW - EV_SATURATE (movl, 0x7fffffff, t2); 1234 ovh = EV_SAT_P_S32 (th); 1235 ovl = EV_SAT_P_S32 (tl); 1236 EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE_ACC (ovh, th, 0x80000000, 0x7fffffff, th), 1237 EV_SATURATE_ACC (ovl, tl, 0x80000000, 0x7fffffff, tl)); 1238 EV_SET_SPEFSCR_OV (movl | ovl, movh | ovh); 1239 PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1240 1241 0.4,6.RS,11.RA,16.RB,21.1413:EVX:e500:evmhossianw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Saturate Integer and Accumulate Negative into Words 1242 int32_t al, ah, bl, bh; 1243 int64_t t1, t2, tl, th; 1244 int ovl, ovh; 1245 al = (int32_t)(int16_t)EV_LOHALF(*rA); 1246 ah = (int32_t)(int16_t)EV_LOHALF(*rAh); 1247 bl = (int32_t)(int16_t)EV_LOHALF(*rB); 1248 bh = (int32_t)(int16_t)EV_LOHALF(*rBh); 1249 t1 = ah * bh; 1250 t2 = al * bl; 1251 th = EV_ACCHIGH - t1; 1252 tl = EV_ACCLOW - t2; 1253 ovh = EV_SAT_P_S32(th); 1254 ovl = EV_SAT_P_S32(tl); 1255 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), 1256 EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); 1257 EV_SET_SPEFSCR_OV(ovl, ovh); 1258 //printf("evmhossianw: ACC = %08x; *rSh = %08x; *rS = %08x\n", ACC, *rSh, *rS); 1259 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1260 1261 0.4,6.RS,11.RA,16.RB,21.1423:EVX:e500:evmhosmfanw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Fractional and Accumulate Negative into Words 1262 int32_t al, ah, bl, bh; 1263 int64_t t1, t2, tl, th; 1264 al = (int32_t)(int16_t)EV_LOHALF(*rA); 1265 ah = (int32_t)(int16_t)EV_LOHALF(*rAh); 1266 bl = (int32_t)(int16_t)EV_LOHALF(*rB); 1267 bh = (int32_t)(int16_t)EV_LOHALF(*rBh); 1268 t1 = ((int64_t)ah * bh) << 1; 1269 t2 = ((int64_t)al * bl) << 1; 1270 th = EV_ACCHIGH - (t1 & 0xffffffff); 1271 tl = EV_ACCLOW - (t2 & 0xffffffff); 1272 EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 1273 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1274 1275 0.4,6.RS,11.RA,16.RB,21.1421:EVX:e500:evmhosmianw %RS,%RA,%RB:Vector Multiply Half Words Odd Signed Modulo Integer and Accumulate Negative into Words 1276 int32_t al, ah, bl, bh; 1277 int64_t t1, t2, tl, th; 1278 al = (int32_t)(int16_t)EV_LOHALF(*rA); 1279 ah = (int32_t)(int16_t)EV_LOHALF(*rAh); 1280 bl = (int32_t)(int16_t)EV_LOHALF(*rB); 1281 bh = (int32_t)(int16_t)EV_LOHALF(*rBh); 1282 t1 = ah * bh; 1283 t2 = al * bl; 1284 th = EV_ACCHIGH - t1; 1285 tl = EV_ACCLOW - t2; 1286 EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 1287 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1288 1289 0.4,6.RS,11.RA,16.RB,21.1412:EVX:e500:evmhousianw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Saturate Integer and Accumulate Negative into Words 1290 uint32_t al, ah, bl, bh; 1291 uint64_t t1, t2; 1292 int64_t tl, th; 1293 int ovl, ovh; 1294 al = (uint32_t)(uint16_t)EV_LOHALF(*rA); 1295 ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh); 1296 bl = (uint32_t)(uint16_t)EV_LOHALF(*rB); 1297 bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh); 1298 t1 = ah * bh; 1299 t2 = al * bl; 1300 th = (int64_t)EV_ACCHIGH - (int64_t)t1; 1301 tl = (int64_t)EV_ACCLOW - (int64_t)t2; 1302 ovl = EV_SAT_P_U32(tl); 1303 ovh = EV_SAT_P_U32(th); 1304 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th), 1305 EV_SATURATE_ACC(ovl, tl, 0, 0xffffffff, tl)); 1306 //printf("evmhousianw: ovh %d ovl %d al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", ovh, ovl, al, ah, bl, bh, t1, t2, tl, th); 1307 //printf("evmoussianw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 1308 EV_SET_SPEFSCR_OV(ovl, ovh); 1309 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1310 1311 0.4,6.RS,11.RA,16.RB,21.1420:EVX:e500:evmhoumianw %RS,%RA,%RB:Vector Multiply Half Words Odd Unsigned Modulo Integer and Accumulate Negative into Words 1312 uint32_t al, ah, bl, bh; 1313 uint32_t t1, t2; 1314 uint64_t tl, th; 1315 al = (uint32_t)(uint16_t)EV_LOHALF(*rA); 1316 ah = (uint32_t)(uint16_t)EV_LOHALF(*rAh); 1317 bl = (uint32_t)(uint16_t)EV_LOHALF(*rB); 1318 bh = (uint32_t)(uint16_t)EV_LOHALF(*rBh); 1319 t1 = ah * bh; 1320 t2 = al * bl; 1321 th = EV_ACCHIGH - t1; 1322 tl = EV_ACCLOW - t2; 1323 EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 1324 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1325 1326 0.4,6.RS,11.RA,16.RB,21.1411:EVX:e500:evmhessfanw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Fractional and Accumulate Negative into Words 1327 int16_t al, ah, bl, bh; 1328 int32_t t1, t2; 1329 int64_t tl, th; 1330 int movl, movh, ovl, ovh; 1331 1332 al = (int16_t) EV_HIHALF (*rA); 1333 ah = (int16_t) EV_HIHALF (*rAh); 1334 bl = (int16_t) EV_HIHALF (*rB); 1335 bh = (int16_t) EV_HIHALF (*rBh); 1336 t1 = ev_multiply16_ssf (ah, bh, &movh); 1337 t2 = ev_multiply16_ssf (al, bl, &movl); 1338 th = EV_ACCHIGH - EV_SATURATE (movh, 0x7fffffff, t1); 1339 tl = EV_ACCLOW - EV_SATURATE (movl, 0x7fffffff, t2); 1340 ovh = EV_SAT_P_S32 (th); 1341 ovl = EV_SAT_P_S32 (tl); 1342 EV_SET_REG2_ACC (*rSh, *rS, EV_SATURATE_ACC (ovh, th, 0x80000000, 0x7fffffff, th), 1343 EV_SATURATE_ACC (ovl, tl, 0x80000000, 0x7fffffff, tl)); 1344 EV_SET_SPEFSCR_OV (movl | ovl, movh | ovh); 1345 PPC_INSN_INT_SPR (RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1346 1347 0.4,6.RS,11.RA,16.RB,21.1409:EVX:e500:evmhessianw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Saturate Integer and Accumulate Negative into Words 1348 int32_t al, ah, bl, bh; 1349 int64_t t1, t2, tl, th; 1350 int ovl, ovh; 1351 al = (int32_t)(int16_t)EV_HIHALF(*rA); 1352 ah = (int32_t)(int16_t)EV_HIHALF(*rAh); 1353 bl = (int32_t)(int16_t)EV_HIHALF(*rB); 1354 bh = (int32_t)(int16_t)EV_HIHALF(*rBh); 1355 t1 = ah * bh; 1356 t2 = al * bl; 1357 th = EV_ACCHIGH - t1; 1358 tl = EV_ACCLOW - t2; 1359 ovh = EV_SAT_P_S32(th); 1360 ovl = EV_SAT_P_S32(tl); 1361 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), 1362 EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); 1363 EV_SET_SPEFSCR_OV(ovl, ovh); 1364 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1365 1366 0.4,6.RS,11.RA,16.RB,21.1419:EVX:e500:evmhesmfanw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Fractional and Accumulate Negative into Words 1367 int32_t al, ah, bl, bh; 1368 int64_t t1, t2, tl, th; 1369 al = (uint32_t)(uint16_t)EV_HIHALF(*rA); 1370 ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh); 1371 bl = (uint32_t)(uint16_t)EV_HIHALF(*rB); 1372 bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh); 1373 t1 = ((int64_t)ah * bh) << 1; 1374 t2 = ((int64_t)al * bl) << 1; 1375 th = EV_ACCHIGH - (t1 & 0xffffffff); 1376 tl = EV_ACCLOW - (t2 & 0xffffffff); 1377 EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 1378 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1379 1380 0.4,6.RS,11.RA,16.RB,21.1417:EVX:e500:evmhesmianw %RS,%RA,%RB:Vector Multiply Half Words Even Signed Modulo Integer and Accumulate Negative into Words 1381 int32_t al, ah, bl, bh; 1382 int64_t t1, t2, tl, th; 1383 al = (int32_t)(int16_t)EV_HIHALF(*rA); 1384 ah = (int32_t)(int16_t)EV_HIHALF(*rAh); 1385 bl = (int32_t)(int16_t)EV_HIHALF(*rB); 1386 bh = (int32_t)(int16_t)EV_HIHALF(*rBh); 1387 t1 = ah * bh; 1388 t2 = al * bl; 1389 th = EV_ACCHIGH - t1; 1390 tl = EV_ACCLOW - t2; 1391 EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 1392 //printf("evmhesmianw: al %d ah %d bl %d bh %d t1 %qd t2 %qd tl %qd th %qd\n", al, ah, bl, bh, t1, t2, tl, th); 1393 //printf("evmhesmianw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 1394 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1395 1396 0.4,6.RS,11.RA,16.RB,21.1408:EVX:e500:evmheusianw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Saturate Integer and Accumulate Negative into Words 1397 uint32_t al, ah, bl, bh; 1398 uint64_t t1, t2; 1399 int64_t tl, th; 1400 int ovl, ovh; 1401 al = (uint32_t)(uint16_t)EV_HIHALF(*rA); 1402 ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh); 1403 bl = (uint32_t)(uint16_t)EV_HIHALF(*rB); 1404 bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh); 1405 t1 = ah * bh; 1406 t2 = al * bl; 1407 th = (int64_t)EV_ACCHIGH - (int64_t)t1; 1408 tl = (int64_t)EV_ACCLOW - (int64_t)t2; 1409 ovl = EV_SAT_P_U32(tl); 1410 ovh = EV_SAT_P_U32(th); 1411 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0, 0xffffffff, th), 1412 EV_SATURATE_ACC(ovl, tl, 0, 0xffffffff, tl)); 1413 //printf("evmheusianw: ovh %d ovl %d al %u ah %u bl %u bh %u t1 %qu t2 %qu tl %qd th %qd\n", ovh, ovl, al, ah, bl, bh, t1, t2, tl, th); 1414 //printf("evmheusianw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 1415 EV_SET_SPEFSCR_OV(ovl, ovh); 1416 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1417 1418 0.4,6.RS,11.RA,16.RB,21.1416:EVX:e500:evmheumianw %RS,%RA,%RB:Vector Multiply Half Words Even Unsigned Modulo Integer and Accumulate Negative into Words 1419 uint32_t al, ah, bl, bh; 1420 uint32_t t1, t2; 1421 uint64_t tl, th; 1422 al = (uint32_t)(uint16_t)EV_HIHALF(*rA); 1423 ah = (uint32_t)(uint16_t)EV_HIHALF(*rAh); 1424 bl = (uint32_t)(uint16_t)EV_HIHALF(*rB); 1425 bh = (uint32_t)(uint16_t)EV_HIHALF(*rBh); 1426 t1 = ah * bh; 1427 t2 = al * bl; 1428 th = EV_ACCHIGH - t1; 1429 tl = EV_ACCLOW - t2; 1430 EV_SET_REG2_ACC(*rSh, *rS, th & 0xffffffff, tl & 0xffffffff); 1431 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1432 1433 0.4,6.RS,11.RA,16.RB,21.1327:EVX:e500:evmhogsmfaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Fractional and Accumulate 1434 int32_t a, b; 1435 int64_t t1, t2; 1436 a = (int32_t)(int16_t)EV_LOHALF(*rA); 1437 b = (int32_t)(int16_t)EV_LOHALF(*rB); 1438 t1 = EV_MUL16_SSF(a, b); 1439 if (t1 & ((uint64_t)1 << 32)) 1440 t1 |= 0xfffffffe00000000; 1441 t2 = ACC + t1; 1442 EV_SET_REG1_ACC(*rSh, *rS, t2); 1443 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1444 1445 0.4,6.RS,11.RA,16.RB,21.1325:EVX:e500:evmhogsmiaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Integer and Accumulate 1446 int32_t a, b; 1447 int64_t t1, t2; 1448 a = (int32_t)(int16_t)EV_LOHALF(*rA); 1449 b = (int32_t)(int16_t)EV_LOHALF(*rB); 1450 t1 = (int64_t)a * (int64_t)b; 1451 t2 = (int64_t)ACC + t1; 1452 EV_SET_REG1_ACC(*rSh, *rS, t2); 1453 //printf("evmhogsmiaa: a %d b %d t1 %qd t2 %qd\n", a, b, t1, t2); 1454 //printf("evmhogsmiaa: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 1455 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1456 1457 0.4,6.RS,11.RA,16.RB,21.1324:EVX:e500:evmhogumiaa %RS,%RA,%RB:Multiply Half Words Odd Guarded Unsigned Modulo Integer and Accumulate 1458 uint32_t a, b; 1459 uint64_t t1, t2; 1460 a = (uint32_t)(uint16_t)EV_LOHALF(*rA); 1461 b = (uint32_t)(uint16_t)EV_LOHALF(*rB); 1462 t1 = a * b; 1463 t2 = ACC + t1; 1464 EV_SET_REG1_ACC(*rSh, *rS, t2); 1465 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1466 1467 0.4,6.RS,11.RA,16.RB,21.1323:EVX:e500:evmhegsmfaa %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Fractional and Accumulate 1468 int32_t a, b; 1469 int64_t t1, t2; 1470 a = (int32_t)(int16_t)EV_HIHALF(*rA); 1471 b = (int32_t)(int16_t)EV_HIHALF(*rB); 1472 t1 = EV_MUL16_SSF(a, b); 1473 if (t1 & ((uint64_t)1 << 32)) 1474 t1 |= 0xfffffffe00000000; 1475 t2 = ACC + t1; 1476 EV_SET_REG1_ACC(*rSh, *rS, t2); 1477 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1478 1479 0.4,6.RS,11.RA,16.RB,21.1321:EVX:e500:evmhegsmiaa %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Integer and Accumulate 1480 int32_t a, b; 1481 int64_t t1, t2; 1482 a = (int32_t)(int16_t)EV_HIHALF(*rA); 1483 b = (int32_t)(int16_t)EV_HIHALF(*rB); 1484 t1 = (int64_t)(a * b); 1485 t2 = ACC + t1; 1486 EV_SET_REG1_ACC(*rSh, *rS, t2); 1487 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1488 1489 0.4,6.RS,11.RA,16.RB,21.1320:EVX:e500:evmhegumiaa %RS,%RA,%RB:Multiply Half Words Even Guarded Unsigned Modulo Integer and Accumulate 1490 uint32_t a, b; 1491 uint64_t t1, t2; 1492 a = (uint32_t)(uint16_t)EV_HIHALF(*rA); 1493 b = (uint32_t)(uint16_t)EV_HIHALF(*rB); 1494 t1 = a * b; 1495 t2 = ACC + t1; 1496 EV_SET_REG1_ACC(*rSh, *rS, t2); 1497 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1498 1499 1500 0.4,6.RS,11.RA,16.RB,21.1455:EVX:e500:evmhogsmfan %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Fractional and Accumulate Negative 1501 int32_t a, b; 1502 int64_t t1, t2; 1503 a = (int32_t)(int16_t)EV_LOHALF(*rA); 1504 b = (int32_t)(int16_t)EV_LOHALF(*rB); 1505 t1 = EV_MUL16_SSF(a, b); 1506 if (t1 & ((uint64_t)1 << 32)) 1507 t1 |= 0xfffffffe00000000; 1508 t2 = ACC - t1; 1509 EV_SET_REG1_ACC(*rSh, *rS, t2); 1510 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1511 1512 0.4,6.RS,11.RA,16.RB,21.1453:EVX:e500:evmhogsmian %RS,%RA,%RB:Multiply Half Words Odd Guarded Signed Modulo Integer and Accumulate Negative 1513 int32_t a, b; 1514 int64_t t1, t2; 1515 a = (int32_t)(int16_t)EV_LOHALF(*rA); 1516 b = (int32_t)(int16_t)EV_LOHALF(*rB); 1517 t1 = (int64_t)a * (int64_t)b; 1518 t2 = ACC - t1; 1519 EV_SET_REG1_ACC(*rSh, *rS, t2); 1520 //printf("evmhogsmian: a %d b %d t1 %qd t2 %qd\n", a, b, t1, t2); 1521 //printf("evmhogsmian: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 1522 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1523 1524 0.4,6.RS,11.RA,16.RB,21.1452:EVX:e500:evmhogumian %RS,%RA,%RB:Multiply Half Words Odd Guarded Unsigned Modulo Integer and Accumulate Negative 1525 uint32_t a, b; 1526 uint64_t t1, t2; 1527 a = (uint32_t)(uint16_t)EV_LOHALF(*rA); 1528 b = (uint32_t)(uint16_t)EV_LOHALF(*rB); 1529 t1 = (uint64_t)a * (uint64_t)b; 1530 t2 = ACC - t1; 1531 EV_SET_REG1_ACC(*rSh, *rS, t2); 1532 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1533 1534 0.4,6.RS,11.RA,16.RB,21.1451:EVX:e500:evmhegsmfan %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Fractional and Accumulate Negative 1535 int32_t a, b; 1536 int64_t t1, t2; 1537 a = (int32_t)(int16_t)EV_HIHALF(*rA); 1538 b = (int32_t)(int16_t)EV_HIHALF(*rB); 1539 t1 = EV_MUL16_SSF(a, b); 1540 if (t1 & ((uint64_t)1 << 32)) 1541 t1 |= 0xfffffffe00000000; 1542 t2 = ACC - t1; 1543 EV_SET_REG1_ACC(*rSh, *rS, t2); 1544 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1545 1546 0.4,6.RS,11.RA,16.RB,21.1449:EVX:e500:evmhegsmian %RS,%RA,%RB:Multiply Half Words Even Guarded Signed Modulo Integer and Accumulate Negative 1547 int32_t a, b; 1548 int64_t t1, t2; 1549 a = (int32_t)(int16_t)EV_HIHALF(*rA); 1550 b = (int32_t)(int16_t)EV_HIHALF(*rB); 1551 t1 = (int64_t)a * (int64_t)b; 1552 t2 = ACC - t1; 1553 EV_SET_REG1_ACC(*rSh, *rS, t2); 1554 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1555 1556 0.4,6.RS,11.RA,16.RB,21.1448:EVX:e500:evmhegumian %RS,%RA,%RB:Multiply Half Words Even Guarded Unsigned Modulo Integer and Accumulate Negative 1557 uint32_t a, b; 1558 uint64_t t1, t2; 1559 a = (uint32_t)(uint16_t)EV_HIHALF(*rA); 1560 b = (uint32_t)(uint16_t)EV_HIHALF(*rB); 1561 t1 = (uint64_t)a * (uint64_t)b; 1562 t2 = ACC - t1; 1563 EV_SET_REG1_ACC(*rSh, *rS, t2); 1564 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1565 1566 1567 0.4,6.RS,11.RA,16.RB,21.1095:EVX:e500:evmwhssf %RS,%RA,%RB:Vector Multiply Word High Signed Saturate Fractional 1568 int32_t al, ah, bl, bh; 1569 int64_t t1, t2; 1570 int movl, movh; 1571 al = *rA; 1572 ah = *rAh; 1573 bl = *rB; 1574 bh = *rBh; 1575 t1 = ev_multiply32_ssf(al, bl, &movl); 1576 t2 = ev_multiply32_ssf(ah, bh, &movh); 1577 EV_SET_REG2(*rSh, *rS, EV_SATURATE(movh, 0x7fffffff, t2 >> 32), 1578 EV_SATURATE(movl, 0x7fffffff, t1 >> 32)); 1579 EV_SET_SPEFSCR_OV(movl, movh); 1580 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1581 1582 0.4,6.RS,11.RA,16.RB,21.1127:EVX:e500:evmwhssfa %RS,%RA,%RB:Vector Multiply Word High Signed Saturate Fractional and Accumulate 1583 int32_t al, ah, bl, bh; 1584 int64_t t1, t2; 1585 int movl, movh; 1586 al = *rA; 1587 ah = *rAh; 1588 bl = *rB; 1589 bh = *rBh; 1590 t1 = ev_multiply32_ssf(al, bl, &movl); 1591 t2 = ev_multiply32_ssf(ah, bh, &movh); 1592 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(movh, 0x7fffffff, t2 >> 32), 1593 EV_SATURATE(movl, 0x7fffffff, t1 >> 32)); 1594 EV_SET_SPEFSCR_OV(movl, movh); 1595 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1596 1597 0.4,6.RS,11.RA,16.RB,21.1103:EVX:e500:evmwhsmf %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Fractional 1598 int32_t al, ah, bl, bh; 1599 int64_t t1, t2; 1600 al = *rA; 1601 ah = *rAh; 1602 bl = *rB; 1603 bh = *rBh; 1604 t1 = EV_MUL32_SSF(al, bl); 1605 t2 = EV_MUL32_SSF(ah, bh); 1606 EV_SET_REG2(*rSh, *rS, t2 >> 32, t1 >> 32); 1607 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1608 1609 0.4,6.RS,11.RA,16.RB,21.1135:EVX:e500:evmwhsmfa %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Fractional and Accumulate 1610 int32_t al, ah, bl, bh; 1611 int64_t t1, t2; 1612 al = *rA; 1613 ah = *rAh; 1614 bl = *rB; 1615 bh = *rBh; 1616 t1 = EV_MUL32_SSF(al, bl); 1617 t2 = EV_MUL32_SSF(ah, bh); 1618 EV_SET_REG2_ACC(*rSh, *rS, t2 >> 32, t1 >> 32); 1619 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1620 1621 0.4,6.RS,11.RA,16.RB,21.1101:EVX:e500:evmwhsmi %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Integer 1622 int32_t al, ah, bl, bh; 1623 int64_t t1, t2; 1624 al = *rA; 1625 ah = *rAh; 1626 bl = *rB; 1627 bh = *rBh; 1628 t1 = (int64_t)al * (int64_t)bl; 1629 t2 = (int64_t)ah * (int64_t)bh; 1630 EV_SET_REG2(*rSh, *rS, t2 >> 32, t1 >> 32); 1631 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1632 1633 0.4,6.RS,11.RA,16.RB,21.1133:EVX:e500:evmwhsmia %RS,%RA,%RB:Vector Multiply Word High Signed Modulo Integer and Accumulate 1634 int32_t al, ah, bl, bh; 1635 int64_t t1, t2; 1636 al = *rA; 1637 ah = *rAh; 1638 bl = *rB; 1639 bh = *rBh; 1640 t1 = (int64_t)al * (int64_t)bl; 1641 t2 = (int64_t)ah * (int64_t)bh; 1642 EV_SET_REG2_ACC(*rSh, *rS, t2 >> 32, t1 >> 32); 1643 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1644 1645 0.4,6.RS,11.RA,16.RB,21.1100:EVX:e500:evmwhumi %RS,%RA,%RB:Vector Multiply Word High Unsigned Modulo Integer 1646 uint32_t al, ah, bl, bh; 1647 uint64_t t1, t2; 1648 al = *rA; 1649 ah = *rAh; 1650 bl = *rB; 1651 bh = *rBh; 1652 t1 = (uint64_t)al * (uint64_t)bl; 1653 t2 = (uint64_t)ah * (uint64_t)bh; 1654 EV_SET_REG2(*rSh, *rS, t2 >> 32, t1 >> 32); 1655 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1656 1657 0.4,6.RS,11.RA,16.RB,21.1132:EVX:e500:evmwhumia %RS,%RA,%RB:Vector Multiply Word High Unsigned Modulo Integer and Accumulate 1658 uint32_t al, ah, bl, bh; 1659 uint64_t t1, t2; 1660 al = *rA; 1661 ah = *rAh; 1662 bl = *rB; 1663 bh = *rBh; 1664 t1 = (uint64_t)al * (uint64_t)bl; 1665 t2 = (uint64_t)ah * (uint64_t)bh; 1666 EV_SET_REG2_ACC(*rSh, *rS, t2 >> 32, t1 >> 32); 1667 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1668 1669 1670 0.4,6.RS,11.RA,16.RB,21.1091:EVX:e500:evmwlssf %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional 1671 int32_t al, ah, bl, bh; 1672 int64_t t1, t2; 1673 int movl, movh; 1674 al = *rA; 1675 ah = *rAh; 1676 bl = *rB; 1677 bh = *rBh; 1678 t1 = ev_multiply32_ssf(al, bl, &movl); 1679 t2 = ev_multiply32_ssf(ah, bh, &movh); 1680 EV_SET_REG2(*rSh, *rS, EV_SATURATE(movh, 0xffffffff, t2), 1681 EV_SATURATE(movl, 0xffffffff, t1)); 1682 EV_SET_SPEFSCR_OV(movl, movh); 1683 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1684 1685 0.4,6.RS,11.RA,16.RB,21.1123:EVX:e500:evmwlssfa %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate 1686 int32_t al, ah, bl, bh; 1687 int64_t t1, t2; 1688 int movl, movh; 1689 al = *rA; 1690 ah = *rAh; 1691 bl = *rB; 1692 bh = *rBh; 1693 t1 = ev_multiply32_ssf(al, bl, &movl); 1694 t2 = ev_multiply32_ssf(ah, bh, &movh); 1695 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(movh, 0xffffffff, t2), 1696 EV_SATURATE(movl, 0xffffffff, t1)); 1697 EV_SET_SPEFSCR_OV(movl, movh); 1698 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1699 1700 0.4,6.RS,11.RA,16.RB,21.1099:EVX:e500:evmwlsmf %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional 1701 int32_t al, ah, bl, bh; 1702 int64_t t1, t2; 1703 al = *rA; 1704 ah = *rAh; 1705 bl = *rB; 1706 bh = *rBh; 1707 t1 = EV_MUL32_SSF(al, bl); 1708 t2 = EV_MUL32_SSF(ah, bh); 1709 EV_SET_REG2(*rSh, *rS, t2, t1); 1710 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1711 1712 0.4,6.RS,11.RA,16.RB,21.1131:EVX:e500:evmwlsmfa %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional and Accumulate 1713 int32_t al, ah, bl, bh; 1714 int64_t t1, t2; 1715 al = *rA; 1716 ah = *rAh; 1717 bl = *rB; 1718 bh = *rBh; 1719 t1 = EV_MUL32_SSF(al, bl); 1720 t2 = EV_MUL32_SSF(ah, bh); 1721 EV_SET_REG2_ACC(*rSh, *rS, t2, t1); 1722 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1723 1724 0.4,6.RS,11.RA,16.RB,21.1096:EVX:e500:evmwlumi %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer 1725 uint32_t al, ah, bl, bh; 1726 uint64_t t1, t2; 1727 al = *rA; 1728 ah = *rAh; 1729 bl = *rB; 1730 bh = *rBh; 1731 t1 = (uint64_t)al * (uint64_t)bl; 1732 t2 = (uint64_t)ah * (uint64_t)bh; 1733 EV_SET_REG2(*rSh, *rS, t2, t1); 1734 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1735 1736 0.4,6.RS,11.RA,16.RB,21.1128:EVX:e500:evmwlumia %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer and Accumulate 1737 uint32_t al, ah, bl, bh; 1738 uint64_t t1, t2; 1739 al = *rA; 1740 ah = *rAh; 1741 bl = *rB; 1742 bh = *rBh; 1743 t1 = (uint64_t)al * (uint64_t)bl; 1744 t2 = (uint64_t)ah * (uint64_t)bh; 1745 EV_SET_REG2_ACC(*rSh, *rS, t2, t1); 1746 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1747 1748 1749 0.4,6.RS,11.RA,16.RB,21.1347:EVX:e500:evmwlssfaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate in Words 1750 int32_t al, ah, bl, bh; 1751 int64_t t1, t2, tl, th; 1752 int movl, movh, ovl, ovh; 1753 al = *rA; 1754 ah = *rAh; 1755 bl = *rB; 1756 bh = *rBh; 1757 t1 = ev_multiply32_ssf(ah, bh, &movh); 1758 t2 = ev_multiply32_ssf(al, bl, &movl); 1759 th = EV_ACCHIGH + EV_SATURATE(movh, 0xffffffff, t1); 1760 tl = EV_ACCLOW + EV_SATURATE(movl, 0xffffffff, t2); 1761 ovh = EV_SAT_P_S32(th); 1762 ovl = EV_SAT_P_S32(tl); 1763 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), 1764 EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); 1765 EV_SET_SPEFSCR_OV(movl | ovl, movh | ovh); 1766 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1767 1768 0.4,6.RS,11.RA,16.RB,21.1345:EVX:e500:evmwlssiaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Integer and Accumulate in Words 1769 int32_t al, ah, bl, bh; 1770 int64_t t1, t2, tl, th; 1771 int ovl, ovh; 1772 al = *rA; 1773 ah = *rAh; 1774 bl = *rB; 1775 bh = *rBh; 1776 t1 = (int64_t)ah * (int64_t)bh; 1777 t2 = (int64_t)al * (int64_t)bl; 1778 th = EV_ACCHIGH + (t1 & 0xffffffff); 1779 tl = EV_ACCLOW + (t2 & 0xffffffff); 1780 ovh = EV_SAT_P_S32(th); 1781 ovl = EV_SAT_P_S32(tl); 1782 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), 1783 EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); 1784 EV_SET_SPEFSCR_OV(ovl, ovh); 1785 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1786 1787 0.4,6.RS,11.RA,16.RB,21.1355:EVX:e500:evmwlsmfaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional and Accumulate in Words 1788 int32_t al, ah, bl, bh; 1789 int64_t t1, t2; 1790 int mov; 1791 al = *rA; 1792 ah = *rAh; 1793 bl = *rB; 1794 bh = *rBh; 1795 t1 = ev_multiply32_smf(ah, bh, &mov); 1796 t2 = ev_multiply32_smf(al, bl, &mov); 1797 EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH + (t1 & 0xffffffff), 1798 EV_ACCLOW + (t2 & 0xffffffff)); 1799 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1800 1801 0.4,6.RS,11.RA,16.RB,21.1353:EVX:e500:evmwlsmiaaw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Integer and Accumulate in Words 1802 int32_t al, ah, bl, bh; 1803 int64_t t1, t2; 1804 al = *rA; 1805 ah = *rAh; 1806 bl = *rB; 1807 bh = *rBh; 1808 t1 = (int64_t)ah * (int64_t)bh; 1809 t2 = (int64_t)al * (int64_t)bl; 1810 EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH + (t1 & 0xffffffff), 1811 EV_ACCLOW + (t2 & 0xffffffff)); 1812 //printf("evmwlsmiaaw: al %d ah %d bl %d bh %d t1 %qd t2 %qd\n", al, ah, bl, bh, t1, t2); 1813 //printf("evmwlsmiaaw: *rSh = %08x; *rS = %08x\n", *rSh, *rS); 1814 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1815 1816 0.4,6.RS,11.RA,16.RB,21.1344:EVX:e500:evmwlusiaaw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Saturate Integer and Accumulate in Words 1817 uint32_t al, ah, bl, bh; 1818 uint64_t t1, t2, tl, th; 1819 int ovl, ovh; 1820 al = *rA; 1821 ah = *rAh; 1822 bl = *rB; 1823 bh = *rBh; 1824 t1 = (uint64_t)ah * (uint64_t)bh; 1825 t2 = (uint64_t)al * (uint64_t)bl; 1826 th = EV_ACCHIGH + (t1 & 0xffffffff); 1827 tl = EV_ACCLOW + (t2 & 0xffffffff); 1828 ovh = (th >> 32); 1829 ovl = (tl >> 32); 1830 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(ovh, 0xffffffff, th), 1831 EV_SATURATE(ovl, 0xffffffff, tl)); 1832 EV_SET_SPEFSCR_OV(ovl, ovh); 1833 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1834 1835 0.4,6.RS,11.RA,16.RB,21.1352:EVX:e500:evmwlumiaaw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer and Accumulate in Words 1836 uint32_t al, ah, bl, bh; 1837 uint64_t t1, t2; 1838 al = *rA; 1839 ah = *rAh; 1840 bl = *rB; 1841 bh = *rBh; 1842 t1 = (uint64_t)ah * (uint64_t)bh; 1843 t2 = (uint64_t)al * (uint64_t)bl; 1844 EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH + (t1 & 0xffffffff), 1845 EV_ACCLOW + (t2 & 0xffffffff)); 1846 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1847 1848 1849 0.4,6.RS,11.RA,16.RB,21.1475:EVX:e500:evmwlssfanw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Fractional and Accumulate Negative in Words 1850 int32_t al, ah, bl, bh; 1851 int64_t t1, t2, tl, th; 1852 int movl, movh, ovl, ovh; 1853 al = *rA; 1854 ah = *rAh; 1855 bl = *rB; 1856 bh = *rBh; 1857 t1 = ev_multiply32_ssf(ah, bh, &movh); 1858 t2 = ev_multiply32_ssf(al, bl, &movl); 1859 th = EV_ACCHIGH - EV_SATURATE(movh, 0xffffffff, t1); 1860 tl = EV_ACCLOW - EV_SATURATE(movl, 0xffffffff, t2); 1861 ovh = EV_SAT_P_S32(th); 1862 ovl = EV_SAT_P_S32(tl); 1863 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), 1864 EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); 1865 EV_SET_SPEFSCR_OV(movl | ovl, movh | ovh); 1866 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1867 1868 0.4,6.RS,11.RA,16.RB,21.1473:EVX:e500:evmwlssianw %RS,%RA,%RB:Vector Multiply Word Low Signed Saturate Integer and Accumulate Negative in Words 1869 int32_t al, ah, bl, bh; 1870 int64_t t1, t2, tl, th; 1871 int ovl, ovh; 1872 al = *rA; 1873 ah = *rAh; 1874 bl = *rB; 1875 bh = *rBh; 1876 t1 = (int64_t)ah * (int64_t)bh; 1877 t2 = (int64_t)al * (int64_t)bl; 1878 th = EV_ACCHIGH - (t1 & 0xffffffff); 1879 tl = EV_ACCLOW - (t2 & 0xffffffff); 1880 ovh = EV_SAT_P_S32(th); 1881 ovl = EV_SAT_P_S32(tl); 1882 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, th, 0x80000000, 0x7fffffff, th), 1883 EV_SATURATE_ACC(ovl, tl, 0x80000000, 0x7fffffff, tl)); 1884 EV_SET_SPEFSCR_OV(ovl, ovh); 1885 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1886 1887 0.4,6.RS,11.RA,16.RB,21.1483:EVX:e500:evmwlsmfanw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Fractional and Accumulate Negative in Words 1888 int32_t al, ah, bl, bh; 1889 int64_t t1, t2; 1890 int mov; 1891 al = *rA; 1892 ah = *rAh; 1893 bl = *rB; 1894 bh = *rBh; 1895 t1 = ev_multiply32_smf(ah, bh, &mov); 1896 t2 = ev_multiply32_smf(al, bl, &mov); 1897 EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH - (t1 & 0xffffffff), 1898 EV_ACCLOW - (t2 & 0xffffffff)); 1899 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1900 1901 0.4,6.RS,11.RA,16.RB,21.1481:EVX:e500:evmwlsmianw %RS,%RA,%RB:Vector Multiply Word Low Signed Modulo Integer and Accumulate Negative in Words 1902 int32_t al, ah, bl, bh; 1903 int64_t t1, t2; 1904 al = *rA; 1905 ah = *rAh; 1906 bl = *rB; 1907 bh = *rBh; 1908 t1 = (int64_t)ah * (int64_t)bh; 1909 t2 = (int64_t)al * (int64_t)bl; 1910 EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH - (t1 & 0xffffffff), 1911 EV_ACCLOW - (t2 & 0xffffffff)); 1912 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1913 1914 0.4,6.RS,11.RA,16.RB,21.1472:EVX:e500:evmwlusianw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Saturate Integer and Accumulate Negative in Words 1915 uint32_t al, ah, bl, bh; 1916 uint64_t t1, t2, tl, th; 1917 int ovl, ovh; 1918 al = *rA; 1919 ah = *rAh; 1920 bl = *rB; 1921 bh = *rBh; 1922 t1 = (uint64_t)ah * (uint64_t)bh; 1923 t2 = (uint64_t)al * (uint64_t)bl; 1924 th = EV_ACCHIGH - (t1 & 0xffffffff); 1925 tl = EV_ACCLOW - (t2 & 0xffffffff); 1926 ovh = (th >> 32); 1927 ovl = (tl >> 32); 1928 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(ovh, 0xffffffff, th), 1929 EV_SATURATE(ovl, 0xffffffff, tl)); 1930 //printf("evmwlusianw: ovl %d ovh %d al %d ah %d bl %d bh %d t1 %qd t2 %qd th %qd tl %qd\n", ovl, ovh, al, ah, al, bh, t1, t2, th, tl); 1931 //printf("evmwlusianw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 1932 EV_SET_SPEFSCR_OV(ovl, ovh); 1933 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1934 1935 0.4,6.RS,11.RA,16.RB,21.1480:EVX:e500:evmwlumianw %RS,%RA,%RB:Vector Multiply Word Low Unsigned Modulo Integer and Accumulate Negative in Words 1936 uint32_t al, ah, bl, bh; 1937 uint64_t t1, t2; 1938 al = *rA; 1939 ah = *rAh; 1940 bl = *rB; 1941 bh = *rBh; 1942 t1 = (uint64_t)ah * (uint64_t)bh; 1943 t2 = (uint64_t)al * (uint64_t)bl; 1944 EV_SET_REG2_ACC(*rSh, *rS, EV_ACCHIGH - (t1 & 0xffffffff), 1945 EV_ACCLOW - (t2 & 0xffffffff)); 1946 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1947 1948 1949 0.4,6.RS,11.RA,16.RB,21.1107:EVX:e500:evmwssf %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional 1950 int32_t a, b; 1951 int64_t t; 1952 int movl; 1953 a = *rA; 1954 b = *rB; 1955 t = ev_multiply32_ssf(a, b, &movl); 1956 EV_SET_REG1(*rSh, *rS, EV_SATURATE(movl, 0x7fffffffffffffff, t)); 1957 EV_SET_SPEFSCR_OV(movl, 0); 1958 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1959 1960 0.4,6.RS,11.RA,16.RB,21.1139:EVX:e500:evmwssfa %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional and Accumulate 1961 int32_t a, b; 1962 int64_t t; 1963 int movl; 1964 a = *rA; 1965 b = *rB; 1966 t = ev_multiply32_ssf(a, b, &movl); 1967 EV_SET_REG1_ACC(*rSh, *rS, EV_SATURATE(movl, 0x7fffffffffffffff, t)); 1968 EV_SET_SPEFSCR_OV(movl, 0); 1969 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 1970 1971 0.4,6.RS,11.RA,16.RB,21.1115:EVX:e500:evmwsmf %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional 1972 int32_t a, b; 1973 int64_t t; 1974 int movl; 1975 a = *rA; 1976 b = *rB; 1977 t = ev_multiply32_smf(a, b, &movl); 1978 EV_SET_REG1(*rSh, *rS, t); 1979 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1980 1981 0.4,6.RS,11.RA,16.RB,21.1147:EVX:e500:evmwsmfa %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional and Accumulate 1982 int32_t a, b; 1983 int64_t t; 1984 int movl; 1985 a = *rA; 1986 b = *rB; 1987 t = ev_multiply32_smf(a, b, &movl); 1988 EV_SET_REG1_ACC(*rSh, *rS, t); 1989 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 1990 1991 0.4,6.RS,11.RA,16.RB,21.1113:EVX:e500:evmwsmi %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer 1992 int32_t a, b; 1993 int64_t t; 1994 int movl; 1995 a = *rA; 1996 b = *rB; 1997 t = (int64_t)a * (int64_t)b; 1998 EV_SET_REG1(*rSh, *rS, t); 1999 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 2000 2001 0.4,6.RS,11.RA,16.RB,21.1145:EVX:e500:evmwsmia %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer and Accumulate 2002 int32_t a, b; 2003 int64_t t; 2004 int movl; 2005 a = *rA; 2006 b = *rB; 2007 t = (int64_t)a * (int64_t)b; 2008 EV_SET_REG1_ACC(*rSh, *rS, t); 2009 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 2010 2011 0.4,6.RS,11.RA,16.RB,21.1112:EVX:e500:evmwumi %RS,%RA,%RB:Vector Multiply Word Unigned Modulo Integer 2012 uint32_t a, b; 2013 uint64_t t; 2014 int movl; 2015 a = *rA; 2016 b = *rB; 2017 t = (int64_t)a * (int64_t)b; 2018 EV_SET_REG1(*rSh, *rS, t); 2019 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 2020 2021 0.4,6.RS,11.RA,16.RB,21.1144:EVX:e500:evmwumia %RS,%RA,%RB:Vector Multiply Word Unigned Modulo Integer and Accumulate 2022 uint32_t a, b; 2023 uint64_t t; 2024 int movl; 2025 a = *rA; 2026 b = *rB; 2027 t = (int64_t)a * (int64_t)b; 2028 EV_SET_REG1_ACC(*rSh, *rS, t); 2029 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 2030 2031 2032 0.4,6.RS,11.RA,16.RB,21.1363:EVX:e500:evmwssfaa %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional Add and Accumulate 2033 int64_t t1, t2; 2034 int32_t a, b; 2035 int movl; 2036 a = *rA; 2037 b = *rB; 2038 t1 = ev_multiply32_ssf(a, b, &movl); 2039 t2 = ACC + EV_SATURATE(movl, 0x7fffffffffffffff, t1); 2040 EV_SET_REG1_ACC(*rSh, *rS, t2); 2041 EV_SET_SPEFSCR_OV(movl, 0); 2042 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 2043 2044 0.4,6.RS,11.RA,16.RB,21.1371:EVX:e500:evmwsmfaa %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional Add and Accumulate 2045 int64_t t1, t2; 2046 int32_t a, b; 2047 int movl; 2048 a = *rA; 2049 b = *rB; 2050 t1 = ev_multiply32_smf(a, b, &movl); 2051 t2 = ACC + t1; 2052 EV_SET_REG1_ACC(*rSh, *rS, t2); 2053 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 2054 2055 0.4,6.RS,11.RA,16.RB,21.1369:EVX:e500:evmwsmiaa %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer And and Accumulate 2056 int64_t t1, t2; 2057 int32_t a, b; 2058 a = *rA; 2059 b = *rB; 2060 t1 = (int64_t)a * (int64_t)b; 2061 t2 = ACC + t1; 2062 EV_SET_REG1_ACC(*rSh, *rS, t2); 2063 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 2064 2065 0.4,6.RS,11.RA,16.RB,21.1368:EVX:e500:evmwumiaa %RS,%RA,%RB:Vector Multiply Word Unsigned Modulo Integer Add and Accumulate 2066 uint64_t t1, t2; 2067 uint32_t a, b; 2068 a = *rA; 2069 b = *rB; 2070 t1 = (uint64_t)a * (uint64_t)b; 2071 t2 = ACC + t1; 2072 EV_SET_REG1_ACC(*rSh, *rS, t2); 2073 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 2074 2075 2076 0.4,6.RS,11.RA,16.RB,21.1491:EVX:e500:evmwssfan %RS,%RA,%RB:Vector Multiply Word Signed Saturate Fractional and Accumulate Negative 2077 int64_t t1, t2; 2078 int32_t a, b; 2079 int movl; 2080 a = *rA; 2081 b = *rB; 2082 t1 = ev_multiply32_ssf(a, b, &movl); 2083 t2 = ACC - EV_SATURATE(movl, 0x7fffffffffffffff, t1); 2084 EV_SET_REG1_ACC(*rSh, *rS, t2); 2085 EV_SET_SPEFSCR_OV(movl, 0); 2086 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 2087 2088 0.4,6.RS,11.RA,16.RB,21.1499:EVX:e500:evmwsmfan %RS,%RA,%RB:Vector Multiply Word Signed Modulo Fractional and Accumulate Negative 2089 int64_t t1, t2; 2090 int32_t a, b; 2091 int movl; 2092 a = *rA; 2093 b = *rB; 2094 t1 = ev_multiply32_smf(a, b, &movl); 2095 t2 = ACC - t1; 2096 EV_SET_REG1_ACC(*rSh, *rS, t2); 2097 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 2098 2099 0.4,6.RS,11.RA,16.RB,21.1497:EVX:e500:evmwsmian %RS,%RA,%RB:Vector Multiply Word Signed Modulo Integer and Accumulate Negative 2100 int64_t t1, t2; 2101 int32_t a, b; 2102 a = *rA; 2103 b = *rB; 2104 t1 = (int64_t)a * (int64_t)b; 2105 t2 = ACC - t1; 2106 EV_SET_REG1_ACC(*rSh, *rS, t2); 2107 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 2108 2109 0.4,6.RS,11.RA,16.RB,21.1496:EVX:e500:evmwumian %RS,%RA,%RB:Vector Multiply Word Unsigned Modulo Integer and Accumulate Negative 2110 uint64_t t1, t2; 2111 uint32_t a, b; 2112 a = *rA; 2113 b = *rB; 2114 t1 = (uint64_t)a * (uint64_t)b; 2115 t2 = ACC - t1; 2116 EV_SET_REG1_ACC(*rSh, *rS, t2); 2117 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 2118 2119 2120 0.4,6.RS,11.RA,16.0,21.1217:EVX:e500:evaddssiaaw %RS,%RA:Vector Add Signed Saturate Integer to Accumulator Word 2121 int64_t t1, t2; 2122 int32_t al, ah; 2123 int ovl, ovh; 2124 al = *rA; 2125 ah = *rAh; 2126 t1 = (int64_t)EV_ACCHIGH + (int64_t)ah; 2127 t2 = (int64_t)EV_ACCLOW + (int64_t)al; 2128 ovh = EV_SAT_P_S32(t1); 2129 ovl = EV_SAT_P_S32(t2); 2130 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, t1 & ((uint64_t)1 << 32), 0x80000000, 0x7fffffff, t1), 2131 EV_SATURATE_ACC(ovl, t2 & ((uint64_t)1 << 32), 0x80000000, 0x7fffffff, t2)); 2132 EV_SET_SPEFSCR_OV(ovl, ovh); 2133 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); 2134 2135 0.4,6.RS,11.RA,16.0,21.1225:EVX:e500:evaddsmiaaw %RS,%RA:Vector Add Signed Modulo Integer to Accumulator Word 2136 int64_t t1, t2; 2137 int32_t al, ah; 2138 al = *rA; 2139 ah = *rAh; 2140 t1 = (int64_t)EV_ACCHIGH + (int64_t)ah; 2141 t2 = (int64_t)EV_ACCLOW + (int64_t)al; 2142 EV_SET_REG2_ACC(*rSh, *rS, t1, t2); 2143 //printf("evaddsmiaaw: al %d ah %d t1 %qd t2 %qd\n", al, ah, t1, t2); 2144 //printf("evaddsmiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 2145 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 2146 2147 0.4,6.RS,11.RA,16.0,21.1216:EVX:e500:evaddusiaaw %RS,%RA:Vector Add Unsigned Saturate Integer to Accumulator Word 2148 int64_t t1, t2; 2149 uint32_t al, ah; 2150 int ovl, ovh; 2151 al = *rA; 2152 ah = *rAh; 2153 t1 = (int64_t)EV_ACCHIGH + (int64_t)ah; 2154 t2 = (int64_t)EV_ACCLOW + (int64_t)al; 2155 ovh = EV_SAT_P_U32(t1); 2156 ovl = EV_SAT_P_U32(t2); 2157 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(ovh, 0xffffffff, t1), 2158 EV_SATURATE(ovl, 0xffffffff, t2)); 2159 //printf("evaddusiaaw: ovl %d ovh %d al %d ah %d t1 %qd t2 %qd\n", ovl, ovh, al, ah, t1, t2); 2160 //printf("evaddusiaaw: ACC = %08x.%08x; *rSh = %08x; *rS = %08x\n", (int)(ACC >> 32), (int)ACC, *rSh, *rS); 2161 EV_SET_SPEFSCR_OV(ovl, ovh); 2162 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); 2163 2164 0.4,6.RS,11.RA,16.0,21.1224:EVX:e500:evaddumiaaw %RS,%RA:Vector Add Unsigned Modulo Integer to Accumulator Word 2165 uint64_t t1, t2; 2166 uint32_t al, ah; 2167 al = *rA; 2168 ah = *rAh; 2169 t1 = (uint64_t)EV_ACCHIGH + (uint64_t)ah; 2170 t2 = EV_ACCLOW + al; 2171 EV_SET_REG2_ACC(*rSh, *rS, t1, t2); 2172 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 2173 2174 2175 0.4,6.RS,11.RA,16.0,21.1219:EVX:e500:evsubfssiaaw %RS,%RA:Vector Subtract Signed Saturate Integer to Accumulator Word 2176 int64_t t1, t2; 2177 int32_t al, ah; 2178 int ovl, ovh; 2179 al = *rA; 2180 ah = *rAh; 2181 t1 = (int64_t)EV_ACCHIGH - (int64_t)ah; 2182 t2 = (int64_t)EV_ACCLOW - (int64_t)al; 2183 ovh = EV_SAT_P_S32(t1); 2184 ovl = EV_SAT_P_S32(t2); 2185 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE_ACC(ovh, t1, 0x80000000, 0x7fffffff, t1), 2186 EV_SATURATE_ACC(ovl, t2, 0x80000000, 0x7fffffff, t2)); 2187 EV_SET_SPEFSCR_OV(ovl, ovh); 2188 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); 2189 2190 0.4,6.RS,11.RA,16.0,21.1227:EVX:e500:evsubfsmiaaw %RS,%RA:Vector Subtract Signed Modulo Integer to Accumulator Word 2191 int64_t t1, t2; 2192 int32_t al, ah; 2193 al = *rA; 2194 ah = *rAh; 2195 t1 = (int64_t)EV_ACCHIGH - (int64_t)ah; 2196 t2 = (int64_t)EV_ACCLOW - (int64_t)al; 2197 EV_SET_REG2_ACC(*rSh, *rS, t1, t2); 2198 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 2199 2200 0.4,6.RS,11.RA,16.0,21.1218:EVX:e500:evsubfusiaaw %RS,%RA:Vector Subtract Unsigned Saturate Integer to Accumulator Word 2201 int64_t t1, t2; 2202 uint32_t al, ah; 2203 int ovl, ovh; 2204 2205 al = *rA; 2206 ah = *rAh; 2207 t1 = (int64_t)EV_ACCHIGH - (int64_t)ah; 2208 t2 = (int64_t)EV_ACCLOW - (int64_t)al; 2209 ovh = EV_SAT_P_U32(t1); 2210 ovl = EV_SAT_P_U32(t2); 2211 EV_SET_REG2_ACC(*rSh, *rS, EV_SATURATE(ovh, 0, t1), 2212 EV_SATURATE(ovl, 0, t2)); 2213 EV_SET_SPEFSCR_OV(ovl, ovh); 2214 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); 2215 2216 0.4,6.RS,11.RA,16.0,21.1226:EVX:e500:evsubfumiaaw %RS,%RA:Vector Subtract Unsigned Modulo Integer to Accumulator Word 2217 uint64_t t1, t2; 2218 uint32_t al, ah; 2219 al = *rA; 2220 ah = *rAh; 2221 t1 = (uint64_t)EV_ACCHIGH - (uint64_t)ah; 2222 t2 = (uint64_t)EV_ACCLOW - (uint64_t)al; 2223 EV_SET_REG2_ACC(*rSh, *rS, t1, t2); 2224 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 2225 2226 2227 0.4,6.RS,11.RA,16.0,21.1220:EVX:e500:evmra %RS,%RA:Initialize Accumulator 2228 EV_SET_REG2_ACC(*rSh, *rS, *rAh, *rA); 2229 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 2230 2231 0.4,6.RS,11.RA,16.RB,21.1222:EVX:e500:evdivws %RS,%RA,%RB:Vector Divide Word Signed 2232 int32_t dividendh, dividendl, divisorh, divisorl; 2233 int32_t w1, w2; 2234 int ovh, ovl; 2235 dividendh = *rAh; 2236 dividendl = *rA; 2237 divisorh = *rBh; 2238 divisorl = *rB; 2239 if (dividendh < 0 && divisorh == 0) { 2240 w1 = 0x80000000; 2241 ovh = 1; 2242 } else if (dividendh > 0 && divisorh == 0) { 2243 w1 = 0x7fffffff; 2244 ovh = 1; 2245 } else if (dividendh == 0x80000000 && divisorh == -1) { 2246 w1 = 0x7fffffff; 2247 ovh = 1; 2248 } else { 2249 w1 = dividendh / divisorh; 2250 ovh = 0; 2251 } 2252 if (dividendl < 0 && divisorl == 0) { 2253 w2 = 0x80000000; 2254 ovl = 1; 2255 } else if (dividendl > 0 && divisorl == 0) { 2256 w2 = 0x7fffffff; 2257 ovl = 1; 2258 } else if (dividendl == 0x80000000 && divisorl == -1) { 2259 w2 = 0x7fffffff; 2260 ovl = 1; 2261 } else { 2262 w2 = dividendl / divisorl; 2263 ovl = 0; 2264 } 2265 EV_SET_REG2(*rSh, *rS, w1, w2); 2266 EV_SET_SPEFSCR_OV(ovl, ovh); 2267 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); 2268 2269 2270 0.4,6.RS,11.RA,16.RB,21.1223:EVX:e500:evdivwu %RS,%RA,%RB:Vector Divide Word Unsigned 2271 uint32_t dividendh, dividendl, divisorh, divisorl; 2272 uint32_t w1, w2; 2273 int ovh, ovl; 2274 dividendh = *rAh; 2275 dividendl = *rA; 2276 divisorh = *rBh; 2277 divisorl = *rB; 2278 if (divisorh == 0) { 2279 w1 = 0xffffffff; 2280 ovh = 1; 2281 } else { 2282 w1 = dividendh / divisorh; 2283 ovh = 0; 2284 } 2285 if (divisorl == 0) { 2286 w2 = 0xffffffff; 2287 ovl = 1; 2288 } else { 2289 w2 = dividendl / divisorl; 2290 ovl = 0; 2291 } 2292 EV_SET_REG2(*rSh, *rS, w1, w2); 2293 EV_SET_SPEFSCR_OV(ovl, ovh); 2294 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK, spr_spefscr); 2295 2296 2297 # 2298 # A.2.9 Floating Point SPE Instructions 2299 # 2300 2301 0.4,6.RS,11.RA,16.0,21.644:EVX:e500:evfsabs %RS,%RA:Vector Floating-Point Absolute Value 2302 uint32_t w1, w2; 2303 w1 = *rAh & 0x7fffffff; 2304 w2 = *rA & 0x7fffffff; 2305 EV_SET_REG2(*rSh, *rS, w1, w2); 2306 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 2307 2308 0.4,6.RS,11.RA,16.0,21.645:EVX:e500:evfsnabs %RS,%RA:Vector Floating-Point Negative Absolute Value 2309 uint32_t w1, w2; 2310 w1 = *rAh | 0x80000000; 2311 w2 = *rA | 0x80000000; 2312 EV_SET_REG2(*rSh, *rS, w1, w2); 2313 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 2314 2315 0.4,6.RS,11.RA,16.0,21.646:EVX:e500:evfsneg %RS,%RA:Vector Floating-Point Negate 2316 uint32_t w1, w2; 2317 w1 = *rAh; 2318 w2 = *rA; 2319 w1 = (w1 & 0x7fffffff) | ((~w1) & 0x80000000); 2320 w2 = (w2 & 0x7fffffff) | ((~w2) & 0x80000000); 2321 EV_SET_REG2(*rSh, *rS, w1, w2); 2322 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 2323 2324 0.4,6.RS,11.RA,16.RB,21.640:EVX:e500:evfsadd %RS,%RA,%RB:Vector Floating-Point Add 2325 uint32_t w1, w2; 2326 w1 = ev_fs_add (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fgh, spefscr_fxh, processor); 2327 w2 = ev_fs_add (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); 2328 EV_SET_REG2(*rSh, *rS, w1, w2); 2329 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 2330 2331 0.4,6.RS,11.RA,16.RB,21.641:EVX:e500:evfssub %RS,%RA,%RB:Vector Floating-Point Subtract 2332 uint32_t w1, w2; 2333 w1 = ev_fs_sub (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fgh, spefscr_fxh, processor); 2334 w2 = ev_fs_sub (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); 2335 EV_SET_REG2(*rSh, *rS, w1, w2); 2336 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 2337 2338 0.4,6.RS,11.RA,16.RB,21.648:EVX:e500:evfsmul %RS,%RA,%RB:Vector Floating-Point Multiply 2339 uint32_t w1, w2; 2340 w1 = ev_fs_mul (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fgh, spefscr_fxh, processor); 2341 w2 = ev_fs_mul (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); 2342 EV_SET_REG2(*rSh, *rS, w1, w2); 2343 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 2344 2345 0.4,6.RS,11.RA,16.RB,21.649:EVX:e500:evfsdiv %RS,%RA,%RB:Vector Floating-Point Divide 2346 int32_t w1, w2; 2347 w1 = ev_fs_div (*rAh, *rBh, spefscr_finvh, spefscr_fovfh, spefscr_funfh, spefscr_fdbzh, spefscr_fgh, spefscr_fxh, processor); 2348 w2 = ev_fs_div (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fdbz, spefscr_fg, spefscr_fx, processor); 2349 EV_SET_REG2(*rSh, *rS, w1, w2); 2350 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 2351 2352 0.4,6.BF,9./,11.RA,16.RB,21.652:EVX:e500:evfscmpgt %BF,%RA,%RB:Vector Floating-Point Compare Greater Than 2353 sim_fpu al, ah, bl, bh; 2354 int w, ch, cl; 2355 sim_fpu_32to (&al, *rA); 2356 sim_fpu_32to (&ah, *rAh); 2357 sim_fpu_32to (&bl, *rB); 2358 sim_fpu_32to (&bh, *rBh); 2359 if (EV_IS_INFDENORMNAN(&al) || EV_IS_INFDENORMNAN(&bl)) 2360 EV_SET_SPEFSCR_BITS(spefscr_finv); 2361 if (EV_IS_INFDENORMNAN(&ah) || EV_IS_INFDENORMNAN(&bh)) 2362 EV_SET_SPEFSCR_BITS(spefscr_finvh); 2363 if (sim_fpu_is_gt(&ah, &bh)) 2364 ch = 1; 2365 else 2366 ch = 0; 2367 if (sim_fpu_is_gt(&al, &bl)) 2368 cl = 1; 2369 else 2370 cl = 0; 2371 w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 2372 CR_SET(BF, w); 2373 PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); 2374 2375 0.4,6.BF,9./,11.RA,16.RB,21.653:EVX:e500:evfscmplt %BF,%RA,%RB:Vector Floating-Point Compare Less Than 2376 sim_fpu al, ah, bl, bh; 2377 int w, ch, cl; 2378 sim_fpu_32to (&al, *rA); 2379 sim_fpu_32to (&ah, *rAh); 2380 sim_fpu_32to (&bl, *rB); 2381 sim_fpu_32to (&bh, *rBh); 2382 if (EV_IS_INFDENORMNAN(&al) || EV_IS_INFDENORMNAN(&bl)) 2383 EV_SET_SPEFSCR_BITS(spefscr_finv); 2384 if (EV_IS_INFDENORMNAN(&ah) || EV_IS_INFDENORMNAN(&bh)) 2385 EV_SET_SPEFSCR_BITS(spefscr_finvh); 2386 if (sim_fpu_is_lt(&ah, &bh)) 2387 ch = 1; 2388 else 2389 ch = 0; 2390 if (sim_fpu_is_lt(&al, &bl)) 2391 cl = 1; 2392 else 2393 cl = 0; 2394 w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 2395 CR_SET(BF, w); 2396 PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); 2397 2398 0.4,6.BF,9./,11.RA,16.RB,21.654:EVX:e500:evfscmpeq %BF,%RA,%RB:Vector Floating-Point Compare Equal 2399 sim_fpu al, ah, bl, bh; 2400 int w, ch, cl; 2401 sim_fpu_32to (&al, *rA); 2402 sim_fpu_32to (&ah, *rAh); 2403 sim_fpu_32to (&bl, *rB); 2404 sim_fpu_32to (&bh, *rBh); 2405 if (EV_IS_INFDENORMNAN(&al) || EV_IS_INFDENORMNAN(&bl)) 2406 EV_SET_SPEFSCR_BITS(spefscr_finv); 2407 if (EV_IS_INFDENORMNAN(&ah) || EV_IS_INFDENORMNAN(&bh)) 2408 EV_SET_SPEFSCR_BITS(spefscr_finvh); 2409 if (sim_fpu_is_eq(&ah, &bh)) 2410 ch = 1; 2411 else 2412 ch = 0; 2413 if (sim_fpu_is_eq(&al, &bl)) 2414 cl = 1; 2415 else 2416 cl = 0; 2417 w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 2418 CR_SET(BF, w); 2419 PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); 2420 2421 0.4,6.BF,9./,11.RA,16.RB,21.668:EVX:e500:evfststgt %BF,%RA,%RB:Vector Floating-Point Test Greater Than 2422 sim_fpu al, ah, bl, bh; 2423 int w, ch, cl; 2424 sim_fpu_32to (&al, *rA); 2425 sim_fpu_32to (&ah, *rAh); 2426 sim_fpu_32to (&bl, *rB); 2427 sim_fpu_32to (&bh, *rBh); 2428 if (sim_fpu_is_gt(&ah, &bh)) 2429 ch = 1; 2430 else 2431 ch = 0; 2432 if (sim_fpu_is_gt(&al, &bl)) 2433 cl = 1; 2434 else 2435 cl = 0; 2436 w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 2437 CR_SET(BF, w); 2438 PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 2439 2440 0.4,6.BF,9./,11.RA,16.RB,21.669:EVX:e500:evfststlt %BF,%RA,%RB:Vector Floating-Point Test Less Than 2441 sim_fpu al, ah, bl, bh; 2442 int w, ch, cl; 2443 sim_fpu_32to (&al, *rA); 2444 sim_fpu_32to (&ah, *rAh); 2445 sim_fpu_32to (&bl, *rB); 2446 sim_fpu_32to (&bh, *rBh); 2447 if (sim_fpu_is_lt(&ah, &bh)) 2448 ch = 1; 2449 else 2450 ch = 0; 2451 if (sim_fpu_is_lt(&al, &bl)) 2452 cl = 1; 2453 else 2454 cl = 0; 2455 w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 2456 CR_SET(BF, w); 2457 PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 2458 2459 0.4,6.BF,9./,11.RA,16.RB,21.670:EVX:e500:evfststeq %BF,%RA,%RB:Vector Floating-Point Test Equal 2460 sim_fpu al, ah, bl, bh; 2461 int w, ch, cl; 2462 sim_fpu_32to (&al, *rA); 2463 sim_fpu_32to (&ah, *rAh); 2464 sim_fpu_32to (&bl, *rB); 2465 sim_fpu_32to (&bh, *rBh); 2466 if (sim_fpu_is_eq(&ah, &bh)) 2467 ch = 1; 2468 else 2469 ch = 0; 2470 if (sim_fpu_is_eq(&al, &bl)) 2471 cl = 1; 2472 else 2473 cl = 0; 2474 w = ch << 3 | cl << 2 | (ch | cl) << 1 | (ch & cl); 2475 CR_SET(BF, w); 2476 PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 2477 2478 0.4,6.RS,11.0,16.RB,21.656:EVX:e500:evfscfui %RS,%RB:Vector Convert Floating-Point from Unsigned Integer 2479 uint32_t f, w1, w2; 2480 sim_fpu b; 2481 2482 sim_fpu_u32to (&b, *rBh, sim_fpu_round_default); 2483 sim_fpu_to32 (&w1, &b); 2484 sim_fpu_u32to (&b, *rB, sim_fpu_round_default); 2485 sim_fpu_to32 (&w2, &b); 2486 2487 EV_SET_REG2(*rSh, *rS, w1, w2); 2488 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2489 2490 0.4,6.RS,11.0,16.RB,21.664:EVX:e500:evfsctuiz %RS,%RB:Vector Convert Floating-Point to Unsigned Integer with Round toward Zero 2491 uint32_t w1, w2; 2492 sim_fpu b; 2493 2494 sim_fpu_32to (&b, *rBh); 2495 sim_fpu_to32u (&w1, &b, sim_fpu_round_zero); 2496 sim_fpu_32to (&b, *rB); 2497 sim_fpu_to32u (&w2, &b, sim_fpu_round_zero); 2498 2499 EV_SET_REG2(*rSh, *rS, w1, w2); 2500 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2501 2502 0.4,6.RS,11.0,16.RB,21.657:EVX:e500:evfscfsi %RS,%RB:Vector Convert Floating-Point from Signed Integer 2503 int32_t w1, w2; 2504 sim_fpu b, x, y; 2505 2506 sim_fpu_i32to (&b, *rBh, sim_fpu_round_default); 2507 sim_fpu_to32 (&w1, &b); 2508 sim_fpu_i32to (&b, *rB, sim_fpu_round_default); 2509 sim_fpu_to32 (&w2, &b); 2510 2511 EV_SET_REG2(*rSh, *rS, w1, w2); 2512 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2513 2514 0.4,6.RS,11.0,16.RB,21.658:EVX:e500:evfscfuf %RS,%RB:Vector Convert Floating-Point from Unsigned Fraction 2515 uint32_t w1, w2, bh, bl; 2516 sim_fpu b, x, y; 2517 bh = *rBh; 2518 if (bh == 0xffffffff) 2519 sim_fpu_to32 (&w1, &sim_fpu_one); 2520 else { 2521 sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); 2522 sim_fpu_u32to (&y, bh, sim_fpu_round_default); 2523 sim_fpu_div (&b, &y, &x); 2524 sim_fpu_to32 (&w1, &b); 2525 } 2526 bl = *rB; 2527 if (bl == 0xffffffff) 2528 sim_fpu_to32 (&w2, &sim_fpu_one); 2529 else { 2530 sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); 2531 sim_fpu_u32to (&y, bl, sim_fpu_round_default); 2532 sim_fpu_div (&b, &y, &x); 2533 sim_fpu_to32 (&w2, &b); 2534 } 2535 EV_SET_REG2(*rSh, *rS, w1, w2); 2536 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2537 2538 0.4,6.RS,11.0,16.RB,21.659:EVX:e500:evfscfsf %RS,%RB:Vector Convert Floating-Point from Signed Fraction 2539 uint32_t w1, w2; 2540 sim_fpu b, x, y; 2541 2542 sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); 2543 sim_fpu_i32to (&y, *rBh, sim_fpu_round_default); 2544 sim_fpu_div (&b, &y, &x); 2545 sim_fpu_to32 (&w1, &b); 2546 2547 sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); 2548 sim_fpu_i32to (&y, *rB, sim_fpu_round_default); 2549 sim_fpu_div (&b, &y, &x); 2550 sim_fpu_to32 (&w2, &b); 2551 2552 EV_SET_REG2(*rSh, *rS, w1, w2); 2553 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2554 2555 0.4,6.RS,11.0,16.RB,21.660:EVX:e500:evfsctui %RS,%RB:Vector Convert Floating-Point to Unsigned Integer 2556 uint32_t w1, w2; 2557 sim_fpu b; 2558 2559 sim_fpu_32to (&b, *rBh); 2560 sim_fpu_to32u (&w1, &b, sim_fpu_round_default); 2561 sim_fpu_32to (&b, *rB); 2562 sim_fpu_to32u (&w2, &b, sim_fpu_round_default); 2563 2564 EV_SET_REG2(*rSh, *rS, w1, w2); 2565 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2566 2567 0.4,6.RS,11.0,16.RB,21.661:EVX:e500:evfsctsi %RS,%RB:Vector Convert Floating-Point to Signed Integer 2568 int32_t w1, w2; 2569 sim_fpu b; 2570 2571 sim_fpu_32to (&b, *rBh); 2572 sim_fpu_to32i (&w1, &b, sim_fpu_round_default); 2573 sim_fpu_32to (&b, *rB); 2574 sim_fpu_to32i (&w2, &b, sim_fpu_round_default); 2575 2576 EV_SET_REG2(*rSh, *rS, w1, w2); 2577 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2578 2579 0.4,6.RS,11.0,16.RB,21.666:EVX:e500:evfsctsiz %RS,%RB:Vector Convert Floating-Point to Signed Integer with Round toward Zero 2580 int32_t w1, w2; 2581 sim_fpu b; 2582 2583 sim_fpu_32to (&b, *rBh); 2584 sim_fpu_to32i (&w1, &b, sim_fpu_round_zero); 2585 sim_fpu_32to (&b, *rB); 2586 sim_fpu_to32i (&w2, &b, sim_fpu_round_zero); 2587 2588 EV_SET_REG2(*rSh, *rS, w1, w2); 2589 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2590 2591 0.4,6.RS,11.0,16.RB,21.662:EVX:e500:evfsctuf %RS,%RB:Vector Convert Floating-Point to Unsigned Fraction 2592 uint32_t w1, w2; 2593 sim_fpu b, x, y; 2594 2595 sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); 2596 sim_fpu_32to (&y, *rBh); 2597 sim_fpu_mul (&b, &y, &x); 2598 sim_fpu_to32u (&w1, &b, sim_fpu_round_default); 2599 2600 sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); 2601 sim_fpu_32to (&y, *rB); 2602 sim_fpu_mul (&b, &y, &x); 2603 sim_fpu_to32u (&w2, &b, sim_fpu_round_default); 2604 2605 EV_SET_REG2(*rSh, *rS, w1, w2); 2606 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2607 2608 0.4,6.RS,11.0,16.RB,21.663:EVX:e500:evfsctsf %RS,%RB:Vector Convert Floating-Point to Signed Fraction 2609 int32_t w1, w2; 2610 sim_fpu b, x, y; 2611 2612 sim_fpu_32to (&y, *rBh); 2613 sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); 2614 sim_fpu_mul (&b, &y, &x); 2615 sim_fpu_to32i (&w1, &b, sim_fpu_round_near); 2616 2617 sim_fpu_32to (&y, *rB); 2618 sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); 2619 sim_fpu_mul (&b, &y, &x); 2620 sim_fpu_to32i (&w2, &b, sim_fpu_round_near); 2621 2622 EV_SET_REG2(*rSh, *rS, w1, w2); 2623 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2624 2625 2626 0.4,6.RS,11.RA,16.0,21.708:EVX:e500:efsabs %RS,%RA:Floating-Point Absolute Value 2627 uint32_t w1, w2; 2628 w1 = *rSh; 2629 w2 = *rA & 0x7fffffff; 2630 EV_SET_REG2(*rSh, *rS, w1, w2); 2631 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 2632 2633 0.4,6.RS,11.RA,16.0,21.709:EVX:e500:efsnabs %RS,%RA:Floating-Point Negative Absolute Value 2634 uint32_t w1, w2; 2635 w1 = *rSh; 2636 w2 = *rA | 0x80000000; 2637 EV_SET_REG2(*rSh, *rS, w1, w2); 2638 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 2639 2640 0.4,6.RS,11.RA,16.0,21.710:EVX:e500:efsneg %RS,%RA:Floating-Point Negate 2641 uint32_t w1, w2; 2642 w1 = *rSh; 2643 w2 = (*rA & 0x7fffffff) | ((~*rA) & 0x80000000); 2644 EV_SET_REG2(*rSh, *rS, w1, w2); 2645 PPC_INSN_INT(RS_BITMASK, RA_BITMASK, 0); 2646 2647 0.4,6.RS,11.RA,16.RB,21.704:EVX:e500:efsadd %RS,%RA,%RB:Floating-Point Add 2648 uint32_t w; 2649 w = ev_fs_add (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); 2650 EV_SET_REG(*rS, w); 2651 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 2652 2653 0.4,6.RS,11.RA,16.RB,21.705:EVX:e500:efssub %RS,%RA,%RB:Floating-Point Subtract 2654 uint32_t w; 2655 w = ev_fs_sub (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); 2656 EV_SET_REG(*rS, w); 2657 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 2658 2659 0.4,6.RS,11.RA,16.RB,21.712:EVX:e500:efsmul %RS,%RA,%RB:Floating-Point Multiply 2660 uint32_t w; 2661 w = ev_fs_mul (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fgh, spefscr_fxh, processor); 2662 EV_SET_REG(*rS, w); 2663 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 2664 2665 0.4,6.RS,11.RA,16.RB,21.713:EVX:e500:efsdiv %RS,%RA,%RB:Floating-Point Divide 2666 uint32_t w; 2667 w = ev_fs_div (*rA, *rB, spefscr_finv, spefscr_fovf, spefscr_funf, spefscr_fdbz, spefscr_fg, spefscr_fx, processor); 2668 EV_SET_REG(*rS, w); 2669 PPC_INSN_INT_SPR(RS_BITMASK, RA_BITMASK | RB_BITMASK, spr_spefscr); 2670 2671 0.4,6.BF,9./,11.RA,16.RB,21.716:EVX:e500:efscmpgt %BF,%RA,%RB:Floating-Point Compare Greater Than 2672 sim_fpu a, b; 2673 int w, cl; 2674 sim_fpu_32to (&a, *rA); 2675 sim_fpu_32to (&b, *rB); 2676 if (EV_IS_INFDENORMNAN(&a) || EV_IS_INFDENORMNAN(&b)) 2677 EV_SET_SPEFSCR_BITS(spefscr_finv); 2678 if (sim_fpu_is_gt(&a, &b)) 2679 cl = 1; 2680 else 2681 cl = 0; 2682 w = cl << 2 | cl << 1; 2683 CR_SET(BF, w); 2684 PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); 2685 2686 0.4,6.BF,9./,11.RA,16.RB,21.717:EVX:e500:efscmplt %BF,%RA,%RB:Floating-Point Compare Less Than 2687 sim_fpu al, bl; 2688 int w, cl; 2689 sim_fpu_32to (&al, *rA); 2690 sim_fpu_32to (&bl, *rB); 2691 if (EV_IS_INFDENORMNAN(&al) || EV_IS_INFDENORMNAN(&bl)) 2692 EV_SET_SPEFSCR_BITS(spefscr_finv); 2693 if (sim_fpu_is_lt(&al, &bl)) 2694 cl = 1; 2695 else 2696 cl = 0; 2697 w = cl << 2 | cl << 1; 2698 CR_SET(BF, w); 2699 PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); 2700 2701 0.4,6.BF,9./,11.RA,16.RB,21.718:EVX:e500:efscmpeq %BF,%RA,%RB:Floating-Point Compare Equal 2702 sim_fpu al, bl; 2703 int w, cl; 2704 sim_fpu_32to (&al, *rA); 2705 sim_fpu_32to (&bl, *rB); 2706 if (EV_IS_INFDENORMNAN(&al) || EV_IS_INFDENORMNAN(&bl)) 2707 EV_SET_SPEFSCR_BITS(spefscr_finv); 2708 if (sim_fpu_is_eq(&al, &bl)) 2709 cl = 1; 2710 else 2711 cl = 0; 2712 w = cl << 2 | cl << 1; 2713 CR_SET(BF, w); 2714 PPC_INSN_INT_SPR(0, RA_BITMASK | RB_BITMASK, spr_spefscr); 2715 2716 0.4,6.BF,9./,11.RA,16.RB,21.732:EVX:e500:efststgt %BF,%RA,%RB:Floating-Point Test Greater Than 2717 sim_fpu al, bl; 2718 int w, cl; 2719 sim_fpu_32to (&al, *rA); 2720 sim_fpu_32to (&bl, *rB); 2721 if (sim_fpu_is_gt(&al, &bl)) 2722 cl = 1; 2723 else 2724 cl = 0; 2725 w = cl << 2 | cl << 1; 2726 CR_SET(BF, w); 2727 PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 2728 2729 0.4,6.BF,9./,11.RA,16.RB,21.733:EVX:e500:efststlt %BF,%RA,%RB:Floating-Point Test Less Than 2730 sim_fpu al, bl; 2731 int w, cl; 2732 sim_fpu_32to (&al, *rA); 2733 sim_fpu_32to (&bl, *rB); 2734 if (sim_fpu_is_lt(&al, &bl)) 2735 cl = 1; 2736 else 2737 cl = 0; 2738 w = cl << 2 | cl << 1; 2739 CR_SET(BF, w); 2740 PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 2741 2742 0.4,6.BF,9./,11.RA,16.RB,21.734:EVX:e500:efststeq %BF,%RA,%RB:Floating-Point Test Equal 2743 sim_fpu al, bl; 2744 int w, cl; 2745 sim_fpu_32to (&al, *rA); 2746 sim_fpu_32to (&bl, *rB); 2747 if (sim_fpu_is_eq(&al, &bl)) 2748 cl = 1; 2749 else 2750 cl = 0; 2751 w = cl << 2 | cl << 1; 2752 CR_SET(BF, w); 2753 PPC_INSN_INT_CR(0, RA_BITMASK | RB_BITMASK, BF_BITMASK); 2754 2755 0.4,6.RS,11.0,16.RB,21.721:EVX:e500:efscfsi %RS,%RB:Convert Floating-Point from Signed Integer 2756 int32_t f, w1, w2; 2757 sim_fpu b; 2758 w1 = *rSh; 2759 sim_fpu_i32to (&b, *rB, sim_fpu_round_default); 2760 sim_fpu_to32 (&w2, &b); 2761 EV_SET_REG2(*rSh, *rS, w1, w2); 2762 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2763 2764 0.4,6.RS,11.0,16.RB,21.720:EVX:e500:efscfui %RS,%RB:Convert Floating-Point from Unsigned Integer 2765 uint32_t w1, w2; 2766 sim_fpu b; 2767 w1 = *rSh; 2768 sim_fpu_u32to (&b, *rB, sim_fpu_round_default); 2769 sim_fpu_to32 (&w2, &b); 2770 EV_SET_REG2(*rSh, *rS, w1, w2); 2771 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2772 2773 0.4,6.RS,11.0,16.RB,21.723:EVX:e500:efscfsf %RS,%RB:Convert Floating-Point from Signed Fraction 2774 uint32_t w1, w2; 2775 sim_fpu b, x, y; 2776 w1 = *rSh; 2777 sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); 2778 sim_fpu_i32to (&y, *rB, sim_fpu_round_default); 2779 sim_fpu_div (&b, &y, &x); 2780 sim_fpu_to32 (&w2, &b); 2781 EV_SET_REG2(*rSh, *rS, w1, w2); 2782 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2783 2784 0.4,6.RS,11.0,16.RB,21.722:EVX:e500:efscfuf %RS,%RB:Convert Floating-Point from Unsigned Fraction 2785 uint32_t w1, w2, bl; 2786 sim_fpu b, x, y; 2787 w1 = *rSh; 2788 bl = *rB; 2789 if (bl == 0xffffffff) 2790 sim_fpu_to32 (&w2, &sim_fpu_one); 2791 else { 2792 sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); 2793 sim_fpu_u32to (&y, bl, sim_fpu_round_default); 2794 sim_fpu_div (&b, &y, &x); 2795 sim_fpu_to32 (&w2, &b); 2796 } 2797 EV_SET_REG2(*rSh, *rS, w1, w2); 2798 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2799 2800 0.4,6.RS,11.0,16.RB,21.725:EVX:e500:efsctsi %RS,%RB:Convert Floating-Point to Signed Integer 2801 int64_t temp; 2802 int32_t w1, w2; 2803 sim_fpu b; 2804 w1 = *rSh; 2805 sim_fpu_32to (&b, *rB); 2806 sim_fpu_to32i (&w2, &b, sim_fpu_round_default); 2807 EV_SET_REG2(*rSh, *rS, w1, w2); 2808 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2809 2810 0.4,6.RS,11.0,16.RB,21.730:EVX:e500:efsctsiz %RS,%RB:Convert Floating-Point to Signed Integer with Round toward Zero 2811 int64_t temp; 2812 int32_t w1, w2; 2813 sim_fpu b; 2814 w1 = *rSh; 2815 sim_fpu_32to (&b, *rB); 2816 sim_fpu_to32i (&w2, &b, sim_fpu_round_zero); 2817 EV_SET_REG2(*rSh, *rS, w1, w2); 2818 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2819 2820 0.4,6.RS,11.0,16.RB,21.724:EVX:e500:efsctui %RS,%RB:Convert Floating-Point to Unsigned Integer 2821 uint64_t temp; 2822 int32_t w1, w2; 2823 sim_fpu b; 2824 w1 = *rSh; 2825 sim_fpu_32to (&b, *rB); 2826 sim_fpu_to32u (&w2, &b, sim_fpu_round_default); 2827 EV_SET_REG2(*rSh, *rS, w1, w2); 2828 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2829 2830 0.4,6.RS,11.0,16.RB,21.728:EVX:e500:efsctuiz %RS,%RB:Convert Floating-Point to Unsigned Integer with Round toward Zero 2831 uint64_t temp; 2832 int32_t w1, w2; 2833 sim_fpu b; 2834 w1 = *rSh; 2835 sim_fpu_32to (&b, *rB); 2836 sim_fpu_to32u (&w2, &b, sim_fpu_round_zero); 2837 EV_SET_REG2(*rSh, *rS, w1, w2); 2838 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2839 2840 0.4,6.RS,11.0,16.RB,21.727:EVX:e500:efsctsf %RS,%RB:Convert Floating-Point to Signed Fraction 2841 uint32_t w1, w2; 2842 sim_fpu b, x, y; 2843 w1 = *rSh; 2844 sim_fpu_32to (&y, *rB); 2845 sim_fpu_u32to (&x, 0x80000000, sim_fpu_round_default); 2846 sim_fpu_mul (&b, &y, &x); 2847 sim_fpu_to32i (&w2, &b, sim_fpu_round_default); 2848 sim_fpu_to32 (&w2, &b); 2849 EV_SET_REG2(*rSh, *rS, w1, w2); 2850 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2851 2852 0.4,6.RS,11.0,16.RB,21.726:EVX:e500:efsctuf %RS,%RB:Convert Floating-Point to Unsigned Fraction 2853 uint32_t w1, w2; 2854 sim_fpu b, x, y; 2855 w1 = *rSh; 2856 sim_fpu_u64to (&x, 0x100000000, sim_fpu_round_default); 2857 sim_fpu_32to (&y, *rB); 2858 sim_fpu_mul (&b, &y, &x); 2859 sim_fpu_to32u (&w2, &b, sim_fpu_round_default); 2860 EV_SET_REG2(*rSh, *rS, w1, w2); 2861 PPC_INSN_INT(RS_BITMASK, RB_BITMASK, 0); 2862 2863 2864 # 2865 # A.2.10 Vector Load/Store Instructions 2866 # 2867 2868 0.4,6.RS,11.RA,16.UIMM,21.769:EVX:e500:evldd %RS,%RA,%UIMM:Vector Load Double Word into Double Word 2869 uint64_t m; 2870 unsigned_word b; 2871 unsigned_word EA; 2872 if (RA_is_0) b = 0; 2873 else b = *rA; 2874 EA = b + (UIMM << 3); 2875 m = MEM(unsigned, EA, 8); 2876 EV_SET_REG1(*rSh, *rS, m); 2877 //printf("evldd(%d<-%d + %u): m %08x.%08x, *rSh %x *rS %x\n", RS, RA, UIMM, (int)(m >> 32), (int)m, *rSh, *rS); 2878 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 2879 2880 0.4,6.RS,11.RA,16.RB,21.768:EVX:e500:evlddx %RS,%RA,%RB:Vector Load Double Word into Double Word Indexed 2881 uint64_t m; 2882 unsigned_word b; 2883 unsigned_word EA; 2884 if (RA_is_0) b = 0; 2885 else b = *rA; 2886 EA = b + *rB; 2887 m = MEM(unsigned, EA, 8); 2888 EV_SET_REG1(*rSh, *rS, m); 2889 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 2890 2891 0.4,6.RS,11.RA,16.UIMM,21.771:EVX:e500:evldw %RS,%RA,%UIMM:Vector Load Double into Two Words 2892 unsigned_word b; 2893 unsigned_word EA; 2894 uint32_t w1, w2; 2895 if (RA_is_0) b = 0; 2896 else b = *rA; 2897 EA = b + (UIMM << 3); 2898 w1 = MEM(unsigned, EA, 4); 2899 w2 = MEM(unsigned, EA + 4, 4); 2900 EV_SET_REG2(*rSh, *rS, w1, w2); 2901 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 2902 2903 0.4,6.RS,11.RA,16.RB,21.770:EVX:e500:evldwx %RS,%RA,%RB:Vector Load Double into Two Words Indexed 2904 unsigned_word b; 2905 unsigned_word EA; 2906 uint32_t w1, w2; 2907 if (RA_is_0) b = 0; 2908 else b = *rA; 2909 EA = b + *rB; 2910 w1 = MEM(unsigned, EA, 4); 2911 w2 = MEM(unsigned, EA + 4, 4); 2912 EV_SET_REG2(*rSh, *rS, w1, w2); 2913 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 2914 2915 0.4,6.RS,11.RA,16.UIMM,21.773:EVX:e500:evldh %RS,%RA,%UIMM:Vector Load Double into 4 Half Words 2916 unsigned_word b; 2917 unsigned_word EA; 2918 uint16_t h1, h2, h3, h4; 2919 if (RA_is_0) b = 0; 2920 else b = *rA; 2921 EA = b + (UIMM << 3); 2922 h1 = MEM(unsigned, EA, 2); 2923 h2 = MEM(unsigned, EA + 2, 2); 2924 h3 = MEM(unsigned, EA + 4, 2); 2925 h4 = MEM(unsigned, EA + 6, 2); 2926 EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); 2927 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 2928 2929 0.4,6.RS,11.RA,16.RB,21.772:EVX:e500:evldhx %RS,%RA,%RB:Vector Load Double into 4 Half Words Indexed 2930 unsigned_word b; 2931 unsigned_word EA; 2932 uint16_t h1, h2, h3, h4; 2933 if (RA_is_0) b = 0; 2934 else b = *rA; 2935 EA = b + *rB; 2936 h1 = MEM(unsigned, EA, 2); 2937 h2 = MEM(unsigned, EA + 2, 2); 2938 h3 = MEM(unsigned, EA + 4, 2); 2939 h4 = MEM(unsigned, EA + 6, 2); 2940 EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); 2941 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 2942 2943 0.4,6.RS,11.RA,16.UIMM,21.785:EVX:e500:evlwhe %RS,%RA,%UIMM:Vector Load Word into Two Half Words Even 2944 unsigned_word b; 2945 unsigned_word EA; 2946 uint16_t h1, h2, h3, h4; 2947 if (RA_is_0) b = 0; 2948 else b = *rA; 2949 EA = b + (UIMM << 2); 2950 h1 = MEM(unsigned, EA, 2); 2951 h2 = 0; 2952 h3 = MEM(unsigned, EA + 2, 2); 2953 h4 = 0; 2954 EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); 2955 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 2956 2957 0.4,6.RS,11.RA,16.RB,21.784:EVX:e500:evlwhex %RS,%RA,%RB:Vector Load Word into Two Half Words Even Indexed 2958 unsigned_word b; 2959 unsigned_word EA; 2960 uint16_t h1, h2, h3, h4; 2961 if (RA_is_0) b = 0; 2962 else b = *rA; 2963 EA = b + *rB; 2964 h1 = MEM(unsigned, EA, 2); 2965 h2 = 0; 2966 h3 = MEM(unsigned, EA + 2, 2); 2967 h4 = 0; 2968 EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); 2969 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 2970 2971 0.4,6.RS,11.RA,16.UIMM,21.789:EVX:e500:evlwhou %RS,%RA,%UIMM:Vector Load Word into Two Half Words Odd Unsigned zero-extended 2972 unsigned_word b; 2973 unsigned_word EA; 2974 uint16_t h1, h2, h3, h4; 2975 if (RA_is_0) b = 0; 2976 else b = *rA; 2977 EA = b + (UIMM << 2); 2978 h1 = 0; 2979 h2 = MEM(unsigned, EA, 2); 2980 h3 = 0; 2981 h4 = MEM(unsigned, EA + 2, 2); 2982 EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); 2983 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 2984 2985 0.4,6.RS,11.RA,16.RB,21.788:EVX:e500:evlwhoux %RS,%RA,%RB:Vector Load Word into Two Half Words Odd Unsigned Indexed zero-extended 2986 unsigned_word b; 2987 unsigned_word EA; 2988 uint16_t h1, h2, h3, h4; 2989 if (RA_is_0) b = 0; 2990 else b = *rA; 2991 EA = b + *rB; 2992 h1 = 0; 2993 h2 = MEM(unsigned, EA, 2); 2994 h3 = 0; 2995 h4 = MEM(unsigned, EA + 2, 2); 2996 EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); 2997 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 2998 2999 0.4,6.RS,11.RA,16.UIMM,21.791:EVX:e500:evlwhos %RS,%RA,%UIMM:Vector Load Word into Half Words Odd Signed with sign extension 3000 unsigned_word b; 3001 unsigned_word EA; 3002 uint16_t h1, h2, h3, h4; 3003 if (RA_is_0) b = 0; 3004 else b = *rA; 3005 EA = b + (UIMM << 2); 3006 h2 = MEM(unsigned, EA, 2); 3007 if (h2 & 0x8000) 3008 h1 = 0xffff; 3009 else 3010 h1 = 0; 3011 h4 = MEM(unsigned, EA + 2, 2); 3012 if (h4 & 0x8000) 3013 h3 = 0xffff; 3014 else 3015 h3 = 0; 3016 EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); 3017 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 3018 3019 0.4,6.RS,11.RA,16.RB,21.790:EVX:e500:evlwhosx %RS,%RA,%RB:Vector Load Word into Half Words Odd Signed Indexed with sign extension 3020 unsigned_word b; 3021 unsigned_word EA; 3022 uint16_t h1, h2, h3, h4; 3023 if (RA_is_0) b = 0; 3024 else b = *rA; 3025 EA = b + *rB; 3026 h2 = MEM(unsigned, EA, 2); 3027 if (h2 & 0x8000) 3028 h1 = 0xffff; 3029 else 3030 h1 = 0; 3031 h4 = MEM(unsigned, EA + 2, 2); 3032 if (h4 & 0x8000) 3033 h3 = 0xffff; 3034 else 3035 h3 = 0; 3036 EV_SET_REG4(*rSh, *rS, h1, h2, h3, h4); 3037 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 3038 3039 0.4,6.RS,11.RA,16.UIMM,21.793:EVX:e500:evlwwsplat %RS,%RA,%UIMM:Vector Load Word into Word and Splat 3040 unsigned_word b; 3041 unsigned_word EA; 3042 uint32_t w1; 3043 if (RA_is_0) b = 0; 3044 else b = *rA; 3045 EA = b + (UIMM << 2); 3046 w1 = MEM(unsigned, EA, 4); 3047 EV_SET_REG2(*rSh, *rS, w1, w1); 3048 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 3049 3050 0.4,6.RS,11.RA,16.RB,21.792:EVX:e500:evlwwsplatx %RS,%RA,%RB:Vector Load Word into Word and Splat Indexed 3051 unsigned_word b; 3052 unsigned_word EA; 3053 uint32_t w1; 3054 if (RA_is_0) b = 0; 3055 else b = *rA; 3056 EA = b + *rB; 3057 w1 = MEM(unsigned, EA, 4); 3058 EV_SET_REG2(*rSh, *rS, w1, w1); 3059 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 3060 3061 0.4,6.RS,11.RA,16.UIMM,21.797:EVX:e500:evlwhsplat %RS,%RA,%UIMM:Vector Load Word into 2 Half Words and Splat 3062 unsigned_word b; 3063 unsigned_word EA; 3064 uint16_t h1, h2; 3065 if (RA_is_0) b = 0; 3066 else b = *rA; 3067 EA = b + (UIMM << 2); 3068 h1 = MEM(unsigned, EA, 2); 3069 h2 = MEM(unsigned, EA + 2, 2); 3070 EV_SET_REG4(*rSh, *rS, h1, h1, h2, h2); 3071 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 3072 3073 0.4,6.RS,11.RA,16.RB,21.796:EVX:e500:evlwhsplatx %RS,%RA,%RB:Vector Load Word into 2 Half Words and Splat Indexed 3074 unsigned_word b; 3075 unsigned_word EA; 3076 uint16_t h1, h2; 3077 if (RA_is_0) b = 0; 3078 else b = *rA; 3079 EA = b + *rB; 3080 h1 = MEM(unsigned, EA, 2); 3081 h2 = MEM(unsigned, EA + 2, 2); 3082 EV_SET_REG4(*rSh, *rS, h1, h1, h2, h2); 3083 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 3084 3085 0.4,6.RS,11.RA,16.UIMM,21.777:EVX:e500:evlhhesplat %RS,%RA,%UIMM:Vector Load Half Word into Half Words Even and Splat 3086 unsigned_word b; 3087 unsigned_word EA; 3088 uint16_t h; 3089 if (RA_is_0) b = 0; 3090 else b = *rA; 3091 EA = b + (UIMM << 1); 3092 h = MEM(unsigned, EA, 2); 3093 EV_SET_REG4(*rSh, *rS, h, 0, h, 0); 3094 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 3095 3096 0.4,6.RS,11.RA,16.RB,21.776:EVX:e500:evlhhesplatx %RS,%RA,%RB:Vector Load Half Word into Half Words Even and Splat Indexed 3097 unsigned_word b; 3098 unsigned_word EA; 3099 uint16_t h; 3100 if (RA_is_0) b = 0; 3101 else b = *rA; 3102 EA = b + *rB; 3103 h = MEM(unsigned, EA, 2); 3104 EV_SET_REG4(*rSh, *rS, h, 0, h, 0); 3105 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 3106 3107 0.4,6.RS,11.RA,16.UIMM,21.781:EVX:e500:evlhhousplat %RS,%RA,%UIMM:Vector Load Half Word into Half Word Odd Unsigned and Splat 3108 unsigned_word b; 3109 unsigned_word EA; 3110 uint16_t h; 3111 if (RA_is_0) b = 0; 3112 else b = *rA; 3113 EA = b + (UIMM << 1); 3114 h = MEM(unsigned, EA, 2); 3115 EV_SET_REG4(*rSh, *rS, 0, h, 0, h); 3116 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 3117 3118 0.4,6.RS,11.RA,16.RB,21.780:EVX:e500:evlhhousplatx %RS,%RA,%RB:Vector Load Half Word into Half Word Odd Unsigned and Splat Indexed 3119 unsigned_word b; 3120 unsigned_word EA; 3121 uint16_t h; 3122 if (RA_is_0) b = 0; 3123 else b = *rA; 3124 EA = b + *rB; 3125 h = MEM(unsigned, EA, 2); 3126 EV_SET_REG4(*rSh, *rS, 0, h, 0, h); 3127 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 3128 3129 0.4,6.RS,11.RA,16.UIMM,21.783:EVX:e500:evlhhossplat %RS,%RA,%UIMM:Vector Load Half Word into Half Word Odd Signed and Splat 3130 unsigned_word b; 3131 unsigned_word EA; 3132 uint16_t h1, h2; 3133 if (RA_is_0) b = 0; 3134 else b = *rA; 3135 EA = b + (UIMM << 1); 3136 h2 = MEM(unsigned, EA, 2); 3137 if (h2 & 0x8000) 3138 h1 = 0xffff; 3139 else 3140 h1 = 0; 3141 EV_SET_REG4(*rSh, *rS, h1, h2, h1, h2); 3142 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 3143 3144 0.4,6.RS,11.RA,16.RB,21.782:EVX:e500:evlhhossplatx %RS,%RA,%RB:Vector Load Half Word into Half Word Odd Signed and Splat Indexed 3145 unsigned_word b; 3146 unsigned_word EA; 3147 uint16_t h1, h2; 3148 if (RA_is_0) b = 0; 3149 else b = *rA; 3150 EA = b + *rB; 3151 h2 = MEM(unsigned, EA, 2); 3152 if (h2 & 0x8000) 3153 h1 = 0xffff; 3154 else 3155 h1 = 0; 3156 EV_SET_REG4(*rSh, *rS, h1, h2, h1, h2); 3157 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 3158 3159 3160 0.4,6.RS,11.RA,16.UIMM,21.801:EVX:e500:evstdd %RS,%RA,%UIMM:Vector Store Double of Double 3161 unsigned_word b; 3162 unsigned_word EA; 3163 if (RA_is_0) b = 0; 3164 else b = *rA; 3165 EA = b + (UIMM << 3); 3166 STORE(EA, 4, (*rSh)); 3167 STORE(EA + 4, 4, (*rS)); 3168 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 3169 3170 0.4,6.RS,11.RA,16.RB,21.800:EVX:e500:evstddx %RS,%RA,%RB:Vector Store Double of Double Indexed 3171 unsigned_word b; 3172 unsigned_word EA; 3173 if (RA_is_0) b = 0; 3174 else b = *rA; 3175 EA = b + *rB; 3176 STORE(EA, 4, (*rSh)); 3177 STORE(EA + 4, 4, (*rS)); 3178 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 3179 3180 0.4,6.RS,11.RA,16.UIMM,21.803:EVX:e500:evstdw %RS,%RA,%UIMM:Vector Store Double of Two Words 3181 unsigned_word b; 3182 unsigned_word EA; 3183 uint32_t w1, w2; 3184 if (RA_is_0) b = 0; 3185 else b = *rA; 3186 EA = b + (UIMM << 3); 3187 w1 = *rSh; 3188 w2 = *rS; 3189 STORE(EA + 0, 4, w1); 3190 STORE(EA + 4, 4, w2); 3191 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 3192 3193 0.4,6.RS,11.RA,16.RB,21.802:EVX:e500:evstdwx %RS,%RA,%RB:Vector Store Double of Two Words Indexed 3194 unsigned_word b; 3195 unsigned_word EA; 3196 uint32_t w1, w2; 3197 if (RA_is_0) b = 0; 3198 else b = *rA; 3199 EA = b + *rB; 3200 w1 = *rSh; 3201 w2 = *rS; 3202 STORE(EA + 0, 4, w1); 3203 STORE(EA + 4, 4, w2); 3204 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 3205 3206 0.4,6.RS,11.RA,16.UIMM,21.805:EVX:e500:evstdh %RS,%RA,%UIMM:Vector Store Double of Four Half Words 3207 unsigned_word b; 3208 unsigned_word EA; 3209 uint16_t h1, h2, h3, h4; 3210 if (RA_is_0) b = 0; 3211 else b = *rA; 3212 EA = b + (UIMM << 3); 3213 h1 = EV_HIHALF(*rSh); 3214 h2 = EV_LOHALF(*rSh); 3215 h3 = EV_HIHALF(*rS); 3216 h4 = EV_LOHALF(*rS); 3217 STORE(EA + 0, 2, h1); 3218 STORE(EA + 2, 2, h2); 3219 STORE(EA + 4, 2, h3); 3220 STORE(EA + 6, 2, h4); 3221 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 3222 3223 0.4,6.RS,11.RA,16.RB,21.804:EVX:e500:evstdhx %RS,%RA,%RB:Vector Store Double of Four Half Words Indexed 3224 unsigned_word b; 3225 unsigned_word EA; 3226 uint16_t h1, h2, h3, h4; 3227 if (RA_is_0) b = 0; 3228 else b = *rA; 3229 EA = b + *rB; 3230 h1 = EV_HIHALF(*rSh); 3231 h2 = EV_LOHALF(*rSh); 3232 h3 = EV_HIHALF(*rS); 3233 h4 = EV_LOHALF(*rS); 3234 STORE(EA + 0, 2, h1); 3235 STORE(EA + 2, 2, h2); 3236 STORE(EA + 4, 2, h3); 3237 STORE(EA + 6, 2, h4); 3238 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 3239 3240 0.4,6.RS,11.RA,16.UIMM,21.825:EVX:e500:evstwwe %RS,%RA,%UIMM:Vector Store Word of Word from Even 3241 unsigned_word b; 3242 unsigned_word EA; 3243 uint32_t w; 3244 if (RA_is_0) b = 0; 3245 else b = *rA; 3246 EA = b + (UIMM << 3); 3247 w = *rSh; 3248 STORE(EA, 4, w); 3249 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 3250 3251 0.4,6.RS,11.RA,16.RB,21.824:EVX:e500:evstwwex %RS,%RA,%RB:Vector Store Word of Word from Even Indexed 3252 unsigned_word b; 3253 unsigned_word EA; 3254 uint32_t w; 3255 if (RA_is_0) b = 0; 3256 else b = *rA; 3257 EA = b + *rB; 3258 w = *rSh; 3259 STORE(EA, 4, w); 3260 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 3261 3262 0.4,6.RS,11.RA,16.UIMM,21.829:EVX:e500:evstwwo %RS,%RA,%UIMM:Vector Store Word of Word from Odd 3263 unsigned_word b; 3264 unsigned_word EA; 3265 uint32_t w; 3266 if (RA_is_0) b = 0; 3267 else b = *rA; 3268 EA = b + (UIMM << 3); 3269 w = *rS; 3270 STORE(EA, 4, w); 3271 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 3272 3273 0.4,6.RS,11.RA,16.RB,21.828:EVX:e500:evstwwox %RS,%RA,%RB:Vector Store Word of Word from Odd Indexed 3274 unsigned_word b; 3275 unsigned_word EA; 3276 uint32_t w; 3277 if (RA_is_0) b = 0; 3278 else b = *rA; 3279 EA = b + *rB; 3280 w = *rS; 3281 STORE(EA, 4, w); 3282 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 3283 3284 0.4,6.RS,11.RA,16.UIMM,21.817:EVX:e500:evstwhe %RS,%RA,%UIMM:Vector Store Word of Two Half Words from Even 3285 unsigned_word b; 3286 unsigned_word EA; 3287 uint16_t h1, h2; 3288 if (RA_is_0) b = 0; 3289 else b = *rA; 3290 EA = b + (UIMM << 3); 3291 h1 = EV_HIHALF(*rSh); 3292 h2 = EV_HIHALF(*rS); 3293 STORE(EA + 0, 2, h1); 3294 STORE(EA + 2, 2, h2); 3295 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 3296 3297 0.4,6.RS,11.RA,16.RB,21.816:EVX:e500:evstwhex %RS,%RA,%RB:Vector Store Word of Two Half Words from Even Indexed 3298 unsigned_word b; 3299 unsigned_word EA; 3300 uint16_t h1, h2; 3301 if (RA_is_0) b = 0; 3302 else b = *rA; 3303 EA = b + *rB; 3304 h1 = EV_HIHALF(*rSh); 3305 h2 = EV_HIHALF(*rS); 3306 STORE(EA + 0, 2, h1); 3307 STORE(EA + 2, 2, h2); 3308 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 3309 3310 0.4,6.RS,11.RA,16.UIMM,21.821:EVX:e500:evstwho %RS,%RA,%UIMM:Vector Store Word of Two Half Words from Odd 3311 unsigned_word b; 3312 unsigned_word EA; 3313 uint16_t h1, h2; 3314 if (RA_is_0) b = 0; 3315 else b = *rA; 3316 EA = b + (UIMM << 3); 3317 h1 = EV_LOHALF(*rSh); 3318 h2 = EV_LOHALF(*rS); 3319 STORE(EA + 0, 2, h1); 3320 STORE(EA + 2, 2, h2); 3321 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1), 0); 3322 3323 0.4,6.RS,11.RA,16.RB,21.820:EVX:e500:evstwhox %RS,%RA,%RB:Vector Store Word of Two Half Words from Odd Indexed 3324 unsigned_word b; 3325 unsigned_word EA; 3326 uint16_t h1, h2; 3327 if (RA_is_0) b = 0; 3328 else b = *rA; 3329 EA = b + *rB; 3330 h1 = EV_LOHALF(*rSh); 3331 h2 = EV_LOHALF(*rS); 3332 STORE(EA + 0, 2, h1); 3333 STORE(EA + 2, 2, h2); 3334 PPC_INSN_INT(RS_BITMASK, (RA_BITMASK & ~1) | RB_BITMASK, 0); 3335 3336 3337 # 3338 # 4.5.1 Integer Select Instruction 3339 # 3340 3341 0.31,6.RS,11.RA,16.RB,21.CRB,26.30:X:e500:isel %RS,%RA,%RB,%CRB:Integer Select 3342 if (CR & (1 << (31 - (unsigned)CRB))) 3343 if (RA_is_0) 3344 EV_SET_REG1(*rSh, *rS, 0); 3345 else 3346 EV_SET_REG2(*rSh, *rS, *rAh, *rA); 3347 else 3348 EV_SET_REG2(*rSh, *rS, *rBh, *rB); 3349 PPC_INSN_INT(RS_BITMASK, RA_BITMASK | RB_BITMASK, 0); 3350
Indexes created Wed Mar 04 15:26:31 UTC 2026