1 // ALU test program. 2 // Test 32 bit MAX, MIN, ABS instructions 3 # mach: bfin 4 5 .include "testutils.inc" 6 start 7 8 9 // MAX 10 // first operand is larger, so AN=0 11 R0.L = 0x0001; 12 R0.H = 0x0000; 13 R1.L = 0x0000; 14 R1.H = 0x0000; 15 R7 = MAX ( R0 , R1 ); 16 DBGA ( R7.L , 0x0001 ); 17 DBGA ( R7.H , 0x0000 ); 18 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); 19 CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); 20 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); 21 CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); 22 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); 23 24 // second operand is larger, so AN=1 25 R0.L = 0x0000; 26 R0.H = 0x0000; 27 R1.L = 0x0001; 28 R1.H = 0x0000; 29 R7 = MAX ( R0 , R1 ); 30 DBGA ( R7.L , 0x0001 ); 31 DBGA ( R7.H , 0x0000 ); 32 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); 33 CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); 34 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); 35 CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); 36 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); 37 38 // first operand is larger, check correct output with overflow 39 R0.L = 0xffff; 40 R0.H = 0x7fff; 41 R1.L = 0xffff; 42 R1.H = 0xffff; 43 R7 = MAX ( R0 , R1 ); 44 DBGA ( R7.L , 0xffff ); 45 DBGA ( R7.H , 0x7fff ); 46 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); 47 CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); 48 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); 49 CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); 50 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); 51 52 // second operand is larger, no overflow here 53 R0.L = 0xffff; 54 R0.H = 0xffff; 55 R1.L = 0xffff; 56 R1.H = 0x7fff; 57 R7 = MAX ( R0 , R1 ); 58 DBGA ( R7.L , 0xffff ); 59 DBGA ( R7.H , 0x7fff ); 60 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); 61 CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); 62 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); 63 CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); 64 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); 65 66 // second operand is larger, overflow 67 R0.L = 0xffff; 68 R0.H = 0x800f; 69 R1.L = 0xffff; 70 R1.H = 0x7fff; 71 R7 = MAX ( R0 , R1 ); 72 DBGA ( R7.L , 0xffff ); 73 DBGA ( R7.H , 0x7fff ); 74 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); 75 CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); 76 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); 77 CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); 78 CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 ); 79 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); 80 CC = AV0S; R7 = CC; DBGA ( R7.L , 0x0 ); 81 CC = AV1S; R7 = CC; DBGA ( R7.L , 0x0 ); 82 83 // both operands equal 84 R0.L = 0x0080; 85 R0.H = 0x8000; 86 R1.L = 0x0080; 87 R1.H = 0x8000; 88 R7 = MAX ( R0 , R1 ); 89 DBGA ( R7.L , 0x0080 ); 90 DBGA ( R7.H , 0x8000 ); 91 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); 92 CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); 93 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); 94 CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); 95 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); 96 97 // MIN 98 // second operand is smaller 99 R0.L = 0x0001; 100 R0.H = 0x0000; 101 R1.L = 0x0000; 102 R1.H = 0x0000; 103 R7 = MIN ( R0 , R1 ); 104 DBGA ( R7.L , 0x0000 ); 105 DBGA ( R7.H , 0x0000 ); 106 CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 ); 107 CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); 108 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); 109 CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); 110 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); 111 112 // first operand is smaller 113 R0.L = 0x0001; 114 R0.H = 0x8000; 115 R1.L = 0x0000; 116 R1.H = 0x0000; 117 R7 = MIN ( R0 , R1 ); 118 DBGA ( R7.L , 0x0001 ); 119 DBGA ( R7.H , 0x8000 ); 120 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); 121 CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); 122 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); 123 CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); 124 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); 125 126 // first operand is smaller, overflow 127 R0.L = 0x0001; 128 R0.H = 0x8000; 129 R1.L = 0x0000; 130 R1.H = 0x0ff0; 131 R7 = MIN ( R0 , R1 ); 132 DBGA ( R7.L , 0x0001 ); 133 DBGA ( R7.H , 0x8000 ); 134 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); 135 CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); 136 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); 137 CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); 138 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); 139 140 // equal operands 141 R0.L = 0x0001; 142 R0.H = 0x8000; 143 R1.L = 0x0001; 144 R1.H = 0x8000; 145 R7 = MIN ( R0 , R1 ); 146 DBGA ( R7.L , 0x0001 ); 147 DBGA ( R7.H , 0x8000 ); 148 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); 149 CC = AN; R7 = CC; DBGA ( R7.L , 0x1 ); 150 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); 151 CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); 152 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); 153 154 // ABS 155 R0.L = 0x0001; 156 R0.H = 0x8000; 157 R7 = ABS R0; 158 _DBG R7; 159 _DBG ASTAT; 160 R6 = ASTAT; 161 162 _DBG R6; 163 DBGA ( R7.L , 0xffff ); 164 DBGA ( R7.H , 0x7fff ); 165 //CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); 166 //CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); 167 //CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); 168 //CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); 169 //CC = VS; R7 = CC; DBGA ( R7.L , 0x1 ); 170 //CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); 171 172 R0.L = 0x0001; 173 R0.H = 0x0000; 174 R7 = ABS R0; 175 DBGA ( R7.L , 0x0001 ); 176 DBGA ( R7.H , 0x0000 ); 177 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); 178 CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); 179 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); 180 CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); 181 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); 182 183 R0.L = 0x0000; 184 R0.H = 0x8000; 185 R7 = ABS R0; 186 DBGA ( R7.L , 0xffff ); 187 DBGA ( R7.H , 0x7fff ); 188 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); 189 CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); 190 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); 191 CC = V; R7 = CC; DBGA ( R7.L , 0x1 ); 192 CC = VS; R7 = CC; DBGA ( R7.L , 0x1 ); 193 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); 194 195 R0.L = 0xffff; 196 R0.H = 0xffff; 197 R7 = ABS R0; 198 DBGA ( R7.L , 0x0001 ); 199 DBGA ( R7.H , 0x0000 ); 200 CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 ); 201 CC = AN; R7 = CC; DBGA ( R7.L , 0x0 ); 202 CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 ); 203 CC = V; R7 = CC; DBGA ( R7.L , 0x0 ); 204 CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 ); 205 206 R0.L = 0x0000; 207 R0.H = 0x0000; 208 R7 = ABS R0; 209 _DBG R7; 210 _DBG ASTAT; 211 R6 = ASTAT; 212 _DBG R6; 213 214 DBGA ( R7.L , 0x0000 ); 215 DBGA ( R7.H , 0x0000 ); 216 CC = VS; R6 = CC; DBGA (R6.L, 0x1); 217 CC = AZ; R6 = CC; DBGA (R6.L, 0x1); 218 219 pass 220
Indexes created Sun Apr 05 00:22:41 UTC 2026