1 //Original:/testcases/core/c_alu2op_divs/c_alu2op_divs.dsp 2 // Spec Reference: alu2op divide s 3 # mach: bfin 4 5 .include "testutils.inc" 6 start 7 8 9 10 imm32 r0, 0x00000000; 11 imm32 r1, 0x12345678; 12 imm32 r2, 0x23456789; 13 imm32 r3, 0x3456789a; 14 imm32 r4, 0x856789ab; 15 imm32 r5, 0x96789abc; 16 imm32 r6, 0xa789abcd; 17 imm32 r7, 0xb89abcde; 18 R0.L = 1; 19 DIVS ( R1 , R0 ); 20 DIVS ( R2 , R0 ); 21 DIVS ( R3 , R0 ); 22 DIVS ( R4 , R0 ); 23 DIVS ( R5 , R0 ); 24 DIVS ( R6 , R0 ); 25 DIVS ( R7 , R0 ); 26 DIVS ( R4 , R0 ); 27 DIVS ( R0 , R0 ); 28 CHECKREG r1, 0x2468ACF0; 29 CHECKREG r2, 0x468ACF12; 30 CHECKREG r3, 0x68ACF134; 31 CHECKREG r4, 0x159E26AE; 32 CHECKREG r5, 0x2CF13579; 33 CHECKREG r6, 0x4F13579B; 34 CHECKREG r7, 0x713579BD; 35 CHECKREG r0, 0x00000002; 36 37 imm32 r0, 0x01230002; 38 imm32 r1, 0x00000000; 39 imm32 r2, 0x93456789; 40 imm32 r3, 0xa456789a; 41 imm32 r4, 0xb56789ab; 42 imm32 r5, 0xc6789abc; 43 imm32 r6, 0xd789abcd; 44 imm32 r7, 0xe89abcde; 45 R1.L = -1; 46 DIVS ( R0 , R1 ); 47 DIVS ( R2 , R1 ); 48 DIVS ( R3 , R1 ); 49 DIVS ( R4 , R1 ); 50 DIVS ( R5 , R1 ); 51 DIVS ( R6 , R1 ); 52 DIVS ( R7 , R1 ); 53 DIVS ( R1 , R1 ); 54 CHECKREG r0, 0x02460005; 55 CHECKREG r1, 0x0001FFFF; 56 CHECKREG r2, 0x268ACF12; 57 CHECKREG r3, 0x48ACF134; 58 CHECKREG r4, 0x6ACF1356; 59 CHECKREG r5, 0x8CF13578; 60 CHECKREG r6, 0xAF13579A; 61 CHECKREG r7, 0xD13579BC; 62 63 imm32 r0, 0x51230002; 64 imm32 r1, 0x12345678; 65 imm32 r2, 0x00000000; 66 imm32 r3, 0x3456789a; 67 imm32 r4, 0x956789ab; 68 imm32 r5, 0x86789abc; 69 imm32 r6, 0x6789abcd; 70 imm32 r7, 0x789abcde; 71 R2.L = 31; 72 DIVS ( R0 , R2 ); 73 DIVS ( R1 , R2 ); 74 DIVS ( R3 , R2 ); 75 DIVS ( R4 , R2 ); 76 DIVS ( R5 , R2 ); 77 DIVS ( R6 , R2 ); 78 DIVS ( R7 , R2 ); 79 DIVS ( R2 , R2 ); 80 CHECKREG r0, 0xA2460004; 81 CHECKREG r1, 0x2468ACF0; 82 CHECKREG r2, 0x0000003E; 83 CHECKREG r3, 0x68ACF134; 84 CHECKREG r4, 0x2ACF1357; 85 CHECKREG r5, 0x0CF13579; 86 CHECKREG r6, 0xCF13579A; 87 CHECKREG r7, 0xF13579BC; 88 89 imm32 r0, 0x01230002; 90 imm32 r1, 0x82345678; 91 imm32 r2, 0x93456789; 92 imm32 r3, 0x00000000; 93 imm32 r4, 0xb56789ab; 94 imm32 r5, 0xc6789abc; 95 imm32 r6, 0xd789abcd; 96 imm32 r7, 0xe89abcde; 97 R3.L = -31; 98 DIVS ( R0 , R3 ); 99 DIVS ( R1 , R3 ); 100 DIVS ( R2 , R3 ); 101 DIVS ( R4 , R3 ); 102 DIVS ( R5 , R3 ); 103 DIVS ( R6 , R3 ); 104 DIVS ( R7 , R3 ); 105 DIVS ( R3 , R3 ); 106 CHECKREG r0, 0x02460005; 107 CHECKREG r1, 0x0468ACF0; 108 CHECKREG r2, 0x268ACF12; 109 CHECKREG r3, 0x0001FFC3; 110 CHECKREG r4, 0x6ACF1356; 111 CHECKREG r5, 0x8CF13578; 112 CHECKREG r6, 0xAF13579A; 113 CHECKREG r7, 0xD13579BC; 114 115 imm32 r0, 0x00000001; 116 imm32 r1, 0x12345678; 117 imm32 r2, 0x23456789; 118 imm32 r3, 0x3456789a; 119 imm32 r4, 0x00000000; 120 imm32 r5, 0x96789abc; 121 imm32 r6, 0xa789abcd; 122 imm32 r7, 0xb89abcde; 123 R4.L = 15; 124 DIVS ( R1 , R4 ); 125 DIVS ( R2 , R4 ); 126 DIVS ( R3 , R4 ); 127 DIVS ( R0 , R4 ); 128 DIVS ( R5 , R4 ); 129 DIVS ( R6 , R4 ); 130 DIVS ( R7 , R4 ); 131 DIVS ( R4 , R4 ); 132 CHECKREG r0, 0x00000002; 133 CHECKREG r1, 0x2468ACF0; 134 CHECKREG r2, 0x468ACF12; 135 CHECKREG r3, 0x68ACF134; 136 CHECKREG r4, 0x0000001E; 137 CHECKREG r5, 0x2CF13579; 138 CHECKREG r6, 0x4F13579B; 139 CHECKREG r7, 0x713579BD; 140 141 imm32 r0, 0x01230002; 142 imm32 r1, 0x00000000; 143 imm32 r2, 0x93456789; 144 imm32 r3, 0xa456789a; 145 imm32 r4, 0xb56789ab; 146 imm32 r5, 0x00000000; 147 imm32 r6, 0xd789abcd; 148 imm32 r7, 0xe89abcde; 149 R5.L = -15; 150 DIVS ( R0 , R5 ); 151 DIVS ( R1 , R5 ); 152 DIVS ( R2 , R5 ); 153 DIVS ( R3 , R5 ); 154 DIVS ( R4 , R5 ); 155 DIVS ( R6 , R5 ); 156 DIVS ( R7 , R5 ); 157 DIVS ( R5 , R5 ); 158 CHECKREG r0, 0x02460005; 159 CHECKREG r1, 0x00000001; 160 CHECKREG r2, 0x268ACF12; 161 CHECKREG r3, 0x48ACF134; 162 CHECKREG r4, 0x6ACF1356; 163 CHECKREG r5, 0x0001FFE3; 164 CHECKREG r6, 0xAF13579A; 165 CHECKREG r7, 0xD13579BC; 166 167 imm32 r0, 0x51230002; 168 imm32 r1, 0x12345678; 169 imm32 r2, 0xb1256790; 170 imm32 r3, 0x3456789a; 171 imm32 r4, 0x956789ab; 172 imm32 r5, 0x86789abc; 173 imm32 r6, 0x00000000; 174 imm32 r7, 0x789abcde; 175 R6.L = 24; 176 DIVS ( R0 , R6 ); 177 DIVS ( R1 , R6 ); 178 DIVS ( R2 , R6 ); 179 DIVS ( R3 , R6 ); 180 DIVS ( R4 , R6 ); 181 DIVS ( R5 , R6 ); 182 DIVS ( R7 , R6 ); 183 DIVS ( R6 , R6 ); 184 CHECKREG r0, 0xA2460004; 185 CHECKREG r1, 0x2468ACF0; 186 CHECKREG r2, 0x624ACF21; 187 CHECKREG r3, 0x68ACF134; 188 CHECKREG r4, 0x2ACF1357; 189 CHECKREG r5, 0x0CF13579; 190 CHECKREG r6, 0x00000030; 191 CHECKREG r7, 0xF13579BC; 192 193 imm32 r0, 0x01230002; 194 imm32 r1, 0x82345678; 195 imm32 r2, 0x93456789; 196 imm32 r3, 0xa456789a; 197 imm32 r4, 0xb56789ab; 198 imm32 r5, 0xc6789abc; 199 imm32 r6, 0xd789abcd; 200 imm32 r7, 0x00000000; 201 R7.L = -24; 202 DIVS ( R0 , R7 ); 203 DIVS ( R1 , R7 ); 204 DIVS ( R2 , R7 ); 205 DIVS ( R3 , R7 ); 206 DIVS ( R4 , R7 ); 207 DIVS ( R5 , R7 ); 208 DIVS ( R6 , R7 ); 209 DIVS ( R7 , R7 ); 210 CHECKREG r0, 0x02460005; 211 CHECKREG r1, 0x0468ACF0; 212 CHECKREG r2, 0x268ACF12; 213 CHECKREG r3, 0x48ACF134; 214 CHECKREG r4, 0x6ACF1356; 215 CHECKREG r5, 0x8CF13578; 216 CHECKREG r6, 0xAF13579A; 217 CHECKREG r7, 0x0001FFD1; 218 219 220 pass 221
Indexes created Thu Mar 19 00:23:35 UTC 2026