1 //Original:/testcases/core/c_dsp32mult_dr_i/c_dsp32mult_dr_i.dsp 2 // Spec Reference: dsp32mult single dr i 3 # mach: bfin 4 5 .include "testutils.inc" 6 start 7 8 imm32 r0, 0x8b235625; 9 imm32 r1, 0x98ba5127; 10 imm32 r2, 0xa3846725; 11 imm32 r3, 0x00080027; 12 imm32 r4, 0xb0ab8d29; 13 imm32 r5, 0x10ace82b; 14 imm32 r6, 0xc00c008d; 15 imm32 r7, 0xd2467028; 16 R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IS); 17 R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (IS); 18 R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (IS); 19 R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (IS); 20 R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (IS); 21 R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (IS); 22 R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (IS); 23 R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (IS); 24 CHECKREG r0, 0x7FFF7FFF; 25 CHECKREG r1, 0x7FFF8000; 26 CHECKREG r2, 0x80007FFF; 27 CHECKREG r3, 0x7FFF7FFF; 28 CHECKREG r4, 0x7FFF7FFF; 29 CHECKREG r5, 0x7FFF8000; 30 CHECKREG r6, 0x7FFF8000; 31 CHECKREG r7, 0x7FFF7FFF; 32 33 imm32 r0, 0x8923a635; 34 imm32 r1, 0x6f995137; 35 imm32 r2, 0x1824b735; 36 imm32 r3, 0x99860037; 37 imm32 r4, 0x8098cd39; 38 imm32 r5, 0xb0a98f3b; 39 imm32 r6, 0xa00c083d; 40 imm32 r7, 0x12467083; 41 R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IS); 42 R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (IS); 43 R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (IS); 44 R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (IS); 45 R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (IS); 46 R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (IS); 47 R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (IS); 48 R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (IS); 49 CHECKREG r0, 0x80008000; 50 CHECKREG r1, 0x7FFF7FFF; 51 CHECKREG r2, 0x80008000; 52 CHECKREG r3, 0x7FFF7FFF; 53 CHECKREG r4, 0x80008000; 54 CHECKREG r5, 0x7FFF8000; 55 CHECKREG r6, 0x80007FFF; 56 CHECKREG r7, 0x80008000; 57 58 imm32 r0, 0x19235655; 59 imm32 r1, 0xc9ba5157; 60 imm32 r2, 0x63246755; 61 imm32 r3, 0x0a060055; 62 imm32 r4, 0x90abc509; 63 imm32 r5, 0x10acef5b; 64 imm32 r6, 0xb00a005d; 65 imm32 r7, 0x1246a05f; 66 R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (IS); 67 R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (IS); 68 R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (IS); 69 R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (IS); 70 R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (IS); 71 R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (IS); 72 R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (IS); 73 R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (IS); 74 CHECKREG r0, 0x7FFF7FFF; 75 CHECKREG r1, 0x7FFF8000; 76 CHECKREG r2, 0x80008000; 77 CHECKREG r3, 0x7FFF7FFF; 78 CHECKREG r4, 0x7FFF7FFF; 79 CHECKREG r5, 0x80008000; 80 CHECKREG r6, 0x80008000; 81 CHECKREG r7, 0x7FFF7FFF; 82 83 imm32 r0, 0xbb235666; 84 imm32 r1, 0xefba5166; 85 imm32 r2, 0x13248766; 86 imm32 r3, 0xe0060066; 87 imm32 r4, 0x9eab9d69; 88 imm32 r5, 0x10ecef6b; 89 imm32 r6, 0x800ee06d; 90 imm32 r7, 0x12467e6f; 91 // test the unsigned U=1 92 R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (IS); 93 R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (IS); 94 R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (IS); 95 R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (IS); 96 R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (IS); 97 R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (IS); 98 R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (IS); 99 R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (IS); 100 CHECKREG r0, 0x7FFF7FFF; 101 CHECKREG r1, 0x80008000; 102 CHECKREG r2, 0x80008000; 103 CHECKREG r3, 0x7FFF7FFF; 104 CHECKREG r4, 0x7FFF7FFF; 105 CHECKREG r5, 0x7FFF7FFF; 106 CHECKREG r6, 0x7FFF7FFF; 107 CHECKREG r7, 0x7FFF7FFF; 108 109 // mix order 110 imm32 r0, 0xac23a675; 111 imm32 r1, 0xcfba5127; 112 imm32 r2, 0x13c46705; 113 imm32 r3, 0xf0060007; 114 imm32 r4, 0x9faccd09; 115 imm32 r5, 0x10fcdfdb; 116 imm32 r6, 0x000fc00d; 117 imm32 r7, 0x1246ff0f; 118 R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (IS); 119 R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (IS); 120 R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (IS); 121 R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (IS); 122 R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (IS); 123 R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (IS); 124 R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (IS); 125 R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (IS); 126 CHECKREG r0, 0x7FFF8000; 127 CHECKREG r1, 0x80007FFF; 128 CHECKREG r2, 0x80008000; 129 CHECKREG r3, 0x80008000; 130 CHECKREG r4, 0x7FFF7FFF; 131 CHECKREG r5, 0x80008000; 132 CHECKREG r6, 0x80008000; 133 CHECKREG r7, 0x80007FFF; 134 135 imm32 r0, 0xab235a75; 136 imm32 r1, 0xcfba5127; 137 imm32 r2, 0xdd246905; 138 imm32 r3, 0x00d6d007; 139 imm32 r4, 0x90abcd09; 140 imm32 r5, 0x10aceddb; 141 imm32 r6, 0x000c0d0d; 142 imm32 r7, 0x1246700f; 143 R0.H = R5.H * R0.H, R0.L = R5.H * R0.L (IS); 144 R1.H = R6.H * R1.L, R1.L = R6.L * R1.L (IS); 145 R2.H = R7.H * R2.H, R2.L = R7.H * R2.H (IS); 146 R3.H = R0.L * R3.H, R3.L = R0.H * R3.L (IS); 147 R4.H = R1.H * R4.H, R4.L = R1.L * R4.L (IS); 148 R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (IS); 149 R6.H = R3.H * R6.H, R6.L = R3.L * R6.L (IS); 150 R7.H = R4.L * R7.H, R7.L = R4.H * R7.H (IS); 151 CHECKREG r0, 0x80007FFF; 152 CHECKREG r1, 0x7FFF7FFF; 153 CHECKREG r2, 0x80008000; 154 CHECKREG r3, 0x7FFF7FFF; 155 CHECKREG r4, 0x80008000; 156 CHECKREG r5, 0x80007FFF; 157 CHECKREG r6, 0x7FFF7FFF; 158 CHECKREG r7, 0x80008000; 159 160 imm32 r0, 0xfb235675; 161 imm32 r1, 0xcfba5127; 162 imm32 r2, 0x13f46705; 163 imm32 r3, 0x000f0007; 164 imm32 r4, 0x90abfd09; 165 imm32 r5, 0x10acefdb; 166 imm32 r6, 0x000c00fd; 167 imm32 r7, 0x1246700f; 168 R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (IS); 169 R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (IS); 170 R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (IS); 171 R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (IS); 172 R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (IS); 173 R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (IS); 174 R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (IS); 175 R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (IS); 176 CHECKREG r0, 0x7FFF8000; 177 CHECKREG r1, 0x80007FFF; 178 CHECKREG r2, 0x7FFF7FFF; 179 CHECKREG r3, 0x80008000; 180 CHECKREG r4, 0x80008000; 181 CHECKREG r5, 0x7FFF8000; 182 CHECKREG r6, 0x80008000; 183 CHECKREG r7, 0x80007FFF; 184 185 imm32 r0, 0xab2d5675; 186 imm32 r1, 0xcfbad127; 187 imm32 r2, 0x13246d05; 188 imm32 r3, 0x000600d7; 189 imm32 r4, 0x908bcd09; 190 imm32 r5, 0x10a9efdb; 191 imm32 r6, 0x000c500d; 192 imm32 r7, 0x1246760f; 193 R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (IS); 194 R6.H = R6.H * R3.L, R6.L = R6.H * R3.H (IS); 195 R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (IS); 196 R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (IS); 197 R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (IS); 198 R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (IS); 199 R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (IS); 200 R7.H = R4.H * R1.L, R7.L = R4.H * R1.H (IS); 201 CHECKREG r0, 0x80008000; 202 CHECKREG r1, 0x80007FFF; 203 CHECKREG r2, 0x7FFF7FFF; 204 CHECKREG r3, 0x80008000; 205 CHECKREG r4, 0x80008000; 206 CHECKREG r5, 0x7FFF7FFF; 207 CHECKREG r6, 0x0A140048; 208 CHECKREG r7, 0x80007FFF; 209 210 211 212 pass 213
Indexes created Sun May 31 00:26:10 UTC 2026