1 //Original:/testcases/core/c_dsp32shiftim_ahh_s/c_dsp32shiftim_ahh_s.dsp 2 # mach: bfin 3 4 .include "testutils.inc" 5 start 6 7 8 // Spec Reference: dsp32shiftimm ashift: ashift / ashift saturated 9 10 11 12 imm32 r0, 0x01230abc; 13 imm32 r1, 0x12345678; 14 imm32 r2, 0x23456789; 15 imm32 r3, 0x3456789a; 16 imm32 r4, 0x456789ab; 17 imm32 r5, 0x56789abc; 18 imm32 r6, 0x6789abcd; 19 imm32 r7, 0x789abcde; 20 R0 = R0 << 0 (V , S); 21 R1 = R1 << 3 (V , S); 22 R2 = R2 << 5 (V , S); 23 R3 = R3 << 8 (V , S); 24 R4 = R4 << 9 (V , S); 25 R5 = R5 << 15 (V , S); 26 R6 = R6 << 7 (V , S); 27 R7 = R7 << 13 (V , S); 28 CHECKREG r0, 0x01230ABC; 29 CHECKREG r1, 0x7FFF7FFF; 30 CHECKREG r2, 0x7FFF7FFF; 31 CHECKREG r3, 0x7FFF7FFF; 32 CHECKREG r4, 0x7FFF8000; 33 CHECKREG r5, 0x7FFF8000; 34 CHECKREG r6, 0x7FFF8000; 35 CHECKREG r7, 0x7FFF8000; 36 37 imm32 r0, 0x01230000; 38 imm32 r1, 0x12345678; 39 imm32 r2, 0x23456789; 40 imm32 r3, 0x3456789a; 41 imm32 r4, 0x456789ab; 42 imm32 r5, 0x56789abc; 43 imm32 r6, 0x6789abcd; 44 imm32 r7, 0x789abcde; 45 R7 = R0 >>> 1 (V, S); 46 R0 = R1 >>> 8 (V, S); 47 R1 = R2 >>> 14 (V, S); 48 R2 = R3 >>> 15 (V, S); 49 R3 = R4 >>> 11 (V, S); 50 R4 = R5 >>> 4 (V, S); 51 R5 = R6 >>> 9 (V, S); 52 R6 = R7 >>> 6 (V, S); 53 CHECKREG r0, 0x00120056; 54 CHECKREG r1, 0x00000001; 55 CHECKREG r2, 0x00000000; 56 CHECKREG r3, 0x0008FFF1; 57 CHECKREG r4, 0x0567F9AB; 58 CHECKREG r5, 0x0033FFD5; 59 CHECKREG r6, 0x00020000; 60 CHECKREG r7, 0x00910000; 61 62 63 64 65 pass 66
Indexes created Wed Aug 12 00:25:48 UTC 2026