1 //Original:/proj/frio/dv/testcases/core/c_interr_nested/c_interr_nested.dsp 2 // Spec Reference: interrupt nested using raises 3 # mach: bfin 4 # sim: --environment operating 5 6 #include "test.h" 7 .include "testutils.inc" 8 start 9 10 include(std.inc) 11 include(selfcheck.inc) 12 include(gen_int.inc) 13 INIT_R_REGS(0); 14 INIT_P_REGS(0); 15 INIT_I_REGS(0); // initialize the dsp address regs 16 INIT_M_REGS(0); 17 INIT_L_REGS(0); 18 INIT_B_REGS(0); 19 //CHECK_INIT(p5, 0xe0000000); 20 include(symtable.inc) 21 CHECK_INIT_DEF(p5); 22 23 #ifndef STACKSIZE 24 #define STACKSIZE 0x10 25 #endif 26 #ifndef EVT 27 #define EVT 0xFFE02000 28 #endif 29 #ifndef EVT15 30 #define EVT15 0xFFE0203C 31 #endif 32 #ifndef EVT_OVERRIDE 33 #define EVT_OVERRIDE 0xFFE02100 34 #endif 35 #ifndef ITABLE 36 #define ITABLE 0xF0000000 37 #endif 38 39 GEN_INT_INIT(ITABLE) // set location for interrupt table 40 41 // 42 // Reset/Bootstrap Code 43 // (Here we should set the processor operating modes, initialize registers, 44 // etc.) 45 // 46 47 BOOT: 48 49 50 LD32_LABEL(sp, KSTACK); // setup the stack pointer 51 FP = SP; // and frame pointer 52 53 LD32(p0, EVT); // Setup Event Vectors and Handlers 54 LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) 55 [ P0 ++ ] = R0; 56 57 LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) 58 [ P0 ++ ] = R0; 59 60 LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) 61 [ P0 ++ ] = R0; 62 63 LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) 64 [ P0 ++ ] = R0; 65 66 [ P0 ++ ] = R0; // IVT4 not used 67 68 LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) 69 [ P0 ++ ] = R0; 70 71 LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) 72 [ P0 ++ ] = R0; 73 74 LD32_LABEL(r0, I7HANDLE); // IVG7 Handler 75 [ P0 ++ ] = R0; 76 77 LD32_LABEL(r0, I8HANDLE); // IVG8 Handler 78 [ P0 ++ ] = R0; 79 80 LD32_LABEL(r0, I9HANDLE); // IVG9 Handler 81 [ P0 ++ ] = R0; 82 83 LD32_LABEL(r0, I10HANDLE);// IVG10 Handler 84 [ P0 ++ ] = R0; 85 86 LD32_LABEL(r0, I11HANDLE);// IVG11 Handler 87 [ P0 ++ ] = R0; 88 89 LD32_LABEL(r0, I12HANDLE);// IVG12 Handler 90 [ P0 ++ ] = R0; 91 92 LD32_LABEL(r0, I13HANDLE);// IVG13 Handler 93 [ P0 ++ ] = R0; 94 95 LD32_LABEL(r0, I14HANDLE);// IVG14 Handler 96 [ P0 ++ ] = R0; 97 98 LD32_LABEL(r0, I15HANDLE);// IVG15 Handler 99 [ P0 ++ ] = R0; 100 101 LD32(p0, EVT_OVERRIDE); 102 R0 = 0; 103 [ P0 ++ ] = R0; 104 R0 = -1; // Change this to mask interrupts (*) 105 [ P0 ] = R0; // IMASK 106 107 DUMMY: 108 109 R0 = 0 (Z); 110 111 LT0 = r0; // set loop counters to something deterministic 112 LB0 = r0; 113 LC0 = r0; 114 LT1 = r0; 115 LB1 = r0; 116 LC1 = r0; 117 118 ASTAT = r0; // reset other internal regs 119 120 // The following code sets up the test for running in USER mode 121 122 LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a 123 // ReturnFromInterrupt (RTI) 124 RETI = r0; // We need to load the return address 125 126 // Comment the following line for a USER Mode test 127 128 JUMP STARTSUP; // jump to code start for SUPERVISOR mode 129 130 RTI; 131 132 STARTSUP: 133 LD32_LABEL(p1, BEGIN); 134 135 LD32(p0, EVT15); 136 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start 137 CSYNC; 138 RAISE 15; // after we RTI, INT 15 should be taken 139 140 RTI; 141 142 // 143 // The Main Program 144 // 145 STARTUSER: 146 LD32_LABEL(sp, USTACK); // setup the stack pointer 147 FP = SP; // set frame pointer 148 JUMP BEGIN; 149 150 //********************************************************************* 151 152 BEGIN: 153 154 // COMMENT the following line for USER MODE tests 155 [ -- SP ] = RETI; // enable interrupts in supervisor mode 156 157 // **** YOUR CODE GOES HERE **** 158 159 160 161 // PUT YOUR TEST HERE! 162 // Can't Raise 0, 3, or 4 163 // Raise 1 requires some intelligence so the test 164 // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) 165 RAISE 2; // RTN 166 // RAISE 5; // RTI 167 RAISE 6; // RTI 168 RAISE 7; // RTI 169 // RAISE 8; // RTI 170 RAISE 9; // RTI 171 RAISE 10; // RTI 172 RAISE 11; // RTI 173 // RAISE 12; // RTI 174 RAISE 13; // RTI 175 RAISE 14; // RTI 176 RAISE 15; // RTI 177 178 CHECKREG(r0, 0x0000000B); 179 CHECKREG(r1, 0x0000000C); 180 CHECKREG(r2, 0x0000000D); 181 CHECKREG(r3, 0x0000000E); 182 CHECKREG(r4, 0x00000007); 183 CHECKREG(r5, 0x00000008); 184 CHECKREG(r6, 0x00000009); 185 CHECKREG(r7, 0x0000000A); 186 R0 = I0; 187 R1 = I1; 188 R2 = I2; 189 R3 = I3; 190 R4 = M0; 191 CHECKREG(r0, 0x00000002); 192 CHECKREG(r1, 0x00000000); 193 CHECKREG(r2, 0x00000005); 194 CHECKREG(r3, 0x00000006); 195 CHECKREG(r4, 0x00000007); 196 197 198 END: 199 dbg_pass; // End the test 200 201 //********************************************************************* 202 203 // 204 // Handlers for Events 205 // 206 207 EHANDLE: // Emulation Handler 0 208 RTE; 209 210 RHANDLE: // Reset Handler 1 211 RTI; 212 213 NHANDLE: // NMI Handler 2 214 R0 = 2; 215 RTN; 216 217 XHANDLE: // Exception Handler 3 218 R1 = 3; 219 RTX; 220 221 HWHANDLE: // HW Error Handler 5 222 R2 = 5; 223 RTI; 224 225 THANDLE: // Timer Handler 6 226 R3 = 6; 227 RAISE 5; 228 RTI; 229 230 I7HANDLE: // IVG 7 Handler 231 R4 = 7; 232 RTI; 233 234 I8HANDLE: // IVG 8 Handler 235 R5 = 8; 236 RTI; 237 238 I9HANDLE: // IVG 9 Handler 239 R6 = 9; 240 RAISE 8; 241 RTI; 242 243 I10HANDLE: // IVG 10 Handler 244 R7 = 10; 245 RTI; 246 247 I11HANDLE: // IVG 11 Handler 248 I0 = R0; 249 I1 = R1; 250 I2 = R2; 251 I3 = R3; 252 M0 = R4; 253 R0 = 11; 254 RTI; 255 256 I12HANDLE: // IVG 12 Handler 257 R1 = 12; 258 RTI; 259 260 I13HANDLE: // IVG 13 Handler 261 R2 = 13; 262 RTI; 263 264 I14HANDLE: // IVG 14 Handler 265 R3 = 14; 266 RAISE 12; 267 RTI; 268 269 I15HANDLE: // IVG 15 Handler 270 R4 = 15; 271 RTI; 272 273 NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug 274 275 // 276 // Data Segment 277 // 278 279 .data 280 DATA: 281 .space (0x10); 282 283 // Stack Segments (Both Kernel and User) 284 285 .space (STACKSIZE); 286 KSTACK: 287 288 .space (STACKSIZE); 289 USTACK: 290
Indexes created Sat Feb 28 05:31:39 UTC 2026