1 //Original:/proj/frio/dv/testcases/core/c_interr_timer_reload/c_interr_timer_reload.dsp 2 // Spec Reference: interrupt on HW TIMER auto-reload 3 # mach: bfin 4 # sim: --environment operating 5 6 #include "test.h" 7 .include "testutils.inc" 8 start 9 10 // 11 // Include Files 12 // 13 14 include(std.inc) 15 include(selfcheck.inc) 16 17 // Defines 18 19 #ifndef TCNTL 20 #define TCNTL 0xFFE03000 21 #endif 22 #ifndef TPERIOD 23 #define TPERIOD 0xFFE03004 24 #endif 25 #ifndef TSCALE 26 #define TSCALE 0xFFE03008 27 #endif 28 #ifndef TCOUNT 29 #define TCOUNT 0xFFE0300c 30 #endif 31 #ifndef EVT 32 #define EVT 0xFFE02000 33 #endif 34 #ifndef EVT15 35 #define EVT15 0xFFE0203c 36 #endif 37 #ifndef EVT_OVERRIDE 38 #define EVT_OVERRIDE 0xFFE02100 39 #endif 40 #ifndef ITABLE 41 #define ITABLE 0x000FF000 42 #endif 43 #ifndef PROGRAM_STACK 44 #define PROGRAM_STACK 0x000FF100 45 #endif 46 #ifndef STACKSIZE 47 #define STACKSIZE 0x00000300 48 #endif 49 50 // Boot code 51 52 BOOT : 53 INIT_R_REGS(0); // Initialize Dregs 54 INIT_P_REGS(0); // Initialize Pregs 55 56 // CHECK_INIT(p5, 0x00BFFFFC); 57 // CHECK_INIT(p5, 0xE0000000); 58 include(symtable.inc) 59 CHECK_INIT_DEF(p5); 60 61 62 LD32(sp, 0x000FF200); 63 LD32(p0, EVT); // Setup Event Vectors and Handlers 64 65 LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) 66 [ P0 ++ ] = R0; 67 68 LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) 69 [ P0 ++ ] = R0; 70 71 LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) 72 [ P0 ++ ] = R0; 73 74 LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) 75 [ P0 ++ ] = R0; 76 77 [ P0 ++ ] = R0; // IVT4 not used 78 79 LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) 80 [ P0 ++ ] = R0; 81 82 LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) 83 [ P0 ++ ] = R0; 84 85 LD32_LABEL(r0, I7HANDLE); // IVG7 Handler 86 [ P0 ++ ] = R0; 87 88 LD32_LABEL(r0, I8HANDLE); // IVG8 Handler 89 [ P0 ++ ] = R0; 90 91 LD32_LABEL(r0, I9HANDLE); // IVG9 Handler 92 [ P0 ++ ] = R0; 93 94 LD32_LABEL(r0, I10HANDLE); // IVG10 Handler 95 [ P0 ++ ] = R0; 96 97 LD32_LABEL(r0, I11HANDLE); // IVG11 Handler 98 [ P0 ++ ] = R0; 99 100 LD32_LABEL(r0, I12HANDLE); // IVG12 Handler 101 [ P0 ++ ] = R0; 102 103 LD32_LABEL(r0, I13HANDLE); // IVG13 Handler 104 [ P0 ++ ] = R0; 105 106 LD32_LABEL(r0, I14HANDLE); // IVG14 Handler 107 [ P0 ++ ] = R0; 108 109 LD32_LABEL(r0, I15HANDLE); // IVG15 Handler 110 [ P0 ++ ] = R0; 111 112 LD32(p0, EVT_OVERRIDE); 113 R0 = 0; 114 [ P0 ++ ] = R0; 115 R0 = -1; // Change this to mask interrupts (*) 116 [ P0 ] = R0; // IMASK 117 118 LD32_LABEL(p1, START); 119 120 LD32(p0, EVT15); 121 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start 122 CSYNC; 123 124 RAISE 15; // after we RTI, INT 15 should be taken 125 126 LD32_LABEL(r7, START); 127 RETI = r7; 128 NOP; // Workaround for Bug 217 129 RTI; 130 NOP; 131 NOP; 132 133 //.code 0x200 134 START : 135 R7 = 0x0; 136 R6 = 0x1; 137 [ -- SP ] = RETI; // Enable Nested Interrupts 138 139 WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) 140 WR_MMR(TPERIOD, 0x00000020, p0, r0); 141 WR_MMR(TCOUNT, 0x00000002, p0, r0); 142 WR_MMR(TSCALE, 0x00000005, p0, r0); 143 CSYNC; 144 // Read the contents of the Timer 145 146 RD_MMR(TPERIOD, p0, r2); 147 CHECKREG(r2, 0x00000020); 148 149 RD_MMR(TCOUNT, p0, r3); 150 CHECKREG(r3, 0x00000002);// fsim -ro useChecker=regtrace 151 152 153 WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) 154 CSYNC; 155 156 157 158 NOP; NOP; NOP; NOP; NOP; 159 NOP; NOP; NOP; NOP; NOP; 160 NOP; NOP; NOP; NOP; NOP; 161 162 RD_MMR(TCOUNT, p0, r4); 163 CHECKREG(r4, 0x00000000); 164 165 RD_MMR(TCNTL, p0, r5); 166 CHECKREG(r5, 0x0000000B); 167 168 WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer 169 CSYNC; 170 CHECKREG(r7, 0x00000001); 171 R7 = 0; 172 NOP; 173 WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power 174 WR_MMR(TPERIOD, 0x00000020, p0, r0); 175 WR_MMR(TCOUNT, 0x00000003, p0, r0); 176 WR_MMR(TSCALE, 0x00000002, p0, r0); 177 WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer auo-reload 178 CSYNC; 179 NOP; NOP; NOP; NOP; NOP; 180 NOP; NOP; NOP; NOP; NOP; 181 NOP; NOP; NOP; NOP; NOP; 182 NOP; NOP; NOP; NOP; NOP; 183 // With auto reload 184 // Read the contents of the Timer 185 186 // CHECKREG(r7, 0x00000002); 187 CC = R7 == 0; 188 IF !CC JUMP LABEL1; 189 WR_MMR(TPERIOD, 0x00000030, p0, r0); // SHOULD NOT EXECUTE 190 191 LABEL1: 192 193 194 RD_MMR(TPERIOD, p0, r2); 195 CHECKREG(r2, 0x00000020); 196 197 RD_MMR(TCNTL , p0, r3); 198 CHECKREG(r3, 0x0000000F); 199 200 WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer but not auto-reload 201 CSYNC; 202 203 NOP; NOP; NOP; NOP; 204 NOP; NOP; NOP; NOP; 205 NOP; NOP; NOP; NOP; 206 NOP; NOP; NOP; NOP; 207 NOP; NOP; NOP; NOP; 208 NOP; NOP; NOP; NOP; 209 NOP; NOP; NOP; NOP; 210 RD_MMR(TCOUNT, p0, r4); 211 CHECKREG(r4, 0x00000000); 212 213 RD_MMR(TCNTL, p0, r5); 214 CHECKREG(r5, 0x0000000B); 215 216 WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer 217 CSYNC; 218 NOP; NOP; NOP; 219 220 221 222 223 224 dbg_pass; // Call Endtest Macro 225 226 227 228 //********************************************************************* 229 // 230 // Handlers for Events 231 // 232 233 EHANDLE: // Emulation Handler 0 234 RTE; 235 236 RHANDLE: // Reset Handler 1 237 RTI; 238 239 NHANDLE: // NMI Handler 2 240 RTN; 241 242 XHANDLE: // Exception Handler 3 243 RTX; 244 245 HWHANDLE: // HW Error Handler 5 246 RTI; 247 248 THANDLE: // Timer Handler 6 249 R7 = R7 + R6; 250 RTI; 251 252 I7HANDLE: // IVG 7 Handler 253 RTI; 254 255 I8HANDLE: // IVG 8 Handler 256 RTI; 257 258 I9HANDLE: // IVG 9 Handler 259 RTI; 260 261 I10HANDLE: // IVG 10 Handler 262 RTI; 263 264 I11HANDLE: // IVG 11 Handler 265 RTI; 266 267 I12HANDLE: // IVG 12 Handler 268 RTI; 269 270 I13HANDLE: // IVG 13 Handler 271 RTI; 272 273 I14HANDLE: // IVG 14 Handler 274 RTI; 275 276 I15HANDLE: // IVG 15 Handler 277 R5 = RETI; 278 P0 = R5; 279 JUMP ( P0 ); 280 RTI; 281 282 .section MEM_DATA_ADDR_1,"aw" 283 284 .space (STACKSIZE); 285 STACK: 286 NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug 287
Indexes created Sat Feb 28 05:31:39 UTC 2026