1 //Original:/proj/frio/dv/testcases/debug/dbg_tr_simplejp/dbg_tr_simplejp.dsp 2 // Description: This test performs simple jumps and verifies the trace buffer 3 // recording for simple jumps. 4 # mach: bfin 5 # sim: --environment operating 6 7 #include "test.h" 8 .include "testutils.inc" 9 start 10 11 include(std.inc) 12 include(mmrs.inc) 13 include(selfcheck.inc) 14 include(symtable.inc) 15 16 #ifndef ITABLE 17 #define ITABLE CODE_ADDR_1 // 18 #endif 19 20 // This test embeds .text offsets, so pad our test so it lines up. 21 .space 0x5e 22 23 // Boot code 24 25 BOOT : 26 INIT_R_REGS(0); // Initialize Dregs 27 INIT_P_REGS(0); // Initialize Pregs 28 29 CHECK_INIT_DEF(p5); // CHECK_INIT(p5, 0x00BFFFFC); 30 31 LD32(p0, EVT0); // Setup Event Vectors and Handlers 32 33 LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) 34 [ P0 ++ ] = R0; 35 36 LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) 37 [ P0 ++ ] = R0; 38 39 LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) 40 [ P0 ++ ] = R0; 41 42 LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) 43 [ P0 ++ ] = R0; 44 45 [ P0 ++ ] = R0; // IVT4 not used 46 47 LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) 48 [ P0 ++ ] = R0; 49 50 LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) 51 [ P0 ++ ] = R0; 52 53 LD32_LABEL(r0, I7HANDLE); // IVG7 Handler 54 [ P0 ++ ] = R0; 55 56 LD32_LABEL(r0, I8HANDLE); // IVG8 Handler 57 [ P0 ++ ] = R0; 58 59 LD32_LABEL(r0, I9HANDLE); // IVG9 Handler 60 [ P0 ++ ] = R0; 61 62 LD32_LABEL(r0, I10HANDLE); // IVG10 Handler 63 [ P0 ++ ] = R0; 64 65 LD32_LABEL(r0, I11HANDLE); // IVG11 Handler 66 [ P0 ++ ] = R0; 67 68 LD32_LABEL(r0, I12HANDLE); // IVG12 Handler 69 [ P0 ++ ] = R0; 70 71 LD32_LABEL(r0, I13HANDLE); // IVG13 Handler 72 [ P0 ++ ] = R0; 73 74 LD32_LABEL(r0, I14HANDLE); // IVG14 Handler 75 [ P0 ++ ] = R0; 76 77 LD32_LABEL(r0, I15HANDLE); // IVG15 Handler 78 [ P0 ++ ] = R0; 79 80 LD32(p0, EVT_OVERRIDE); 81 R0 = 0; 82 [ P0 ++ ] = R0; 83 R0 = -1; // Change this to mask interrupts (*) 84 [ P0 ] = R0; // IMASK 85 86 LD32_LABEL(p1, START); 87 88 LD32(p0, EVT15); 89 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start 90 91 LD32_LABEL(r7, DUMMY); 92 RETI = r7; 93 RAISE 15; // after we RTI, INT 15 should be taken 94 95 NOP; // Workaround for Bug 217 96 RTI; 97 NOP; 98 NOP; 99 NOP; 100 DUMMY: 101 NOP; 102 NOP; 103 NOP; 104 NOP; 105 106 107 108 START : 109 WR_MMR(TBUFCTL, 0x00000003, p0, r0); // Turn ON trace Buffer 110 // TBUFPWR = 1 111 // TBUFEN = 1 112 // TBUFOVF = 0 113 // CMPLP = 0 114 NOP; 115 NOP; 116 NOP; 117 NOP; 118 NOP; 119 NOP; 120 NOP; 121 NOP; 122 NOP; 123 JUMP.S label1; // 0x0224 124 R4.L = 0x1111; // Will be killed 125 R4.H = 0x1111; // Will be killed 126 NOP; 127 NOP; 128 NOP; 129 label2: R5.H = 0x7777; // 0x0234 130 R5.L = 0x7888; 131 JUMP.S label3; //0x023c 132 R6.L = 0x1111; // Will be killed 133 R6.H = 0x1111; // Will be killed 134 NOP; 135 NOP; 136 NOP; 137 NOP; 138 NOP; 139 label1: R4.H = 0x5555; // 0x0250 140 R4.L = 0x6666; 141 NOP; 142 JUMP.S label2; // 0x0258 143 R5.L = 0x1111; // Will be killed 144 R5.H = 0x1111; // Will be killed 145 NOP; 146 NOP; 147 NOP; 148 NOP; 149 label3: R6.H = 0x7999; //0x026c 150 R6.L = 0x7aaa; 151 NOP; 152 NOP; 153 NOP; 154 NOP; 155 156 WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn OFF trace Buffer 157 158 NOP; 159 NOP; 160 NOP; 161 NOP; 162 NOP; 163 // Read the contents of the Trace Buffer 164 165 RD_MMR(TBUFSTAT, p0, r2); 166 CHECKREG(r2, 0x00000003); 167 168 // Read 3rd Entry of the Trace Buffer 169 RD_MMR(TBUF, p0, r0); 170 CHECKREG(r0, 0x0000026c); 171 172 RD_MMR(TBUFSTAT, p0, r2); 173 CHECKREG(r2, 0x00000003); 174 175 RD_MMR(TBUF, p0, r1); 176 CHECKREG(r1, 0x0000023c); 177 178 RD_MMR(TBUFSTAT, p0, r2); 179 CHECKREG(r2, 0x00000002); 180 181 // Read 2nd Entry of the Trace Buffer 182 RD_MMR(TBUF, p0, r0); 183 CHECKREG(r0, 0x00000234); 184 185 RD_MMR(TBUFSTAT, p0, r2); 186 CHECKREG(r2, 0x00000002); 187 188 RD_MMR(TBUF, p0, r1); 189 CHECKREG(r1, 0x0000025a); 190 191 RD_MMR(TBUFSTAT, p0, r2); 192 CHECKREG(r2, 0x00000001); 193 194 // Read ist Entry of the Trace Buffer 195 RD_MMR(TBUF, p0, r0); 196 CHECKREG(r0, 0x00000250); 197 198 RD_MMR(TBUFSTAT, p0, r2); 199 CHECKREG(r2, 0x00000001); 200 201 RD_MMR(TBUF, p0, r1); 202 CHECKREG(r1, 0x00000224); 203 204 RD_MMR(TBUFSTAT, p0, r2); 205 CHECKREG(r2, 0x00000000); 206 207 WR_MMR(TBUFCTL, 0x00000000, p0, r0); // Turn OFF trace Buffer Power 208 209 NOP; 210 NOP; 211 NOP; 212 NOP; 213 NOP; 214 NOP; 215 dbg_pass; // Call Endtest Macro 216 217 218 219 //********************************************************************* 220 // 221 // Handlers for Events 222 // 223 224 EHANDLE: // Emulation Handler 0 225 RTE; 226 227 RHANDLE: // Reset Handler 1 228 RTI; 229 230 NHANDLE: // NMI Handler 2 231 RTN; 232 233 XHANDLE: // Exception Handler 3 234 RTX; 235 236 HWHANDLE: // HW Error Handler 5 237 RTI; 238 239 THANDLE: // Timer Handler 6 240 RTI; 241 242 I7HANDLE: // IVG 7 Handler 243 RTI; 244 245 I8HANDLE: // IVG 8 Handler 246 RTI; 247 248 I9HANDLE: // IVG 9 Handler 249 RTI; 250 251 I10HANDLE: // IVG 10 Handler 252 RTI; 253 254 I11HANDLE: // IVG 11 Handler 255 RTI; 256 257 I12HANDLE: // IVG 12 Handler 258 RTI; 259 260 I13HANDLE: // IVG 13 Handler 261 RTI; 262 263 I14HANDLE: // IVG 14 Handler 264 RTI; 265 266 I15HANDLE: // IVG 15 Handler 267 RTI; 268
Indexes created Sat Feb 28 05:31:39 UTC 2026