1 //Original:/proj/frio/dv/testcases/seq/se_cc_kill/se_cc_kill.dsp 2 // Description: 3 // Verify CC kill under the following condition: 4 // 5 // (1) CC = AZ killed in WB 6 // (2) CC = AN killed in WB 7 // (3) CC = AC killed in WB 8 // (4) CC = AV0 killed in WB 9 // (5) CC = AV1 killed in WB 10 // (6) CC = AQ killed in WB 11 # mach: bfin 12 # sim: --environment operating 13 14 #include "test.h" 15 .include "testutils.inc" 16 start 17 18 // ---------------------------------------------------------------- 19 // Include Files 20 // ---------------------------------------------------------------- 21 22 include(std.inc) 23 include(selfcheck.inc) 24 include(symtable.inc) 25 include(mmrs.inc) 26 27 // ---------------------------------------------------------------- 28 // Defines 29 // ---------------------------------------------------------------- 30 31 #ifndef STACKSIZE 32 #define STACKSIZE 0x00000010 33 #endif 34 #ifndef ITABLE 35 #define ITABLE CODE_ADDR_1 // 36 #endif 37 38 39 // ---------------------------------------------------------------- 40 // Reset ISR 41 // - set the processor operating modes 42 // - initialize registers 43 // - etc ... 44 // ---------------------------------------------------------------- 45 46 RST_ISR: 47 48 // Initialize data registers 49 //INIT_R_REGS(0); 50 R7 = 0; 51 R6 = 0; 52 R5 = 0; 53 R4 = 0; 54 R3 = 0; 55 R2 = 0; 56 R1 = 0; 57 R0 = 0; 58 59 // Initialize pointer registers 60 INIT_P_REGS(0); 61 62 // Initialize address registers 63 INIT_I_REGS(0); 64 INIT_M_REGS(0); 65 INIT_L_REGS(0); 66 INIT_B_REGS(0); 67 68 // Initialize the address of the checkreg data segment 69 // **** THIS IS NEEDED WHENEVER CHECKREG IS USED **** 70 CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC); 71 72 // Inhibit events during MMR writes 73 CLI R1; 74 75 // Setup user stack 76 LD32_LABEL(sp, USTACK); 77 USP = SP; 78 79 // Setup kernel stack 80 LD32_LABEL(sp, KSTACK); 81 82 // Setup frame pointer 83 FP = SP; 84 85 // Setup event vector table 86 LD32(p0, EVT0); 87 88 LD32_LABEL(r0, EMU_ISR); // Emulation Handler (EVT0) 89 [ P0 ++ ] = R0; 90 LD32_LABEL(r0, RST_ISR); // Reset Handler (EVT1) 91 [ P0 ++ ] = R0; 92 LD32_LABEL(r0, NMI_ISR); // NMI Handler (EVT2) 93 [ P0 ++ ] = R0; 94 LD32_LABEL(r0, EXC_ISR); // Exception Handler (EVT3) 95 [ P0 ++ ] = R0; 96 [ P0 ++ ] = R0; // EVT4 not used 97 LD32_LABEL(r0, HWE_ISR); // HW Error Handler (EVT5) 98 [ P0 ++ ] = R0; 99 LD32_LABEL(r0, TMR_ISR); // Timer Handler (EVT6) 100 [ P0 ++ ] = R0; 101 LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler 102 [ P0 ++ ] = R0; 103 LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler 104 [ P0 ++ ] = R0; 105 LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler 106 [ P0 ++ ] = R0; 107 LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler 108 [ P0 ++ ] = R0; 109 LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler 110 [ P0 ++ ] = R0; 111 LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler 112 [ P0 ++ ] = R0; 113 LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler 114 [ P0 ++ ] = R0; 115 LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler 116 [ P0 ++ ] = R0; 117 LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler 118 [ P0 ++ ] = R0; 119 120 // Set the EVT_OVERRIDE MMR 121 LD32(p0, EVT_OVERRIDE); 122 R0 = 0; 123 [ P0 ++ ] = R0; 124 125 // Disable L1 data cache 126 WR_MMR(DMEM_CONTROL, 0x00000000, p0, r0); 127 128 // Mask interrupts (*) 129 R1 = -1; 130 131 // Wait for MMR writes to finish 132 CSYNC; 133 134 // Re-enable events 135 STI R1; 136 137 // Reset loop counters to deterministic values 138 R0 = 0 (Z); 139 140 LT0 = R0; 141 LB0 = R0; 142 LC0 = R0; 143 LT1 = R0; 144 LB1 = R0; 145 LC1 = R0; 146 147 // Reset other internal regs 148 ASTAT = R0; 149 SYSCFG = R0; 150 RETS = R0; 151 152 // Setup the test to run in USER mode 153 LD32_LABEL(r0, USER_CODE); 154 RETI = R0; 155 156 // Setup the test to run in SUPERVISOR mode 157 // Comment the following line for a USER mode test 158 JUMP.S SUPERVISOR_CODE; 159 RTI; 160 161 SUPERVISOR_CODE: 162 // Load IVG15 general handler (Int15) with MAIN_CODE 163 LD32_LABEL(p1, MAIN_CODE); 164 165 LD32(p0, EVT15); 166 167 CLI R1; 168 [ P0 ] = P1; 169 CSYNC; 170 STI R1; 171 172 // Take Int15 which branch to MAIN_CODE after RTI 173 RAISE 15; 174 RTI; 175 176 USER_CODE: 177 // Setup the stack pointer and the frame pointer 178 LD32_LABEL(sp, USTACK); 179 FP = SP; 180 JUMP.S MAIN_CODE; 181 182 .dw 0xFFFF 183 .dw 0xFFFF 184 .dw 0xFFFF 185 .dw 0xFFFF 186 .dw 0xFFFF 187 .dw 0xFFFF 188 .dw 0xFFFF 189 190 // ---------------------------------------------------------------- 191 // ISR Table 192 // ---------------------------------------------------------------- 193 194 195 // ---------------------------------------------------------------- 196 // EMU ISR 197 // ---------------------------------------------------------------- 198 199 EMU_ISR : 200 201 RTE; 202 203 .dw 0xFFFF 204 .dw 0xFFFF 205 .dw 0xFFFF 206 .dw 0xFFFF 207 .dw 0xFFFF 208 .dw 0xFFFF 209 .dw 0xFFFF 210 211 // ---------------------------------------------------------------- 212 // NMI ISR 213 // ---------------------------------------------------------------- 214 215 NMI_ISR : 216 217 RTN; 218 219 .dw 0xFFFF 220 .dw 0xFFFF 221 .dw 0xFFFF 222 .dw 0xFFFF 223 .dw 0xFFFF 224 .dw 0xFFFF 225 .dw 0xFFFF 226 227 // ---------------------------------------------------------------- 228 // EXC ISR 229 // ---------------------------------------------------------------- 230 231 EXC_ISR : 232 233 RTX; 234 235 .dw 0xFFFF 236 .dw 0xFFFF 237 .dw 0xFFFF 238 .dw 0xFFFF 239 .dw 0xFFFF 240 .dw 0xFFFF 241 .dw 0xFFFF 242 243 // ---------------------------------------------------------------- 244 // HWE ISR 245 // ---------------------------------------------------------------- 246 247 HWE_ISR : 248 249 RTI; 250 251 .dw 0xFFFF 252 .dw 0xFFFF 253 .dw 0xFFFF 254 .dw 0xFFFF 255 .dw 0xFFFF 256 .dw 0xFFFF 257 .dw 0xFFFF 258 259 // ---------------------------------------------------------------- 260 // TMR ISR 261 // ---------------------------------------------------------------- 262 263 TMR_ISR : 264 265 RTI; 266 267 .dw 0xFFFF 268 .dw 0xFFFF 269 .dw 0xFFFF 270 .dw 0xFFFF 271 .dw 0xFFFF 272 .dw 0xFFFF 273 .dw 0xFFFF 274 275 // ---------------------------------------------------------------- 276 // IGV7 ISR 277 // ---------------------------------------------------------------- 278 279 IGV7_ISR : 280 281 RTI; 282 283 .dw 0xFFFF 284 .dw 0xFFFF 285 .dw 0xFFFF 286 .dw 0xFFFF 287 .dw 0xFFFF 288 .dw 0xFFFF 289 .dw 0xFFFF 290 291 // ---------------------------------------------------------------- 292 // IGV8 ISR 293 // ---------------------------------------------------------------- 294 295 IGV8_ISR : 296 297 RTI; 298 299 .dw 0xFFFF 300 .dw 0xFFFF 301 .dw 0xFFFF 302 .dw 0xFFFF 303 .dw 0xFFFF 304 .dw 0xFFFF 305 .dw 0xFFFF 306 307 // ---------------------------------------------------------------- 308 // IGV9 ISR 309 // ---------------------------------------------------------------- 310 311 IGV9_ISR : 312 313 RTI; 314 315 .dw 0xFFFF 316 .dw 0xFFFF 317 .dw 0xFFFF 318 .dw 0xFFFF 319 .dw 0xFFFF 320 .dw 0xFFFF 321 .dw 0xFFFF 322 323 // ---------------------------------------------------------------- 324 // IGV10 ISR 325 // ---------------------------------------------------------------- 326 327 IGV10_ISR : 328 329 RTI; 330 331 .dw 0xFFFF 332 .dw 0xFFFF 333 .dw 0xFFFF 334 .dw 0xFFFF 335 .dw 0xFFFF 336 .dw 0xFFFF 337 .dw 0xFFFF 338 339 // ---------------------------------------------------------------- 340 // IGV11 ISR 341 // ---------------------------------------------------------------- 342 343 IGV11_ISR : 344 345 RTI; 346 347 .dw 0xFFFF 348 .dw 0xFFFF 349 .dw 0xFFFF 350 .dw 0xFFFF 351 .dw 0xFFFF 352 .dw 0xFFFF 353 .dw 0xFFFF 354 355 // ---------------------------------------------------------------- 356 // IGV12 ISR 357 // ---------------------------------------------------------------- 358 359 IGV12_ISR : 360 361 RTI; 362 363 .dw 0xFFFF 364 .dw 0xFFFF 365 .dw 0xFFFF 366 .dw 0xFFFF 367 .dw 0xFFFF 368 .dw 0xFFFF 369 .dw 0xFFFF 370 371 // ---------------------------------------------------------------- 372 // IGV13 ISR 373 // ---------------------------------------------------------------- 374 375 IGV13_ISR : 376 377 RTI; 378 379 .dw 0xFFFF 380 .dw 0xFFFF 381 .dw 0xFFFF 382 .dw 0xFFFF 383 .dw 0xFFFF 384 .dw 0xFFFF 385 .dw 0xFFFF 386 387 // ---------------------------------------------------------------- 388 // IGV14 ISR 389 // ---------------------------------------------------------------- 390 391 IGV14_ISR : 392 393 RTI; 394 395 .dw 0xFFFF 396 .dw 0xFFFF 397 .dw 0xFFFF 398 .dw 0xFFFF 399 .dw 0xFFFF 400 .dw 0xFFFF 401 .dw 0xFFFF 402 403 // ---------------------------------------------------------------- 404 // IGV15 ISR 405 // ---------------------------------------------------------------- 406 407 IGV15_ISR : 408 409 RTI; 410 411 .dw 0xFFFF 412 .dw 0xFFFF 413 .dw 0xFFFF 414 .dw 0xFFFF 415 .dw 0xFFFF 416 .dw 0xFFFF 417 .dw 0xFFFF 418 419 // ---------------------------------------------------------------- 420 // Main Code 421 // ---------------------------------------------------------------- 422 423 424 MAIN_CODE: 425 // Enable interrupts in SUPERVISOR mode 426 // Comment the following line for a USER mode test 427 [ -- SP ] = RETI; 428 429 // Start of the program code 430 431 // Verify CC kill under the following condition: 432 433 // (1) CC = AZ killed in WB 434 CC = R2 < R3; 435 EXCPT 3; 436 CC = AZ; 437 438 // (2) CC = AN killed in WB 439 CC = R2 == R3; 440 EXCPT 3; 441 CC = AN; 442 443 // (3) CC = AC killed in WB 444 CC = R2 < R3; 445 EXCPT 3; 446 CC = AC0; 447 448 // (4) CC = AV0 killed in WB 449 CC = R2 == R3; 450 EXCPT 3; 451 CC = AV0; 452 453 // (5) CC = AV1 killed in WB 454 CC = R2 == R3; 455 EXCPT 3; 456 CC = AV1; 457 458 // (6) CC = AQ killed in WB 459 CC = R2 == R3; 460 EXCPT 3; 461 CC = AQ; 462 463 464 END: 465 dbg_pass; 466 467 // ---------------------------------------------------------------- 468 // Data Segment 469 // - define kernel and user stacks 470 // ---------------------------------------------------------------- 471 472 .data 473 DATA: 474 .space (STACKSIZE); 475 476 .space (STACKSIZE); 477 KSTACK: 478 479 .space (STACKSIZE); 480 USTACK: 481
Indexes created Mon Mar 02 05:31:46 UTC 2026