1 //Original:/proj/frio/dv/testcases/seq/se_excpt_ssstep/se_excpt_ssstep.dsp 2 // Description: EXCPT instruction vs Single Step Exception Priority 3 # mach: bfin 4 # sim: --environment operating 5 6 #include "test.h" 7 .include "testutils.inc" 8 start 9 10 // 11 // Constants and Defines 12 // 13 14 include(gen_int.inc) 15 include(selfcheck.inc) 16 include(std.inc) 17 //include(mmrs.inc) 18 include(symtable.inc) 19 20 #ifndef STACKSIZE 21 #define STACKSIZE 0x10 22 #endif 23 #ifndef EVT 24 #define EVT 0xFFE02000 25 #endif 26 #ifndef EVT15 27 #define EVT15 0xFFE0203C 28 #endif 29 #ifndef EVT_OVERRIDE 30 #define EVT_OVERRIDE 0xFFE02100 31 #endif 32 #ifndef ITABLE 33 #define ITABLE 0xF0000000 34 #endif 35 36 GEN_INT_INIT(ITABLE) // set location for interrupt table 37 38 // 39 // Reset/Bootstrap Code 40 // (Here we should set the processor operating modes, initialize registers, 41 // etc.) 42 // 43 44 BOOT: 45 INIT_R_REGS(0); // initialize general purpose regs 46 47 INIT_P_REGS(0); // initialize the pointers 48 49 INIT_I_REGS(0); // initialize the dsp address regs 50 INIT_M_REGS(0); 51 INIT_L_REGS(0); 52 INIT_B_REGS(0); 53 54 LD32_LABEL(sp, KSTACK); // setup the stack pointer 55 FP = SP; // and frame pointer 56 57 LD32(p0, EVT); // Setup Event Vectors and Handlers 58 59 LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) 60 [ P0 ++ ] = R0; 61 62 LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) 63 [ P0 ++ ] = R0; 64 65 LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) 66 [ P0 ++ ] = R0; 67 68 LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) 69 [ P0 ++ ] = R0; 70 71 [ P0 ++ ] = R0; // IVT4 not used 72 73 LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) 74 [ P0 ++ ] = R0; 75 76 LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) 77 [ P0 ++ ] = R0; 78 79 LD32_LABEL(r0, I7HANDLE); // IVG7 Handler 80 [ P0 ++ ] = R0; 81 82 LD32_LABEL(r0, I8HANDLE); // IVG8 Handler 83 [ P0 ++ ] = R0; 84 85 LD32_LABEL(r0, I9HANDLE); // IVG9 Handler 86 [ P0 ++ ] = R0; 87 88 LD32_LABEL(r0, I10HANDLE);// IVG10 Handler 89 [ P0 ++ ] = R0; 90 91 LD32_LABEL(r0, I11HANDLE);// IVG11 Handler 92 [ P0 ++ ] = R0; 93 94 LD32_LABEL(r0, I12HANDLE);// IVG12 Handler 95 [ P0 ++ ] = R0; 96 97 LD32_LABEL(r0, I13HANDLE);// IVG13 Handler 98 [ P0 ++ ] = R0; 99 100 LD32_LABEL(r0, I14HANDLE);// IVG14 Handler 101 [ P0 ++ ] = R0; 102 103 LD32_LABEL(r0, I15HANDLE);// IVG15 Handler 104 [ P0 ++ ] = R0; 105 106 LD32(p0, EVT_OVERRIDE); 107 R0 = 0; 108 [ P0 ++ ] = R0; 109 R0 = -1; // Change this to mask interrupts (*) 110 [ P0 ] = R0; // IMASK 111 112 DUMMY: 113 114 R0 = 0 (Z); 115 116 LT0 = r0; // set loop counters to something deterministic 117 LB0 = r0; 118 LC0 = r0; 119 LT1 = r0; 120 LB1 = r0; 121 LC1 = r0; 122 123 ASTAT = r0; // reset other internal regs 124 125 // The following code sets up the test for running in USER mode 126 127 LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a 128 // ReturnFromInterrupt (RTI) 129 RETI = r0; // We need to load the return address 130 131 R0 = 1; 132 133 SYSCFG = r0; // Enable Supervisor Single Step 134 135 CHECK_INIT_DEF(p2); //CHECK_INIT(p2, 0x2000); 136 137 138 // Comment the following line for a USER Mode test 139 140 // JUMP STARTSUP; // jump to code start for SUPERVISOR mode 141 142 RTI; 143 144 STARTSUP: 145 LD32_LABEL(p1, BEGIN); 146 147 LD32(p0, EVT15); 148 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start 149 150 RAISE 15; // after we RTI, INT 15 should be taken 151 152 NOP; // Workaround for Bug 217 153 RTI; 154 155 // 156 // The Main Program 157 // 158 159 STARTUSER: 160 LD32_LABEL(sp, USTACK); // setup the stack pointer 161 FP = SP; // set frame pointer 162 JUMP BEGIN; 163 164 //********************************************************************* 165 166 BEGIN: 167 168 // COMMENT the following line for USER MODE tests 169 // [--sp] = RETI; // enable interrupts in supervisor mode 170 171 // **** YOUR CODE GOES HERE **** 172 R0 = 0; 173 R0 = 0; 174 R0 = 0; 175 R0 = 0; 176 R0 = 0; 177 EXCPT 15; // single step shouldn't happen for this. 178 R0 = 0; 179 R0 = 0; 180 R0 = 0; 181 R0 = 0; 182 R0 = 0; 183 184 EXCPT 3; // turn off single step via handler 185 186 CHECKREG(r4, 1); // one EXCPT 15 instruction 187 CHECKREG(r5, 14); // 14 instructions are executed before we disable single step 188 189 190 // PUT YOUR TEST HERE! 191 192 193 END: 194 dbg_pass; // End the test 195 196 //********************************************************************* 197 198 // 199 // Handlers for Events 200 // 201 202 EHANDLE: // Emulation Handler 0 203 RTE; 204 205 RHANDLE: // Reset Handler 1 206 RTI; 207 208 NHANDLE: // NMI Handler 2 209 RTN; 210 211 XHANDLE: // Exception Handler 3 212 [ -- SP ] = ASTAT; // save what we damage 213 [ -- SP ] = ( R7:6 ); 214 R7 = SEQSTAT; 215 R7 <<= 26; 216 R7 >>= 26; // only want EXCAUSE 217 R6 = 0x10; // EXCAUSE 0x10 means Single Step 218 CC = r7 == r6; 219 IF CC JUMP SINGLESTEP (BP); // Go to Single Step Handler 220 221 R6 = 15; // EXCAUSE 15 means EXCPT 15 instruction 222 CC = r7 == r6; 223 IF CC JUMP EXCPT15 (BP); 224 225 SYSCFG = r0; // otherwise must be an EXCPT, so turn off singlestep 226 227 JUMP.S OUT; 228 229 EXCPT15: 230 R4 += 1; // R4 counts EXCPT 15s 231 JUMP.S OUT; 232 233 SINGLESTEP: 234 R5 += 1; // R5 counts single step events 235 236 OUT: 237 ( R7:6 ) = [ SP ++ ]; 238 ASTAT = [sp++]; 239 RTX; 240 241 HWHANDLE: // HW Error Handler 5 242 RTI; 243 244 THANDLE: // Timer Handler 6 245 RTI; 246 247 I7HANDLE: // IVG 7 Handler 248 RTI; 249 250 I8HANDLE: // IVG 8 Handler 251 RTI; 252 253 I9HANDLE: // IVG 9 Handler 254 RTI; 255 256 I10HANDLE: // IVG 10 Handler 257 RTI; 258 259 I11HANDLE: // IVG 11 Handler 260 RTI; 261 262 I12HANDLE: // IVG 12 Handler 263 RTI; 264 265 I13HANDLE: // IVG 13 Handler 266 RTI; 267 268 I14HANDLE: // IVG 14 Handler 269 RTI; 270 271 I15HANDLE: // IVG 15 Handler 272 RTI; 273 274 NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug 275 276 // 277 // Data Segment 278 // 279 280 .data 281 DATA: 282 .space (0x10); 283 284 // Stack Segments (Both Kernel and User) 285 286 .space (STACKSIZE); 287 KSTACK: 288 289 .space (STACKSIZE); 290 USTACK: 291
Indexes created Sat Feb 28 05:31:39 UTC 2026