1 # frv testcase for mqaddhss $FRi,$FRj,$FRj 2 # mach: frv fr500 3 4 .include "../testutils.inc" 5 6 start 7 8 .global mqaddhss 9 mqaddhss: 10 set_fr_iimmed 0x0000,0x0000,fr10 11 set_fr_iimmed 0xdead,0x0000,fr11 12 set_fr_iimmed 0x0000,0x0000,fr12 13 set_fr_iimmed 0x0000,0xbeef,fr13 14 mqaddhss fr10,fr12,fr14 15 test_fr_limmed 0x0000,0x0000,fr14 16 test_fr_limmed 0xdead,0xbeef,fr15 17 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 18 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 19 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 20 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 21 22 set_fr_iimmed 0x0000,0xdead,fr10 23 set_fr_iimmed 0x1234,0x5678,fr11 24 set_fr_iimmed 0xbeef,0x0000,fr12 25 set_fr_iimmed 0x1111,0x1111,fr13 26 mqaddhss fr10,fr12,fr14 27 test_fr_limmed 0xbeef,0xdead,fr14 28 test_fr_limmed 0x2345,0x6789,fr15 29 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 30 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 31 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 32 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 33 34 set_spr_immed 0,msr0 35 set_fr_iimmed 0x1234,0x5678,fr10 36 set_fr_iimmed 0x7ffe,0x7ffe,fr11 37 set_fr_iimmed 0xffff,0xffff,fr12 38 set_fr_iimmed 0x0002,0x0001,fr13 39 mqaddhss fr10,fr12,fr14 40 test_fr_limmed 0x1233,0x5677,fr14 41 test_fr_limmed 0x7fff,0x7fff,fr15 42 test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set 43 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 44 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 45 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 46 47 set_spr_immed 0,msr0 48 set_fr_iimmed 0x8001,0x8001,fr10 49 set_fr_iimmed 0x8001,0x8001,fr11 50 set_fr_iimmed 0xffff,0xfffe,fr12 51 set_fr_iimmed 0xfffe,0xfffe,fr13 52 mqaddhss fr10,fr12,fr14 53 test_fr_limmed 0x8000,0x8000,fr14 54 test_fr_limmed 0x8000,0x8000,fr15 55 test_spr_bits 0x3c,2,0x7,msr0 ; msr0.sie is set 56 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 57 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 58 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 59 60 set_spr_immed 0,msr0 61 set_spr_immed 0,msr1 62 set_fr_iimmed 0x0001,0x0001,fr10 63 set_fr_iimmed 0xffff,0xffff,fr11 64 set_fr_iimmed 0x7fff,0x0000,fr12 65 set_fr_iimmed 0x0000,0x8000,fr13 66 mqaddhss.p fr10,fr10,fr14 67 mqaddhss fr12,fr12,fr16 68 test_fr_limmed 0x0002,0x0002,fr14 69 test_fr_limmed 0xfffe,0xfffe,fr15 70 test_fr_limmed 0x7fff,0x0000,fr16 71 test_fr_limmed 0x0000,0x8000,fr17 72 test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie not set 73 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 74 test_spr_bits 0x3c,2,0x9,msr1 ; msr1.sie is set 75 test_spr_bits 2,1,1,msr1 ; msr1.ovf set 76 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 77 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 78 79 pass 80
Indexes created Sun Jun 28 00:24:58 UTC 2026