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      1 # frv testcase for msubhus $FRi,$FRj,$FRj
      2 # mach: frv fr500
      3 
      4 	.include "../testutils.inc"
      5 
      6 	start
      7 
      8 	.global msubhus
      9 msubhus:
     10 	set_fr_iimmed	0x0000,0x0000,fr10
     11 	set_fr_iimmed	0xdead,0xbeef,fr11
     12 	set_fr_iimmed	0x0000,0x0000,fr12
     13 	set_fr_iimmed	0x0000,0x0000,fr13
     14 	mqsubhus	fr10,fr12,fr14
     15 	test_fr_limmed	0x0000,0x0000,fr14
     16 	test_fr_limmed	0xdead,0xbeef,fr15
     17 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
     18 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
     19 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
     20 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
     21 
     22 	set_fr_iimmed	0x1234,0x5678,fr10
     23 	set_fr_iimmed	0x7ffe,0x7ffe,fr11
     24 	set_fr_iimmed	0x1111,0x1111,fr12
     25 	set_fr_iimmed	0x0002,0x0001,fr13
     26 	mqsubhus	fr10,fr12,fr14
     27 	test_fr_limmed	0x0123,0x4567,fr14
     28 	test_fr_limmed	0x7ffc,0x7ffd,fr15
     29 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
     30 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
     31 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
     32 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
     33 
     34 	set_spr_immed	0,msr0
     35 	set_fr_iimmed	0x0001,0x0001,fr10
     36 	set_fr_iimmed	0x0001,0x0001,fr11
     37 	set_fr_iimmed	0x0001,0x0002,fr12
     38 	set_fr_iimmed	0x0002,0x0001,fr13
     39 	mqsubhus	fr10,fr12,fr14
     40 	test_fr_limmed	0x0000,0x0000,fr14
     41 	test_fr_limmed	0x0000,0x0000,fr15
     42 	test_spr_bits	0x3c,2,0x6,msr0		; msr0.sie is set
     43 	test_spr_bits	2,1,1,msr0		; msr0.ovf set
     44 	test_spr_bits	1,0,1,msr0		; msr0.aovf set
     45 	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
     46 
     47 	set_spr_immed	0,msr0
     48 	set_spr_immed	0,msr1
     49 	set_fr_iimmed	0x0001,0x0001,fr10
     50 	set_fr_iimmed	0x0002,0x0002,fr11
     51 	set_fr_iimmed	0x0000,0x0001,fr12
     52 	set_fr_iimmed	0x0002,0x0003,fr13
     53 	mqsubhus.p	fr10,fr10,fr14
     54 	mqsubhus	fr10,fr12,fr16
     55 	test_fr_limmed	0x0000,0x0000,fr14
     56 	test_fr_limmed	0x0000,0x0000,fr15
     57 	test_fr_limmed	0x0001,0x0000,fr16
     58 	test_fr_limmed	0x0000,0x0000,fr17
     59 	test_spr_bits	0x3c,2,0x0,msr0		; msr0.sie is clear
     60 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
     61 	test_spr_bits	0x3c,2,0x1,msr1		; msr1.sie is set
     62 	test_spr_bits	2,1,1,msr1		; msr1.ovf set
     63 	test_spr_bits	1,0,1,msr0		; msr0.aovf set
     64 	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
     65 
     66 	pass
     67