1 # frv testcase for cmqmachu $GRi,$GRj,$GRk,$CCi,$cond 2 # mach: all 3 4 .include "../testutils.inc" 5 6 start 7 8 .global cmqmachu 9 cmqmachu: 10 set_spr_immed 0x1b1b,cccr 11 12 set_spr_immed 0,msr0 13 set_accg_immed 0,accg0 14 set_acc_immed 0,acc0 15 set_accg_immed 0,accg1 16 set_acc_immed 0,acc1 17 set_accg_immed 0,accg2 18 set_acc_immed 0,acc2 19 set_accg_immed 0,accg3 20 set_acc_immed 0,acc3 21 set_fr_iimmed 3,2,fr8 ; multiply small numbers 22 set_fr_iimmed 2,3,fr10 23 set_fr_iimmed 1,2,fr9 ; multiply by 1 24 set_fr_iimmed 2,1,fr11 25 cmqmachu fr8,fr10,acc0,cc0,1 26 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 27 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 28 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 29 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 30 test_accg_immed 0,accg0 31 test_acc_immed 6,acc0 32 test_accg_immed 0,accg1 33 test_acc_immed 6,acc1 34 test_accg_immed 0,accg2 35 test_acc_immed 2,acc2 36 test_accg_immed 0,accg3 37 test_acc_immed 2,acc3 38 39 set_fr_iimmed 0,2,fr8 ; multiply by 0 40 set_fr_iimmed 2,0,fr10 41 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result 42 set_fr_iimmed 2,0x3fff,fr11 43 cmqmachu fr8,fr10,acc0,cc0,1 44 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 45 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 46 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 47 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 48 test_accg_immed 0,accg0 49 test_acc_immed 6,acc0 50 test_accg_immed 0,accg1 51 test_acc_immed 6,acc1 52 test_accg_immed 0,accg2 53 test_acc_limmed 0x0000,0x8000,acc2 54 test_accg_immed 0,accg3 55 test_acc_limmed 0x0000,0x8000,acc3 56 57 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result 58 set_fr_iimmed 2,0x4000,fr10 59 set_fr_iimmed 0x8000,2,fr9 ; 17 bit result 60 set_fr_iimmed 2,0x8000,fr11 61 cmqmachu fr8,fr10,acc0,cc0,1 62 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 63 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 64 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 65 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 66 test_accg_immed 0,accg0 67 test_acc_limmed 0x0000,0x8006,acc0 68 test_accg_immed 0,accg1 69 test_acc_limmed 0x0000,0x8006,acc1 70 test_accg_immed 0,accg2 71 test_acc_immed 0x00018000,acc2 72 test_accg_immed 0,accg3 73 test_acc_immed 0x00018000,acc3 74 75 set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result 76 set_fr_iimmed 0x7fff,0x7fff,fr10 77 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result 78 set_fr_iimmed 0x8000,0x8000,fr11 79 cmqmachu fr8,fr10,acc0,cc4,1 80 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 81 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 82 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 83 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 84 test_accg_immed 0,accg0 85 test_acc_immed 0x3fff8007,acc0 86 test_accg_immed 0,accg1 87 test_acc_immed 0x3fff8007,acc1 88 test_accg_immed 0,accg2 89 test_acc_limmed 0x4001,0x8000,acc2 90 test_accg_immed 0,accg3 91 test_acc_limmed 0x4001,0x8000,acc3 92 93 set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result 94 set_fr_iimmed 0xffff,0xffff,fr10 95 set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result 96 set_fr_iimmed 0xffff,0xffff,fr11 97 cmqmachu fr8,fr10,acc0,cc4,1 98 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 99 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 100 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 101 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 102 test_accg_immed 1,accg0 103 test_acc_limmed 0x3ffd,0x8008,acc0 104 test_accg_immed 1,accg1 105 test_acc_limmed 0x3ffd,0x8008,acc1 106 test_accg_immed 1,accg2 107 test_acc_limmed 0x3fff,0x8001,acc2 108 test_accg_immed 1,accg3 109 test_acc_limmed 0x3fff,0x8001,acc3 110 111 set_accg_immed 0xff,accg0 ; saturation 112 set_acc_immed 0xffffffff,acc0 113 set_accg_immed 0xff,accg1 114 set_acc_immed 0xffffffff,acc1 115 set_accg_immed 0xff,accg2 ; saturation 116 set_acc_immed 0xffffffff,acc2 117 set_accg_immed 0xff,accg3 118 set_acc_immed 0xffffffff,acc3 119 set_fr_iimmed 1,1,fr8 120 set_fr_iimmed 1,1,fr10 121 set_fr_iimmed 1,1,fr9 122 set_fr_iimmed 1,1,fr11 123 cmqmachu fr8,fr10,acc0,cc4,1 124 test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set 125 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 126 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 127 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 128 test_accg_immed 0xff,accg0 129 test_acc_limmed 0xffff,0xffff,acc0 130 test_accg_immed 0xff,accg1 131 test_acc_limmed 0xffff,0xffff,acc1 132 test_accg_immed 0xff,accg2 133 test_acc_limmed 0xffff,0xffff,acc2 134 test_accg_immed 0xff,accg3 135 test_acc_limmed 0xffff,0xffff,acc3 136 137 set_fr_iimmed 0xffff,0x0000,fr8 138 set_fr_iimmed 0xffff,0xffff,fr10 139 set_fr_iimmed 0x0000,0xffff,fr9 140 set_fr_iimmed 0xffff,0xffff,fr11 141 cmqmachu fr8,fr10,acc0,cc4,1 142 test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set 143 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 144 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 145 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 146 test_accg_immed 0xff,accg0 147 test_acc_limmed 0xffff,0xffff,acc0 148 test_accg_immed 0xff,accg1 149 test_acc_limmed 0xffff,0xffff,acc1 150 test_accg_immed 0xff,accg2 151 test_acc_limmed 0xffff,0xffff,acc2 152 test_accg_immed 0xff,accg3 153 test_acc_limmed 0xffff,0xffff,acc3 154 155 set_spr_immed 0,msr0 156 set_accg_immed 0,accg0 157 set_acc_immed 0,acc0 158 set_accg_immed 0,accg1 159 set_acc_immed 0,acc1 160 set_accg_immed 0,accg2 161 set_acc_immed 0,acc2 162 set_accg_immed 0,accg3 163 set_acc_immed 0,acc3 164 set_fr_iimmed 3,2,fr8 ; multiply small numbers 165 set_fr_iimmed 2,3,fr10 166 set_fr_iimmed 1,2,fr9 ; multiply by 1 167 set_fr_iimmed 2,1,fr11 168 cmqmachu fr8,fr10,acc0,cc1,0 169 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 170 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 171 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 172 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 173 test_accg_immed 0,accg0 174 test_acc_immed 6,acc0 175 test_accg_immed 0,accg1 176 test_acc_immed 6,acc1 177 test_accg_immed 0,accg2 178 test_acc_immed 2,acc2 179 test_accg_immed 0,accg3 180 test_acc_immed 2,acc3 181 182 set_fr_iimmed 0,2,fr8 ; multiply by 0 183 set_fr_iimmed 2,0,fr10 184 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result 185 set_fr_iimmed 2,0x3fff,fr11 186 cmqmachu fr8,fr10,acc0,cc1,0 187 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 188 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 189 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 190 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 191 test_accg_immed 0,accg0 192 test_acc_immed 6,acc0 193 test_accg_immed 0,accg1 194 test_acc_immed 6,acc1 195 test_accg_immed 0,accg2 196 test_acc_limmed 0x0000,0x8000,acc2 197 test_accg_immed 0,accg3 198 test_acc_limmed 0x0000,0x8000,acc3 199 200 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result 201 set_fr_iimmed 2,0x4000,fr10 202 set_fr_iimmed 0x8000,2,fr9 ; 17 bit result 203 set_fr_iimmed 2,0x8000,fr11 204 cmqmachu fr8,fr10,acc0,cc1,0 205 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 206 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 207 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 208 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 209 test_accg_immed 0,accg0 210 test_acc_limmed 0x0000,0x8006,acc0 211 test_accg_immed 0,accg1 212 test_acc_limmed 0x0000,0x8006,acc1 213 test_accg_immed 0,accg2 214 test_acc_immed 0x00018000,acc2 215 test_accg_immed 0,accg3 216 test_acc_immed 0x00018000,acc3 217 218 set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result 219 set_fr_iimmed 0x7fff,0x7fff,fr10 220 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result 221 set_fr_iimmed 0x8000,0x8000,fr11 222 cmqmachu fr8,fr10,acc0,cc5,0 223 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 224 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 225 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 226 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 227 test_accg_immed 0,accg0 228 test_acc_immed 0x3fff8007,acc0 229 test_accg_immed 0,accg1 230 test_acc_immed 0x3fff8007,acc1 231 test_accg_immed 0,accg2 232 test_acc_limmed 0x4001,0x8000,acc2 233 test_accg_immed 0,accg3 234 test_acc_limmed 0x4001,0x8000,acc3 235 236 set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result 237 set_fr_iimmed 0xffff,0xffff,fr10 238 set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result 239 set_fr_iimmed 0xffff,0xffff,fr11 240 cmqmachu fr8,fr10,acc0,cc5,0 241 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 242 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 243 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 244 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 245 test_accg_immed 1,accg0 246 test_acc_limmed 0x3ffd,0x8008,acc0 247 test_accg_immed 1,accg1 248 test_acc_limmed 0x3ffd,0x8008,acc1 249 test_accg_immed 1,accg2 250 test_acc_limmed 0x3fff,0x8001,acc2 251 test_accg_immed 1,accg3 252 test_acc_limmed 0x3fff,0x8001,acc3 253 254 set_accg_immed 0xff,accg0 ; saturation 255 set_acc_immed 0xffffffff,acc0 256 set_accg_immed 0xff,accg1 257 set_acc_immed 0xffffffff,acc1 258 set_accg_immed 0xff,accg2 ; saturation 259 set_acc_immed 0xffffffff,acc2 260 set_accg_immed 0xff,accg3 261 set_acc_immed 0xffffffff,acc3 262 set_fr_iimmed 1,1,fr8 263 set_fr_iimmed 1,1,fr10 264 set_fr_iimmed 1,1,fr9 265 set_fr_iimmed 1,1,fr11 266 cmqmachu fr8,fr10,acc0,cc5,0 267 test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set 268 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 269 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 270 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 271 test_accg_immed 0xff,accg0 272 test_acc_limmed 0xffff,0xffff,acc0 273 test_accg_immed 0xff,accg1 274 test_acc_limmed 0xffff,0xffff,acc1 275 test_accg_immed 0xff,accg2 276 test_acc_limmed 0xffff,0xffff,acc2 277 test_accg_immed 0xff,accg3 278 test_acc_limmed 0xffff,0xffff,acc3 279 280 set_fr_iimmed 0xffff,0x0000,fr8 281 set_fr_iimmed 0xffff,0xffff,fr10 282 set_fr_iimmed 0x0000,0xffff,fr9 283 set_fr_iimmed 0xffff,0xffff,fr11 284 cmqmachu fr8,fr10,acc0,cc5,0 285 test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set 286 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 287 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 288 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 289 test_accg_immed 0xff,accg0 290 test_acc_limmed 0xffff,0xffff,acc0 291 test_accg_immed 0xff,accg1 292 test_acc_limmed 0xffff,0xffff,acc1 293 test_accg_immed 0xff,accg2 294 test_acc_limmed 0xffff,0xffff,acc2 295 test_accg_immed 0xff,accg3 296 test_acc_limmed 0xffff,0xffff,acc3 297 298 set_spr_immed 0,msr0 299 set_accg_immed 0x00000011,accg0 300 set_acc_immed 0x11111111,acc0 301 set_accg_immed 0x00000022,accg1 302 set_acc_immed 0x22222222,acc1 303 set_accg_immed 0x00000033,accg2 304 set_acc_immed 0x33333333,acc2 305 set_accg_immed 0x00000044,accg3 306 set_acc_immed 0x44444444,acc3 307 set_fr_iimmed 3,2,fr8 ; multiply small numbers 308 set_fr_iimmed 2,3,fr10 309 set_fr_iimmed 1,2,fr9 ; multiply by 1 310 set_fr_iimmed 2,1,fr11 311 cmqmachu fr8,fr10,acc0,cc0,0 312 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 313 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 314 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 315 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 316 test_accg_immed 0x00000011,accg0 317 test_acc_immed 0x11111111,acc0 318 test_accg_immed 0x00000022,accg1 319 test_acc_immed 0x22222222,acc1 320 test_accg_immed 0x00000033,accg2 321 test_acc_immed 0x33333333,acc2 322 test_accg_immed 0x00000044,accg3 323 test_acc_immed 0x44444444,acc3 324 325 set_fr_iimmed 0,2,fr8 ; multiply by 0 326 set_fr_iimmed 2,0,fr10 327 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result 328 set_fr_iimmed 2,0x3fff,fr11 329 cmqmachu fr8,fr10,acc0,cc0,0 330 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 331 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 332 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 333 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 334 test_accg_immed 0x00000011,accg0 335 test_acc_immed 0x11111111,acc0 336 test_accg_immed 0x00000022,accg1 337 test_acc_immed 0x22222222,acc1 338 test_accg_immed 0x00000033,accg2 339 test_acc_immed 0x33333333,acc2 340 test_accg_immed 0x00000044,accg3 341 test_acc_immed 0x44444444,acc3 342 343 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result 344 set_fr_iimmed 2,0x4000,fr10 345 set_fr_iimmed 0x8000,2,fr9 ; 17 bit result 346 set_fr_iimmed 2,0x8000,fr11 347 cmqmachu fr8,fr10,acc0,cc0,0 348 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 349 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 350 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 351 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 352 test_accg_immed 0x00000011,accg0 353 test_acc_immed 0x11111111,acc0 354 test_accg_immed 0x00000022,accg1 355 test_acc_immed 0x22222222,acc1 356 test_accg_immed 0x00000033,accg2 357 test_acc_immed 0x33333333,acc2 358 test_accg_immed 0x00000044,accg3 359 test_acc_immed 0x44444444,acc3 360 361 set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result 362 set_fr_iimmed 0x7fff,0x7fff,fr10 363 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result 364 set_fr_iimmed 0x8000,0x8000,fr11 365 cmqmachu fr8,fr10,acc0,cc4,0 366 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 367 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 368 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 369 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 370 test_accg_immed 0x00000011,accg0 371 test_acc_immed 0x11111111,acc0 372 test_accg_immed 0x00000022,accg1 373 test_acc_immed 0x22222222,acc1 374 test_accg_immed 0x00000033,accg2 375 test_acc_immed 0x33333333,acc2 376 test_accg_immed 0x00000044,accg3 377 test_acc_immed 0x44444444,acc3 378 379 set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result 380 set_fr_iimmed 0xffff,0xffff,fr10 381 set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result 382 set_fr_iimmed 0xffff,0xffff,fr11 383 cmqmachu fr8,fr10,acc0,cc4,0 384 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 385 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 386 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 387 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 388 test_accg_immed 0x00000011,accg0 389 test_acc_immed 0x11111111,acc0 390 test_accg_immed 0x00000022,accg1 391 test_acc_immed 0x22222222,acc1 392 test_accg_immed 0x00000033,accg2 393 test_acc_immed 0x33333333,acc2 394 test_accg_immed 0x00000044,accg3 395 test_acc_immed 0x44444444,acc3 396 397 set_accg_immed 0xff,accg0 ; saturation 398 set_acc_immed 0xffffffff,acc0 399 set_accg_immed 0xff,accg1 400 set_acc_immed 0xffffffff,acc1 401 set_accg_immed 0xff,accg2 ; saturation 402 set_acc_immed 0xffffffff,acc2 403 set_accg_immed 0xff,accg3 404 set_acc_immed 0xffffffff,acc3 405 set_fr_iimmed 1,1,fr8 406 set_fr_iimmed 1,1,fr10 407 set_fr_iimmed 1,1,fr9 408 set_fr_iimmed 1,1,fr11 409 cmqmachu fr8,fr10,acc0,cc4,0 410 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 411 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 412 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 413 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 414 test_accg_immed 0xff,accg0 ; saturation 415 test_acc_immed 0xffffffff,acc0 416 test_accg_immed 0xff,accg1 417 test_acc_immed 0xffffffff,acc1 418 test_accg_immed 0xff,accg2 ; saturation 419 test_acc_immed 0xffffffff,acc2 420 test_accg_immed 0xff,accg3 421 test_acc_immed 0xffffffff,acc3 422 423 set_fr_iimmed 0xffff,0x0000,fr8 424 set_fr_iimmed 0xffff,0xffff,fr10 425 set_fr_iimmed 0x0000,0xffff,fr9 426 set_fr_iimmed 0xffff,0xffff,fr11 427 cmqmachu fr8,fr10,acc0,cc4,0 428 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 429 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 430 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 431 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 432 test_accg_immed 0xff,accg0 ; saturation 433 test_acc_immed 0xffffffff,acc0 434 test_accg_immed 0xff,accg1 435 test_acc_immed 0xffffffff,acc1 436 test_accg_immed 0xff,accg2 ; saturation 437 test_acc_immed 0xffffffff,acc2 438 test_accg_immed 0xff,accg3 439 test_acc_immed 0xffffffff,acc3 440 441 set_spr_immed 0,msr0 442 set_accg_immed 0x00000011,accg0 443 set_acc_immed 0x11111111,acc0 444 set_accg_immed 0x00000022,accg1 445 set_acc_immed 0x22222222,acc1 446 set_accg_immed 0x00000033,accg2 447 set_acc_immed 0x33333333,acc2 448 set_accg_immed 0x00000044,accg3 449 set_acc_immed 0x44444444,acc3 450 set_fr_iimmed 3,2,fr8 ; multiply small numbers 451 set_fr_iimmed 2,3,fr10 452 set_fr_iimmed 1,2,fr9 ; multiply by 1 453 set_fr_iimmed 2,1,fr11 454 cmqmachu fr8,fr10,acc0,cc1,1 455 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 456 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 457 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 458 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 459 test_accg_immed 0x00000011,accg0 460 test_acc_immed 0x11111111,acc0 461 test_accg_immed 0x00000022,accg1 462 test_acc_immed 0x22222222,acc1 463 test_accg_immed 0x00000033,accg2 464 test_acc_immed 0x33333333,acc2 465 test_accg_immed 0x00000044,accg3 466 test_acc_immed 0x44444444,acc3 467 468 set_fr_iimmed 0,2,fr8 ; multiply by 0 469 set_fr_iimmed 2,0,fr10 470 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result 471 set_fr_iimmed 2,0x3fff,fr11 472 cmqmachu fr8,fr10,acc0,cc1,1 473 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 474 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 475 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 476 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 477 test_accg_immed 0x00000011,accg0 478 test_acc_immed 0x11111111,acc0 479 test_accg_immed 0x00000022,accg1 480 test_acc_immed 0x22222222,acc1 481 test_accg_immed 0x00000033,accg2 482 test_acc_immed 0x33333333,acc2 483 test_accg_immed 0x00000044,accg3 484 test_acc_immed 0x44444444,acc3 485 486 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result 487 set_fr_iimmed 2,0x4000,fr10 488 set_fr_iimmed 0x8000,2,fr9 ; 17 bit result 489 set_fr_iimmed 2,0x8000,fr11 490 cmqmachu fr8,fr10,acc0,cc1,1 491 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 492 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 493 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 494 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 495 test_accg_immed 0x00000011,accg0 496 test_acc_immed 0x11111111,acc0 497 test_accg_immed 0x00000022,accg1 498 test_acc_immed 0x22222222,acc1 499 test_accg_immed 0x00000033,accg2 500 test_acc_immed 0x33333333,acc2 501 test_accg_immed 0x00000044,accg3 502 test_acc_immed 0x44444444,acc3 503 504 set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result 505 set_fr_iimmed 0x7fff,0x7fff,fr10 506 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result 507 set_fr_iimmed 0x8000,0x8000,fr11 508 cmqmachu fr8,fr10,acc0,cc5,1 509 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 510 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 511 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 512 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 513 test_accg_immed 0x00000011,accg0 514 test_acc_immed 0x11111111,acc0 515 test_accg_immed 0x00000022,accg1 516 test_acc_immed 0x22222222,acc1 517 test_accg_immed 0x00000033,accg2 518 test_acc_immed 0x33333333,acc2 519 test_accg_immed 0x00000044,accg3 520 test_acc_immed 0x44444444,acc3 521 522 set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result 523 set_fr_iimmed 0xffff,0xffff,fr10 524 set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result 525 set_fr_iimmed 0xffff,0xffff,fr11 526 cmqmachu fr8,fr10,acc0,cc5,1 527 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 528 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 529 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 530 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 531 test_accg_immed 0x00000011,accg0 532 test_acc_immed 0x11111111,acc0 533 test_accg_immed 0x00000022,accg1 534 test_acc_immed 0x22222222,acc1 535 test_accg_immed 0x00000033,accg2 536 test_acc_immed 0x33333333,acc2 537 test_accg_immed 0x00000044,accg3 538 test_acc_immed 0x44444444,acc3 539 540 set_accg_immed 0xff,accg0 ; saturation 541 set_acc_immed 0xffffffff,acc0 542 set_accg_immed 0xff,accg1 543 set_acc_immed 0xffffffff,acc1 544 set_accg_immed 0xff,accg2 ; saturation 545 set_acc_immed 0xffffffff,acc2 546 set_accg_immed 0xff,accg3 547 set_acc_immed 0xffffffff,acc3 548 set_fr_iimmed 1,1,fr8 549 set_fr_iimmed 1,1,fr10 550 set_fr_iimmed 1,1,fr9 551 set_fr_iimmed 1,1,fr11 552 cmqmachu fr8,fr10,acc0,cc5,1 553 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 554 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 555 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 556 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 557 test_accg_immed 0xff,accg0 ; saturation 558 test_acc_immed 0xffffffff,acc0 559 test_accg_immed 0xff,accg1 560 test_acc_immed 0xffffffff,acc1 561 test_accg_immed 0xff,accg2 ; saturation 562 test_acc_immed 0xffffffff,acc2 563 test_accg_immed 0xff,accg3 564 test_acc_immed 0xffffffff,acc3 565 566 set_fr_iimmed 0xffff,0x0000,fr8 567 set_fr_iimmed 0xffff,0xffff,fr10 568 set_fr_iimmed 0x0000,0xffff,fr9 569 set_fr_iimmed 0xffff,0xffff,fr11 570 cmqmachu fr8,fr10,acc0,cc5,1 571 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 572 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 573 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 574 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 575 test_accg_immed 0xff,accg0 ; saturation 576 test_acc_immed 0xffffffff,acc0 577 test_accg_immed 0xff,accg1 578 test_acc_immed 0xffffffff,acc1 579 test_accg_immed 0xff,accg2 ; saturation 580 test_acc_immed 0xffffffff,acc2 581 test_accg_immed 0xff,accg3 582 test_acc_immed 0xffffffff,acc3 583 584 set_spr_immed 0,msr0 585 set_accg_immed 0x00000011,accg0 586 set_acc_immed 0x11111111,acc0 587 set_accg_immed 0x00000022,accg1 588 set_acc_immed 0x22222222,acc1 589 set_accg_immed 0x00000033,accg2 590 set_acc_immed 0x33333333,acc2 591 set_accg_immed 0x00000044,accg3 592 set_acc_immed 0x44444444,acc3 593 set_fr_iimmed 3,2,fr8 ; multiply small numbers 594 set_fr_iimmed 2,3,fr10 595 set_fr_iimmed 1,2,fr9 ; multiply by 1 596 set_fr_iimmed 2,1,fr11 597 cmqmachu fr8,fr10,acc0,cc2,1 598 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 599 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 600 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 601 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 602 test_accg_immed 0x00000011,accg0 603 test_acc_immed 0x11111111,acc0 604 test_accg_immed 0x00000022,accg1 605 test_acc_immed 0x22222222,acc1 606 test_accg_immed 0x00000033,accg2 607 test_acc_immed 0x33333333,acc2 608 test_accg_immed 0x00000044,accg3 609 test_acc_immed 0x44444444,acc3 610 611 set_fr_iimmed 0,2,fr8 ; multiply by 0 612 set_fr_iimmed 2,0,fr10 613 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result 614 set_fr_iimmed 2,0x3fff,fr11 615 cmqmachu fr8,fr10,acc0,cc2,0 616 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 617 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 618 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 619 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 620 test_accg_immed 0x00000011,accg0 621 test_acc_immed 0x11111111,acc0 622 test_accg_immed 0x00000022,accg1 623 test_acc_immed 0x22222222,acc1 624 test_accg_immed 0x00000033,accg2 625 test_acc_immed 0x33333333,acc2 626 test_accg_immed 0x00000044,accg3 627 test_acc_immed 0x44444444,acc3 628 629 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result 630 set_fr_iimmed 2,0x4000,fr10 631 set_fr_iimmed 0x8000,2,fr9 ; 17 bit result 632 set_fr_iimmed 2,0x8000,fr11 633 cmqmachu fr8,fr10,acc0,cc2,1 634 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 635 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 636 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 637 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 638 test_accg_immed 0x00000011,accg0 639 test_acc_immed 0x11111111,acc0 640 test_accg_immed 0x00000022,accg1 641 test_acc_immed 0x22222222,acc1 642 test_accg_immed 0x00000033,accg2 643 test_acc_immed 0x33333333,acc2 644 test_accg_immed 0x00000044,accg3 645 test_acc_immed 0x44444444,acc3 646 647 set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result 648 set_fr_iimmed 0x7fff,0x7fff,fr10 649 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result 650 set_fr_iimmed 0x8000,0x8000,fr11 651 cmqmachu fr8,fr10,acc0,cc6,0 652 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 653 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 654 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 655 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 656 test_accg_immed 0x00000011,accg0 657 test_acc_immed 0x11111111,acc0 658 test_accg_immed 0x00000022,accg1 659 test_acc_immed 0x22222222,acc1 660 test_accg_immed 0x00000033,accg2 661 test_acc_immed 0x33333333,acc2 662 test_accg_immed 0x00000044,accg3 663 test_acc_immed 0x44444444,acc3 664 665 set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result 666 set_fr_iimmed 0xffff,0xffff,fr10 667 set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result 668 set_fr_iimmed 0xffff,0xffff,fr11 669 cmqmachu fr8,fr10,acc0,cc6,1 670 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 671 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 672 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 673 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 674 test_accg_immed 0x00000011,accg0 675 test_acc_immed 0x11111111,acc0 676 test_accg_immed 0x00000022,accg1 677 test_acc_immed 0x22222222,acc1 678 test_accg_immed 0x00000033,accg2 679 test_acc_immed 0x33333333,acc2 680 test_accg_immed 0x00000044,accg3 681 test_acc_immed 0x44444444,acc3 682 683 set_accg_immed 0xff,accg0 ; saturation 684 set_acc_immed 0xffffffff,acc0 685 set_accg_immed 0xff,accg1 686 set_acc_immed 0xffffffff,acc1 687 set_accg_immed 0xff,accg2 ; saturation 688 set_acc_immed 0xffffffff,acc2 689 set_accg_immed 0xff,accg3 690 set_acc_immed 0xffffffff,acc3 691 set_fr_iimmed 1,1,fr8 692 set_fr_iimmed 1,1,fr10 693 set_fr_iimmed 1,1,fr9 694 set_fr_iimmed 1,1,fr11 695 cmqmachu fr8,fr10,acc0,cc6,0 696 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 697 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 698 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 699 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 700 test_accg_immed 0xff,accg0 ; saturation 701 test_acc_immed 0xffffffff,acc0 702 test_accg_immed 0xff,accg1 703 test_acc_immed 0xffffffff,acc1 704 test_accg_immed 0xff,accg2 ; saturation 705 test_acc_immed 0xffffffff,acc2 706 test_accg_immed 0xff,accg3 707 test_acc_immed 0xffffffff,acc3 708 709 set_fr_iimmed 0xffff,0x0000,fr8 710 set_fr_iimmed 0xffff,0xffff,fr10 711 set_fr_iimmed 0x0000,0xffff,fr9 712 set_fr_iimmed 0xffff,0xffff,fr11 713 cmqmachu fr8,fr10,acc0,cc6,1 714 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 715 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 716 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 717 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 718 test_accg_immed 0xff,accg0 ; saturation 719 test_acc_immed 0xffffffff,acc0 720 test_accg_immed 0xff,accg1 721 test_acc_immed 0xffffffff,acc1 722 test_accg_immed 0xff,accg2 ; saturation 723 test_acc_immed 0xffffffff,acc2 724 test_accg_immed 0xff,accg3 725 test_acc_immed 0xffffffff,acc3 726 ; 727 set_spr_immed 0,msr0 728 set_accg_immed 0x00000011,accg0 729 set_acc_immed 0x11111111,acc0 730 set_accg_immed 0x00000022,accg1 731 set_acc_immed 0x22222222,acc1 732 set_accg_immed 0x00000033,accg2 733 set_acc_immed 0x33333333,acc2 734 set_accg_immed 0x00000044,accg3 735 set_acc_immed 0x44444444,acc3 736 set_fr_iimmed 3,2,fr8 ; multiply small numbers 737 set_fr_iimmed 2,3,fr10 738 set_fr_iimmed 1,2,fr9 ; multiply by 1 739 set_fr_iimmed 2,1,fr11 740 cmqmachu fr8,fr10,acc0,cc3,1 741 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 742 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 743 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 744 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 745 test_accg_immed 0x00000011,accg0 746 test_acc_immed 0x11111111,acc0 747 test_accg_immed 0x00000022,accg1 748 test_acc_immed 0x22222222,acc1 749 test_accg_immed 0x00000033,accg2 750 test_acc_immed 0x33333333,acc2 751 test_accg_immed 0x00000044,accg3 752 test_acc_immed 0x44444444,acc3 753 754 set_fr_iimmed 0,2,fr8 ; multiply by 0 755 set_fr_iimmed 2,0,fr10 756 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result 757 set_fr_iimmed 2,0x3fff,fr11 758 cmqmachu fr8,fr10,acc0,cc3,0 759 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 760 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 761 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 762 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 763 test_accg_immed 0x00000011,accg0 764 test_acc_immed 0x11111111,acc0 765 test_accg_immed 0x00000022,accg1 766 test_acc_immed 0x22222222,acc1 767 test_accg_immed 0x00000033,accg2 768 test_acc_immed 0x33333333,acc2 769 test_accg_immed 0x00000044,accg3 770 test_acc_immed 0x44444444,acc3 771 772 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result 773 set_fr_iimmed 2,0x4000,fr10 774 set_fr_iimmed 0x8000,2,fr9 ; 17 bit result 775 set_fr_iimmed 2,0x8000,fr11 776 cmqmachu fr8,fr10,acc0,cc3,1 777 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 778 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 779 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 780 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 781 test_accg_immed 0x00000011,accg0 782 test_acc_immed 0x11111111,acc0 783 test_accg_immed 0x00000022,accg1 784 test_acc_immed 0x22222222,acc1 785 test_accg_immed 0x00000033,accg2 786 test_acc_immed 0x33333333,acc2 787 test_accg_immed 0x00000044,accg3 788 test_acc_immed 0x44444444,acc3 789 790 set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result 791 set_fr_iimmed 0x7fff,0x7fff,fr10 792 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result 793 set_fr_iimmed 0x8000,0x8000,fr11 794 cmqmachu fr8,fr10,acc0,cc7,0 795 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 796 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 797 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 798 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 799 test_accg_immed 0x00000011,accg0 800 test_acc_immed 0x11111111,acc0 801 test_accg_immed 0x00000022,accg1 802 test_acc_immed 0x22222222,acc1 803 test_accg_immed 0x00000033,accg2 804 test_acc_immed 0x33333333,acc2 805 test_accg_immed 0x00000044,accg3 806 test_acc_immed 0x44444444,acc3 807 808 set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result 809 set_fr_iimmed 0xffff,0xffff,fr10 810 set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result 811 set_fr_iimmed 0xffff,0xffff,fr11 812 cmqmachu fr8,fr10,acc0,cc7,1 813 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 814 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 815 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 816 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 817 test_accg_immed 0x00000011,accg0 818 test_acc_immed 0x11111111,acc0 819 test_accg_immed 0x00000022,accg1 820 test_acc_immed 0x22222222,acc1 821 test_accg_immed 0x00000033,accg2 822 test_acc_immed 0x33333333,acc2 823 test_accg_immed 0x00000044,accg3 824 test_acc_immed 0x44444444,acc3 825 826 set_accg_immed 0xff,accg0 ; saturation 827 set_acc_immed 0xffffffff,acc0 828 set_accg_immed 0xff,accg1 829 set_acc_immed 0xffffffff,acc1 830 set_accg_immed 0xff,accg2 ; saturation 831 set_acc_immed 0xffffffff,acc2 832 set_accg_immed 0xff,accg3 833 set_acc_immed 0xffffffff,acc3 834 set_fr_iimmed 1,1,fr8 835 set_fr_iimmed 1,1,fr10 836 set_fr_iimmed 1,1,fr9 837 set_fr_iimmed 1,1,fr11 838 cmqmachu fr8,fr10,acc0,cc7,0 839 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 840 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 841 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 842 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 843 test_accg_immed 0xff,accg0 ; saturation 844 test_acc_immed 0xffffffff,acc0 845 test_accg_immed 0xff,accg1 846 test_acc_immed 0xffffffff,acc1 847 test_accg_immed 0xff,accg2 ; saturation 848 test_acc_immed 0xffffffff,acc2 849 test_accg_immed 0xff,accg3 850 test_acc_immed 0xffffffff,acc3 851 852 set_fr_iimmed 0xffff,0x0000,fr8 853 set_fr_iimmed 0xffff,0xffff,fr10 854 set_fr_iimmed 0x0000,0xffff,fr9 855 set_fr_iimmed 0xffff,0xffff,fr11 856 cmqmachu fr8,fr10,acc0,cc7,1 857 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 858 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 859 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 860 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 861 test_accg_immed 0xff,accg0 ; saturation 862 test_acc_immed 0xffffffff,acc0 863 test_accg_immed 0xff,accg1 864 test_acc_immed 0xffffffff,acc1 865 test_accg_immed 0xff,accg2 ; saturation 866 test_acc_immed 0xffffffff,acc2 867 test_accg_immed 0xff,accg3 868 test_acc_immed 0xffffffff,acc3 869 870 pass 871
Indexes created Fri Jun 26 00:24:39 UTC 2026