1 # frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond 2 # mach: all 3 4 .include "../testutils.inc" 5 6 start 7 8 .global cmqsubhus 9 cmqsubhus: 10 set_spr_immed 0x1b1b,cccr 11 12 set_fr_iimmed 0x0000,0x0000,fr10 13 set_fr_iimmed 0xdead,0xbeef,fr11 14 set_fr_iimmed 0x0000,0x0000,fr12 15 set_fr_iimmed 0x0000,0x0000,fr13 16 cmqsubhus fr10,fr12,fr14,cc0,1 17 test_fr_limmed 0x0000,0x0000,fr14 18 test_fr_limmed 0xdead,0xbeef,fr15 19 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 20 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 21 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 22 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 23 24 set_fr_iimmed 0x1234,0x5678,fr10 25 set_fr_iimmed 0x7ffe,0x7ffe,fr11 26 set_fr_iimmed 0x1111,0x1111,fr12 27 set_fr_iimmed 0x0002,0x0001,fr13 28 cmqsubhus fr10,fr12,fr14,cc0,1 29 test_fr_limmed 0x0123,0x4567,fr14 30 test_fr_limmed 0x7ffc,0x7ffd,fr15 31 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 32 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 33 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 34 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 35 36 set_spr_immed 0,msr0 37 set_fr_iimmed 0x0001,0x0001,fr10 38 set_fr_iimmed 0x0001,0x0001,fr11 39 set_fr_iimmed 0x0001,0x0002,fr12 40 set_fr_iimmed 0x0002,0x0001,fr13 41 cmqsubhus fr10,fr12,fr14,cc4,1 42 test_fr_limmed 0x0000,0x0000,fr14 43 test_fr_limmed 0x0000,0x0000,fr15 44 test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set 45 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 46 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 47 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 48 49 set_spr_immed 0,msr0 50 set_fr_iimmed 0x0001,0x0001,fr10 51 set_fr_iimmed 0x0002,0x0002,fr11 52 set_fr_iimmed 0x0000,0x0001,fr12 53 set_fr_iimmed 0x0002,0x0003,fr13 54 cmqsubhus.p fr10,fr10,fr14,cc4,1 55 cmqsubhus fr10,fr12,fr16,cc4,1 56 test_fr_limmed 0x0000,0x0000,fr14 57 test_fr_limmed 0x0000,0x0000,fr15 58 test_fr_limmed 0x0001,0x0000,fr16 59 test_fr_limmed 0x0000,0x0000,fr17 60 test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set 61 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 62 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 63 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 64 65 set_spr_immed 0,msr0 66 set_fr_iimmed 0x0000,0x0000,fr10 67 set_fr_iimmed 0xdead,0xbeef,fr11 68 set_fr_iimmed 0x0000,0x0000,fr12 69 set_fr_iimmed 0x0000,0x0000,fr13 70 cmqsubhus fr10,fr12,fr14,cc1,0 71 test_fr_limmed 0x0000,0x0000,fr14 72 test_fr_limmed 0xdead,0xbeef,fr15 73 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 74 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 75 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 76 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 77 78 set_fr_iimmed 0x1234,0x5678,fr10 79 set_fr_iimmed 0x7ffe,0x7ffe,fr11 80 set_fr_iimmed 0x1111,0x1111,fr12 81 set_fr_iimmed 0x0002,0x0001,fr13 82 cmqsubhus fr10,fr12,fr14,cc1,0 83 test_fr_limmed 0x0123,0x4567,fr14 84 test_fr_limmed 0x7ffc,0x7ffd,fr15 85 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 86 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 87 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 88 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 89 90 set_spr_immed 0,msr0 91 set_fr_iimmed 0x0001,0x0001,fr10 92 set_fr_iimmed 0x0001,0x0001,fr11 93 set_fr_iimmed 0x0001,0x0002,fr12 94 set_fr_iimmed 0x0002,0x0001,fr13 95 cmqsubhus fr10,fr12,fr14,cc5,0 96 test_fr_limmed 0x0000,0x0000,fr14 97 test_fr_limmed 0x0000,0x0000,fr15 98 test_spr_bits 0x3c,2,0x6,msr0 ; msr0.sie is set 99 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 100 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 101 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 102 103 set_spr_immed 0,msr0 104 set_fr_iimmed 0x0001,0x0001,fr10 105 set_fr_iimmed 0x0002,0x0002,fr11 106 set_fr_iimmed 0x0000,0x0001,fr12 107 set_fr_iimmed 0x0002,0x0003,fr13 108 cmqsubhus.p fr10,fr10,fr14,cc5,0 109 cmqsubhus fr10,fr12,fr16,cc5,0 110 test_fr_limmed 0x0000,0x0000,fr14 111 test_fr_limmed 0x0000,0x0000,fr15 112 test_fr_limmed 0x0001,0x0000,fr16 113 test_fr_limmed 0x0000,0x0000,fr17 114 test_spr_bits 0x3c,2,0x1,msr0 ; msr0.sie is set 115 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 116 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 117 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 118 119 set_fr_iimmed 0x1111,0x1111,fr14 120 set_fr_iimmed 0x2222,0x2222,fr15 121 set_spr_immed 0,msr0 122 set_fr_iimmed 0x0000,0x0000,fr10 123 set_fr_iimmed 0xdead,0xbeef,fr11 124 set_fr_iimmed 0x0000,0x0000,fr12 125 set_fr_iimmed 0x0000,0x0000,fr13 126 cmqsubhus fr10,fr12,fr14,cc0,0 127 test_fr_limmed 0x1111,0x1111,fr14 128 test_fr_limmed 0x2222,0x2222,fr15 129 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 130 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 131 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 132 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 133 134 set_fr_iimmed 0x1234,0x5678,fr10 135 set_fr_iimmed 0x7ffe,0x7ffe,fr11 136 set_fr_iimmed 0x1111,0x1111,fr12 137 set_fr_iimmed 0x0002,0x0001,fr13 138 cmqsubhus fr10,fr12,fr14,cc0,0 139 test_fr_limmed 0x1111,0x1111,fr14 140 test_fr_limmed 0x2222,0x2222,fr15 141 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 142 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 143 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 144 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 145 146 set_spr_immed 0,msr0 147 set_fr_iimmed 0x0001,0x0001,fr10 148 set_fr_iimmed 0x0001,0x0001,fr11 149 set_fr_iimmed 0x0001,0x0002,fr12 150 set_fr_iimmed 0x0002,0x0001,fr13 151 cmqsubhus fr10,fr12,fr14,cc4,0 152 test_fr_limmed 0x1111,0x1111,fr14 153 test_fr_limmed 0x2222,0x2222,fr15 154 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 155 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 156 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 157 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 158 159 set_fr_iimmed 0x3333,0x3333,fr16 160 set_fr_iimmed 0x4444,0x4444,fr17 161 set_spr_immed 0,msr0 162 set_fr_iimmed 0x0001,0x0001,fr10 163 set_fr_iimmed 0x0002,0x0002,fr11 164 set_fr_iimmed 0x0000,0x0001,fr12 165 set_fr_iimmed 0x0002,0x0003,fr13 166 cmqsubhus.p fr10,fr10,fr14,cc4,0 167 cmqsubhus fr10,fr12,fr16,cc4,0 168 test_fr_limmed 0x1111,0x1111,fr14 169 test_fr_limmed 0x2222,0x2222,fr15 170 test_fr_limmed 0x3333,0x3333,fr16 171 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 172 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 173 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 174 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 175 test_fr_limmed 0x4444,0x4444,fr17 176 177 set_fr_iimmed 0x1111,0x1111,fr14 178 set_fr_iimmed 0x2222,0x2222,fr15 179 set_spr_immed 0,msr0 180 set_fr_iimmed 0x0000,0x0000,fr10 181 set_fr_iimmed 0xdead,0xbeef,fr11 182 set_fr_iimmed 0x0000,0x0000,fr12 183 set_fr_iimmed 0x0000,0x0000,fr13 184 cmqsubhus fr10,fr12,fr14,cc1,1 185 test_fr_limmed 0x1111,0x1111,fr14 186 test_fr_limmed 0x2222,0x2222,fr15 187 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 188 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 189 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 190 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 191 192 set_fr_iimmed 0x1234,0x5678,fr10 193 set_fr_iimmed 0x7ffe,0x7ffe,fr11 194 set_fr_iimmed 0x1111,0x1111,fr12 195 set_fr_iimmed 0x0002,0x0001,fr13 196 cmqsubhus fr10,fr12,fr14,cc1,1 197 test_fr_limmed 0x1111,0x1111,fr14 198 test_fr_limmed 0x2222,0x2222,fr15 199 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 200 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 201 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 202 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 203 204 set_spr_immed 0,msr0 205 set_fr_iimmed 0x0001,0x0001,fr10 206 set_fr_iimmed 0x0001,0x0001,fr11 207 set_fr_iimmed 0x0001,0x0002,fr12 208 set_fr_iimmed 0x0002,0x0001,fr13 209 cmqsubhus fr10,fr12,fr14,cc5,1 210 test_fr_limmed 0x1111,0x1111,fr14 211 test_fr_limmed 0x2222,0x2222,fr15 212 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 213 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 214 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 215 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 216 217 set_fr_iimmed 0x3333,0x3333,fr16 218 set_fr_iimmed 0x4444,0x4444,fr17 219 set_spr_immed 0,msr0 220 set_fr_iimmed 0x0001,0x0001,fr10 221 set_fr_iimmed 0x0002,0x0002,fr11 222 set_fr_iimmed 0x0000,0x0001,fr12 223 set_fr_iimmed 0x0002,0x0003,fr13 224 cmqsubhus.p fr10,fr10,fr14,cc5,1 225 cmqsubhus fr10,fr12,fr16,cc5,1 226 test_fr_limmed 0x1111,0x1111,fr14 227 test_fr_limmed 0x2222,0x2222,fr15 228 test_fr_limmed 0x3333,0x3333,fr16 229 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 230 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 231 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 232 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 233 test_fr_limmed 0x4444,0x4444,fr17 234 235 set_fr_iimmed 0x1111,0x1111,fr14 236 set_fr_iimmed 0x2222,0x2222,fr15 237 set_spr_immed 0,msr0 238 set_fr_iimmed 0x0000,0x0000,fr10 239 set_fr_iimmed 0xdead,0xbeef,fr11 240 set_fr_iimmed 0x0000,0x0000,fr12 241 set_fr_iimmed 0x0000,0x0000,fr13 242 cmqsubhus fr10,fr12,fr14,cc2,1 243 test_fr_limmed 0x1111,0x1111,fr14 244 test_fr_limmed 0x2222,0x2222,fr15 245 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 246 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 247 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 248 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 249 250 set_fr_iimmed 0x1234,0x5678,fr10 251 set_fr_iimmed 0x7ffe,0x7ffe,fr11 252 set_fr_iimmed 0x1111,0x1111,fr12 253 set_fr_iimmed 0x0002,0x0001,fr13 254 cmqsubhus fr10,fr12,fr14,cc2,0 255 test_fr_limmed 0x1111,0x1111,fr14 256 test_fr_limmed 0x2222,0x2222,fr15 257 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 258 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 259 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 260 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 261 262 set_spr_immed 0,msr0 263 set_fr_iimmed 0x0001,0x0001,fr10 264 set_fr_iimmed 0x0001,0x0001,fr11 265 set_fr_iimmed 0x0001,0x0002,fr12 266 set_fr_iimmed 0x0002,0x0001,fr13 267 cmqsubhus fr10,fr12,fr14,cc6,1 268 test_fr_limmed 0x1111,0x1111,fr14 269 test_fr_limmed 0x2222,0x2222,fr15 270 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 271 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 272 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 273 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 274 275 set_fr_iimmed 0x3333,0x3333,fr16 276 set_fr_iimmed 0x4444,0x4444,fr17 277 set_spr_immed 0,msr0 278 set_fr_iimmed 0x0001,0x0001,fr10 279 set_fr_iimmed 0x0002,0x0002,fr11 280 set_fr_iimmed 0x0000,0x0001,fr12 281 set_fr_iimmed 0x0002,0x0003,fr13 282 cmqsubhus.p fr10,fr10,fr14,cc6,0 283 cmqsubhus fr10,fr12,fr16,cc6,1 284 test_fr_limmed 0x1111,0x1111,fr14 285 test_fr_limmed 0x2222,0x2222,fr15 286 test_fr_limmed 0x3333,0x3333,fr16 287 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 288 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 289 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 290 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 291 test_fr_limmed 0x4444,0x4444,fr17 292 ; 293 set_fr_iimmed 0x1111,0x1111,fr14 294 set_fr_iimmed 0x2222,0x2222,fr15 295 set_spr_immed 0,msr0 296 set_fr_iimmed 0x0000,0x0000,fr10 297 set_fr_iimmed 0xdead,0xbeef,fr11 298 set_fr_iimmed 0x0000,0x0000,fr12 299 set_fr_iimmed 0x0000,0x0000,fr13 300 cmqsubhus fr10,fr12,fr14,cc3,1 301 test_fr_limmed 0x1111,0x1111,fr14 302 test_fr_limmed 0x2222,0x2222,fr15 303 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 304 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 305 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 306 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 307 308 set_fr_iimmed 0x1234,0x5678,fr10 309 set_fr_iimmed 0x7ffe,0x7ffe,fr11 310 set_fr_iimmed 0x1111,0x1111,fr12 311 set_fr_iimmed 0x0002,0x0001,fr13 312 cmqsubhus fr10,fr12,fr14,cc3,0 313 test_fr_limmed 0x1111,0x1111,fr14 314 test_fr_limmed 0x2222,0x2222,fr15 315 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 316 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 317 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 318 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 319 320 set_spr_immed 0,msr0 321 set_fr_iimmed 0x0001,0x0001,fr10 322 set_fr_iimmed 0x0001,0x0001,fr11 323 set_fr_iimmed 0x0001,0x0002,fr12 324 set_fr_iimmed 0x0002,0x0001,fr13 325 cmqsubhus fr10,fr12,fr14,cc7,1 326 test_fr_limmed 0x1111,0x1111,fr14 327 test_fr_limmed 0x2222,0x2222,fr15 328 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 329 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 330 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 331 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 332 333 set_fr_iimmed 0x3333,0x3333,fr16 334 set_fr_iimmed 0x4444,0x4444,fr17 335 set_spr_immed 0,msr0 336 set_fr_iimmed 0x0001,0x0001,fr10 337 set_fr_iimmed 0x0002,0x0002,fr11 338 set_fr_iimmed 0x0000,0x0001,fr12 339 set_fr_iimmed 0x0002,0x0003,fr13 340 cmqsubhus.p fr10,fr10,fr14,cc7,0 341 cmqsubhus fr10,fr12,fr16,cc7,1 342 test_fr_limmed 0x1111,0x1111,fr14 343 test_fr_limmed 0x2222,0x2222,fr15 344 test_fr_limmed 0x3333,0x3333,fr16 345 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 346 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 347 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 348 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 349 test_fr_limmed 0x4444,0x4444,fr17 350 351 pass 352
Indexes created Fri Jun 26 00:24:39 UTC 2026