1 # frv testcase for mmachs $GRi,$GRj,$ACCk 2 # mach: all 3 4 .include "../testutils.inc" 5 6 start 7 8 .global mmachs 9 mmachs: 10 ; Positive operands 11 set_fr_iimmed 2,3,fr7 ; multiply small numbers 12 set_fr_iimmed 3,2,fr8 13 mmachs fr7,fr8,acc0 14 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 15 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 16 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 17 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 18 test_accg_immed 0,accg0 19 test_acc_immed 6,acc0 20 test_accg_immed 0,accg1 21 test_acc_immed 6,acc1 22 23 set_fr_iimmed 0,1,fr7 ; multiply by 0 24 set_fr_iimmed 2,0,fr8 25 mmachs fr7,fr8,acc0 26 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 27 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 28 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 29 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 30 test_accg_immed 0,accg0 31 test_acc_immed 6,acc0 32 test_accg_immed 0,accg1 33 test_acc_immed 6,acc1 34 35 set_fr_iimmed 2,1,fr7 ; multiply by 1 36 set_fr_iimmed 1,2,fr8 37 mmachs fr7,fr8,acc0 38 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 39 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 40 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 41 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 42 test_accg_immed 0,accg0 43 test_acc_immed 8,acc0 44 test_accg_immed 0,accg1 45 test_acc_immed 8,acc1 46 47 set_fr_iimmed 0x3fff,2,fr7 ; 15 bit result 48 set_fr_iimmed 2,0x3fff,fr8 49 mmachs fr7,fr8,acc0 50 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 51 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 52 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 53 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 54 test_accg_immed 0,accg0 55 test_acc_limmed 0,0x8006,acc0 56 test_accg_immed 0,accg1 57 test_acc_limmed 0,0x8006,acc1 58 59 set_fr_iimmed 0x4000,2,fr7 ; 16 bit result 60 set_fr_iimmed 2,0x4000,fr8 61 mmachs fr7,fr8,acc0 62 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 63 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 64 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 65 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 66 test_accg_immed 0,accg0 67 test_acc_limmed 0x0001,0x0006,acc0 68 test_accg_immed 0,accg1 69 test_acc_limmed 0x0001,0x0006,acc1 70 71 set_fr_iimmed 0x7fff,0x7fff,fr7 ; max positive result 72 set_fr_iimmed 0x7fff,0x7fff,fr8 73 mmachs fr7,fr8,acc0 74 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 75 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 76 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 77 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 78 test_accg_immed 0,accg0 79 test_acc_limmed 0x4000,0x0007,acc0 80 test_accg_immed 0,accg1 81 test_acc_limmed 0x4000,0x0007,acc1 82 83 ; Mixed operands 84 set_fr_iimmed 2,0xfffd,fr7 ; multiply small numbers 85 set_fr_iimmed 0xfffd,2,fr8 86 mmachs fr7,fr8,acc0 87 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 88 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 89 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 90 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 91 test_accg_immed 0,accg0 92 test_acc_limmed 0x4000,0x0001,acc0 93 test_accg_immed 0,accg1 94 test_acc_limmed 0x4000,0x0001,acc1 95 96 set_fr_iimmed 0xfffe,1,fr7 ; multiply by 1 97 set_fr_iimmed 1,0xfffe,fr8 98 mmachs fr7,fr8,acc0 99 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 100 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 101 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 102 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 103 test_accg_immed 0,accg0 104 test_acc_limmed 0x3fff,0xffff,acc0 105 test_accg_immed 0,accg1 106 test_acc_limmed 0x3fff,0xffff,acc1 107 108 set_fr_iimmed 0xfffe,0,fr7 ; multiply by 0 109 set_fr_iimmed 0,0xfffe,fr8 110 mmachs fr7,fr8,acc0 111 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 112 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 113 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 114 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 115 test_accg_immed 0,accg0 116 test_acc_limmed 0x3fff,0xffff,acc0 117 test_accg_immed 0,accg1 118 test_acc_limmed 0x3fff,0xffff,acc1 119 120 set_fr_iimmed 0x2001,0xfffe,fr7 ; 15 bit result 121 set_fr_iimmed 0xfffe,0x2001,fr8 122 mmachs fr7,fr8,acc0 123 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 124 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 125 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 126 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 127 test_accg_immed 0,accg0 128 test_acc_limmed 0x3fff,0xbffd,acc0 129 test_accg_immed 0,accg1 130 test_acc_limmed 0x3fff,0xbffd,acc1 131 132 set_fr_iimmed 0x4000,0xfffe,fr7 ; 16 bit result 133 set_fr_iimmed 0xfffe,0x4000,fr8 134 mmachs fr7,fr8,acc0 135 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 136 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 137 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 138 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 139 test_accg_immed 0,accg0 140 test_acc_limmed 0x3fff,0x3ffd,acc0 141 test_accg_immed 0,accg1 142 test_acc_limmed 0x3fff,0x3ffd,acc1 143 144 set_fr_iimmed 0x7fff,0x8000,fr7 ; max negative result 145 set_fr_iimmed 0x8000,0x7fff,fr8 146 mmachs fr7,fr8,acc0 147 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 148 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 149 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 150 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 151 test_accg_immed 0xff,accg0 152 test_acc_limmed 0xffff,0xbffd,acc0 153 test_accg_immed 0xff,accg1 154 test_acc_limmed 0xffff,0xbffd,acc1 155 156 ; Negative operands 157 set_fr_iimmed 0xfffe,0xfffd,fr7 ; multiply small numbers 158 set_fr_iimmed 0xfffd,0xfffe,fr8 159 mmachs fr7,fr8,acc0 160 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 161 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 162 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 163 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 164 test_accg_immed 0xff,accg0 165 test_acc_limmed 0xffff,0xc003,acc0 166 test_accg_immed 0xff,accg1 167 test_acc_limmed 0xffff,0xc003,acc1 168 169 set_fr_iimmed 0xffff,0xfffe,fr7 ; multiply by -1 170 set_fr_iimmed 0xfffe,0xffff,fr8 171 mmachs fr7,fr8,acc0 172 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 173 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 174 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 175 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 176 test_accg_immed 0xff,accg0 177 test_acc_limmed 0xffff,0xc005,acc0 178 test_accg_immed 0xff,accg1 179 test_acc_limmed 0xffff,0xc005,acc1 180 181 set_fr_iimmed 0x8001,0x8001,fr7 ; almost max positive result 182 set_fr_iimmed 0x8001,0x8001,fr8 183 mmachs fr7,fr8,acc0 184 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 185 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 186 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 187 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 188 test_accg_immed 0,accg0 189 test_acc_immed 0x3ffec006,acc0 190 test_accg_immed 0,accg1 191 test_acc_immed 0x3ffec006,acc1 192 193 set_fr_iimmed 0x8000,0x8000,fr7 ; max positive result 194 set_fr_iimmed 0x8000,0x8000,fr8 195 mmachs fr7,fr8,acc0 196 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 197 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 198 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 199 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 200 test_accg_immed 0,accg0 201 test_acc_immed 0x7ffec006,acc0 202 test_accg_immed 0,accg1 203 test_acc_immed 0x7ffec006,acc1 204 205 set_accg_immed 0x7f,accg0 ; saturation 206 set_acc_immed 0xffffffff,acc0 207 set_accg_immed 0x7f,accg1 208 set_acc_immed 0xffffffff,acc1 209 set_fr_iimmed 1,1,fr7 210 set_fr_iimmed 1,1,fr8 211 mmachs fr7,fr8,acc0 212 test_accg_immed 0x7f,accg0 213 test_acc_limmed 0xffff,0xffff,acc0 214 test_accg_immed 0x7f,accg1 215 test_acc_limmed 0xffff,0xffff,acc1 216 217 set_fr_iimmed 0x7fff,0x7fff,fr7 ; saturation 218 set_fr_iimmed 0x7fff,0x7fff,fr8 219 mmachs fr7,fr8,acc0 220 test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set 221 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 222 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 223 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 224 test_accg_immed 0x7f,accg0 225 test_acc_limmed 0xffff,0xffff,acc0 226 test_accg_immed 0x7f,accg1 227 test_acc_limmed 0xffff,0xffff,acc1 228 229 set_accg_immed 0x80,accg0 ; saturation 230 set_acc_immed 0,acc0 231 set_accg_immed 0x80,accg1 232 set_acc_immed 0,acc1 233 set_fr_iimmed 0xffff,0,fr7 234 set_fr_iimmed 1,0xffff,fr8 235 mmachs fr7,fr8,acc0 236 test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set 237 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 238 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 239 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 240 test_accg_immed 0x80,accg0 241 test_acc_immed 0,acc0 242 test_accg_immed 0x80,accg1 243 test_acc_immed 0,acc1 244 245 set_fr_iimmed 0x0000,0x8000,fr7 ; saturation 246 set_fr_iimmed 0x7fff,0x7fff,fr8 247 mmachs fr7,fr8,acc0 248 test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set 249 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 250 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 251 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 252 test_accg_immed 0x80,accg0 253 test_acc_immed 0,acc0 254 test_accg_immed 0x80,accg1 255 test_acc_immed 0,acc1 256 257 pass 258 259 260
Indexes created Sun Jun 28 00:24:58 UTC 2026