1 # frv testcase to generate fp_exception 2 # mach: fr550 3 .include "testutils.inc" 4 5 float_constants 6 start 7 load_float_constants 8 9 .global align 10 align: 11 ; clear the packing bit if the insn at 'pack:'. We can't simply use 12 ; '.p' because the assembler will catch the error. 13 set_gr_mem pack,gr10 14 and_gr_immed 0x7fffffff,gr10 15 set_mem_gr gr10,pack 16 set_gr_addr pack,gr10 17 flush_data_cache gr10 18 19 ; Make the the source register number odd at badst. We can't simply 20 ; code an odd register number because the assembler will catch the 21 ; error. 22 set_gr_mem badst,gr10 23 or_gr_immed 0x02000000,gr10 24 set_mem_gr gr10,badst 25 set_gr_addr badst,gr10 26 flush_data_cache gr10 27 28 ; Make the the dest register number odd at badld. We can't simply 29 ; code an odd register number because the assembler will catch the 30 ; error. 31 set_gr_mem badld,gr10 32 or_gr_immed 0x02000000,gr10 33 set_mem_gr gr10,badld 34 set_gr_addr badld,gr10 35 flush_data_cache gr10 36 37 and_spr_immed -4081,tbr ; clear tbr.tt 38 set_gr_spr tbr,gr17 39 inc_gr_immed 0x070,gr17 ; address of exception handler 40 set_bctrlr_0_0 gr17 41 inc_gr_immed 0x060,gr17 ; address of exception handler 42 set_bctrlr_0_0 gr17 43 set_spr_immed 128,lcr 44 set_spr_addr ok1,lr 45 set_psr_et 1 46 inc_gr_immed -4,sp ; for alignment 47 48 set_gr_immed 0,gr20 ; PC increment 49 set_gr_immed 0,gr15 50 51 set_spr_addr ok3,lr 52 set_gr_immed 4,gr20 ; PC increment 53 badst: stdfi fr0,@(sp,0) ; misaligned reg -- slot I0 54 test_gr_immed 1,gr15 55 56 set_spr_addr ok4,lr 57 set_gr_immed 8,gr20 ; PC increment 58 nop.p 59 badld: lddfi @(sp,0),fr8 ; misaligned reg -- slot I1 60 test_gr_immed 2,gr15 61 62 set_spr_addr ok5,lr 63 set_gr_immed 20,gr20 ; PC increment 64 fnegs.p fr9,fr9 65 fnegs.p fr9,fr10 66 fnegs.p fr9,fr11 67 pack: fnegs fr10,fr12 68 fnegs fr10,fr13 ; packing violation 69 test_gr_immed 3,gr15 70 71 set_spr_addr ok1,lr 72 set_gr_immed 4,gr20 ; PC increment 73 bad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented) 74 test_gr_immed 4,gr15 75 76 and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception 77 set_fr_iimmed 0x7f7f,0xffff,fr0 78 set_fr_iimmed 0x0000,0x0000,fr1 79 fdivs fr0,fr1,fr2 ; div/0 -- no exception 80 test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set 81 test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set 82 test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear 83 84 set_spr_addr ok2,lr 85 set_gr_immed 0,gr20 ; PC increment 86 or_spr_immed 0x04000000,fsr0 ; enable div/0 fp_exception 87 set_fr_iimmed 0xdead,0xbeef,fr2 88 div0: fdivs fr0,fr1,fr2 ; fp_exception - div/0 89 test_fr_iimmed 0xdeadbeef,fr2 ; fr2 not updated 90 test_gr_immed 5,gr15 91 92 and_spr_immed 0xfdffffff,fsr0 ; disable inexact fp_exception 93 fsqrts fr32,fr2 ; inexact -- no exception 94 test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is never set 95 test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is set 96 test_spr_bits 0xe0000,17,0x0,fsr0 ; fsr0.ftt is clear 97 98 set_fr_fr fr2,fr3 ; sqrt 2 99 set_fr_iimmed 0xdead,0xbeef,fr2 100 set_spr_addr ok6,lr 101 or_spr_immed 0x02000000,fsr0 ; enable inexact fp_exception 102 inxt1: fsqrts fr32,fr2 ; fp_exception - inexact 103 test_gr_immed 6,gr15 ; handler called 104 test_fr_fr fr2,fr3 ; fr2 updated 105 106 set_fr_iimmed 0xdead,0xbeef,fr2 107 set_spr_addr ok7,lr 108 inxt2: fsqrts fr32,fr2 ; fp_exception - inexact again 109 test_gr_immed 7,gr15 ; handler called 110 test_fr_fr fr2,fr3 ; fr2 updated 111 112 pass 113 114 ; exception handler 1 -- illegal_instruction: bad insn 115 ok1: 116 test_spr_immed 1,esfr1 ; esr0 active 117 test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set 118 test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set 119 bra ret 120 121 ; exception handler 2 - fp_exception: divide by 0 122 ok2: 123 test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear 124 test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set 125 test_spr_bits 0xfc00,10,0x4,fsr0 ; fsr0.aexc is still set 126 127 test_spr_immed 4,esfr1 ; esr2 active 128 test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set 129 test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set 130 test_spr_addr div0,epcr2 ; epcr2 is set 131 bra ret 132 133 ; exception handler 3 - illegal_instruction: register exception 134 ok3: 135 test_spr_immed 1,esfr1 ; esr0 active 136 test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set 137 test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set 138 bra ret 139 140 ; exception handler 4 - illegal_instruction: register exception 141 ok4: 142 test_spr_immed 1,esfr1 ; esr0 active 143 test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set 144 test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set 145 bra ret 146 147 ; exception handler 5 - illegal_instruction: sequence violation 148 ok5: 149 test_spr_immed 1,esfr1 ; esr0 active 150 test_spr_bits 0x3e,1,0x5,esr0 ; esr0.ec is set 151 test_spr_bits 0x1,0,0x1,esr0 ; esr0.valid is set 152 bra ret 153 154 ; exception handler 6 - fp_exception: inexact 155 ok6: 156 test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear 157 test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set 158 test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set 159 160 test_spr_immed 4,esfr1 ; esr2 active 161 test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set 162 test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set 163 test_spr_addr inxt1,epcr2 ; epcr2 is set 164 bra ret 165 166 ; exception handler 7 - fp_exception: inexact again 167 ok7: 168 test_spr_bits 0x100000,20,0x0,fsr0 ; fsr0.qne is clear 169 test_spr_bits 0xe0000,17,0x1,fsr0 ; fsr0.ftt is set 170 test_spr_bits 0xfc00,10,0x6,fsr0 ; fsr0.aexc is still set 171 172 test_spr_immed 4,esfr1 ; esr2 active 173 test_spr_bits 0x3e,1,0xd,esr2 ; esr2.ec is set 174 test_spr_bits 0x1,0,0x1,esr2 ; esr2.valid is set 175 test_spr_addr inxt2,epcr2 ; epcr2 is set 176 bra ret 177 178 ret: 179 inc_gr_immed 1,gr15 180 movsg pcsr,gr60 181 add gr60,gr20,gr60 182 movgs gr60,pcsr 183 rett 0 184 fail 185 186
Indexes created Sat Sep 12 00:25:55 UTC 2026