1 # frv testcase to generate interrupts for bad register alignment 2 # mach: frv 3 .include "testutils.inc" 4 5 start 6 7 .global align 8 align: 9 and_spr_immed -4081,tbr ; clear tbr.tt 10 set_gr_spr tbr,gr17 11 inc_gr_immed 0x080,gr17 ; address of exception handler 12 set_bctrlr_0_0 gr17 13 inc_gr_immed 0x050,gr17 ; address of exception handler 14 set_bctrlr_0_0 gr17 15 set_spr_immed 128,lcr 16 set_spr_addr ok1,lr 17 set_psr_et 1 18 19 ; Make the the register number odd at bad[1-4], bad9 and bada. 20 ; We can't simply code an odd register number because the assembler 21 ; will catch the error. 22 set_gr_mem bad1,gr10 23 or_gr_immed 0x02000000,gr10 24 set_mem_gr gr10,bad1 25 set_gr_addr bad1,gr10 26 flush_data_cache gr10 27 set_gr_mem bad2,gr10 28 or_gr_immed 0x02000000,gr10 29 set_mem_gr gr10,bad2 30 set_gr_addr bad2,gr10 31 flush_data_cache gr10 32 set_gr_mem bad3,gr10 33 or_gr_immed 0x02000000,gr10 34 set_mem_gr gr10,bad3 35 set_gr_addr bad3,gr10 36 flush_data_cache gr10 37 set_gr_mem bad4,gr10 38 or_gr_immed 0x02000000,gr10 39 set_mem_gr gr10,bad4 40 set_gr_addr bad4,gr10 41 flush_data_cache gr10 42 set_gr_mem bad9,gr10 43 or_gr_immed 0x02000000,gr10 44 set_mem_gr gr10,bad9 45 set_gr_addr bad9,gr10 46 flush_data_cache gr10 47 set_gr_mem bada,gr10 48 or_gr_immed 0x02000000,gr10 49 set_mem_gr gr10,bada 50 set_gr_addr bada,gr10 51 flush_data_cache gr10 52 53 set_gr_immed 4,gr20 ; PC increment 54 set_gr_immed 0,gr15 55 inc_gr_immed -12,sp ; for memory alignment 56 57 set_gr_addr bad1,gr17 58 bad1: stdi gr0,@(sp,0) ; misaligned reg 59 test_gr_immed 1,gr15 60 61 set_gr_addr bad2,gr17 62 bad2: lddi @(sp,0),gr8 ; misaligned reg 63 test_gr_immed 2,gr15 64 65 set_gr_addr bad3,gr17 66 bad3: stdc cpr0,@(sp,gr0) ; misaligned reg 67 test_gr_immed 3,gr15 68 69 set_gr_addr bad4,gr17 70 bad4: lddc @(sp,gr0),cpr8 ; misaligned reg 71 test_gr_immed 4,gr15 72 73 set_gr_addr bad5,gr17 74 bad5: stqi gr2,@(sp,0) ; misaligned reg 75 test_gr_immed 5,gr15 76 77 set_gr_addr bad6,gr17 78 bad6: ldqi @(sp,0),gr10 ; misaligned reg 79 test_gr_immed 6,gr15 80 81 set_gr_addr bad7,gr17 82 bad7: stqc cpr2,@(sp,gr0) ; misaligned reg 83 test_gr_immed 7,gr15 84 85 set_gr_addr bad8,gr17 86 bad8: ldqc @(sp,gr0),cpr10 ; misaligned reg 87 test_gr_immed 8,gr15 88 89 set_gr_immed 0,gr20 ; PC increment 90 set_gr_addr bad9,gr17 91 bad9: stdfi fr0,@(sp,0) ; misaligned reg 92 test_gr_immed 9,gr15 93 94 set_gr_addr bada,gr17 95 bada: lddfi @(sp,0),fr8 ; misaligned reg 96 test_gr_immed 10,gr15 97 98 set_gr_addr badb,gr17 99 badb: stqfi fr2,@(sp,0) ; misaligned reg 100 test_gr_immed 11,gr15 101 102 set_gr_addr badc,gr17 103 badc: ldqfi @(sp,0),fr10 ; misaligned reg 104 test_gr_immed 12,gr15 105 106 pass 107 108 ; exception handler 109 ok1: 110 cmpi gr20,0,icc0 111 beq icc0,0,float 112 113 ; check register_exception 114 test_spr_immed 0x1,esfr1 ; esr0 is active 115 test_spr_gr epcr0,gr17 116 test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid 117 test_spr_bits 0x003e,1,0xc,esr0 ; esr0.ec is set 118 test_spr_bits 0x00c0,6,0x1,esr0 ; esr0.rec is set 119 test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set 120 movsg pcsr,gr60 121 add gr60,gr20,gr60 122 movgs gr60,pcsr 123 bra ret 124 float: 125 ; check fp_exception 126 test_spr_immed 0,esfr1 ; no esr's active 127 ret: 128 inc_gr_immed 1,gr15 129 rett 0 130 fail 131
Indexes created Thu Sep 10 00:26:39 UTC 2026