1 # frv testcase for mdaddaccs $ACC40Si,$ACC40Sk 2 # mach: fr400 3 4 .include "testutils.inc" 5 6 start 7 8 .global mdaddaccs 9 mdaddaccs: 10 set_accg_immed 0,accg0 11 set_acc_immed 0x00000000,acc0 12 set_accg_immed 0,accg1 13 set_acc_immed 0x00000000,acc1 14 set_accg_immed 0,accg2 15 set_acc_immed 0xdead0000,acc2 16 set_accg_immed 0,accg3 17 set_acc_immed 0x0000beef,acc3 18 mdaddaccs acc0,acc2 19 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 20 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 21 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 22 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 23 test_accg_immed 0,accg2 24 test_acc_limmed 0x0000,0x0000,acc2 25 test_accg_immed 0,accg3 26 test_acc_limmed 0xdead,0xbeef,acc3 27 28 set_accg_immed 0,accg0 29 set_acc_immed 0x0000dead,acc0 30 set_accg_immed 0,accg1 31 set_acc_immed 0xbeef0000,acc1 32 set_accg_immed 0,accg2 33 set_acc_immed 0x12345678,acc2 34 set_accg_immed 0,accg3 35 set_acc_immed 0x11111111,acc3 36 mdaddaccs acc0,acc2 37 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 38 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 39 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 40 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 41 test_accg_immed 0,accg2 42 test_acc_limmed 0xbeef,0xdead,acc2 43 test_accg_immed 0,accg3 44 test_acc_limmed 0x2345,0x6789,acc3 45 46 set_accg_immed 0,accg0 47 set_acc_immed 0x12345678,acc0 48 set_accg_immed 0,accg1 49 set_acc_immed 0xffffffff,acc1 50 set_accg_immed 0,accg2 51 set_acc_immed 0x12345678,acc2 52 set_accg_immed 0xff,accg3 53 set_acc_immed 0xffffffff,acc3 54 mdaddaccs acc0,acc2 55 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 56 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 57 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 58 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 59 test_accg_immed 1,accg2 60 test_acc_limmed 0x1234,0x5677,acc2 61 test_accg_immed 0,accg3 62 test_acc_limmed 0x1234,0x5677,acc3 63 64 set_spr_immed 0,msr0 65 set_accg_immed 0x7f,accg0 66 set_acc_immed 0xfffe7ffe,acc0 67 set_accg_immed 0x0,accg1 68 set_acc_immed 0x00020001,acc1 69 set_accg_immed 0x80,accg2 70 set_acc_immed 0x00000001,acc2 71 set_accg_immed 0xff,accg3 72 set_acc_immed 0xfffffffe,acc3 73 mdaddaccs acc0,acc2 74 test_spr_bits 0x3c,2,0xc,msr0 ; msr0.sie is set 75 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 76 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 77 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 78 test_accg_immed 0x7f,accg2 79 test_acc_limmed 0xffff,0xffff,acc2 80 test_accg_immed 0x80,accg3 81 test_acc_limmed 0x0000,0x0000,acc3 82 83 set_spr_immed 0,msr0 84 set_accg_immed 0,accg0 85 set_acc_immed 0x00000001,acc0 86 set_accg_immed 0,accg1 87 set_acc_immed 0x00000001,acc1 88 set_accg_immed 0,accg2 89 set_acc_immed 0x00000001,acc2 90 set_accg_immed 0x7f,accg3 91 set_acc_immed 0xffffffff,acc3 92 mdaddaccs acc0,acc2 93 test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie set 94 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 95 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 96 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 97 test_accg_immed 0,accg2 98 test_acc_limmed 0x0000,0x0002,acc2 99 test_accg_immed 0x7f,accg3 100 test_acc_limmed 0xffff,0xffff,acc3 101 102 pass 103
Indexes created Fri Jun 26 00:24:39 UTC 2026