1 # Hitachi H8 testcase 'and.l' 2 # mach(): h8300h h8300s h8sx 3 # as(h8300): --defsym sim_cpu=0 4 # as(h8300h): --defsym sim_cpu=1 5 # as(h8300s): --defsym sim_cpu=2 6 # as(h8sx): --defsym sim_cpu=3 7 # ld(h8300h): -m h8300helf 8 # ld(h8300s): -m h8300self 9 # ld(h8sx): -m h8300sxelf 10 11 .include "testutils.inc" 12 13 start 14 15 .if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx. 16 and_l_imm16: 17 set_grs_a5a5 ; Fill all general regs with a fixed pattern 18 ;; fixme set ccr 19 20 ;; and.l #xx:16,Rd 21 and.l #0xaaaa:16, er0 ; Immediate 16-bit operand 22 23 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 24 25 test_h_gr32 0x0000a0a0 er0 ; and result: a5a5a5a5 & aaaa 26 27 test_gr_a5a5 1 ; Make sure other general regs not disturbed 28 test_gr_a5a5 2 29 test_gr_a5a5 3 30 test_gr_a5a5 4 31 test_gr_a5a5 5 32 test_gr_a5a5 6 33 test_gr_a5a5 7 34 .endif 35 36 and_l_imm32: 37 set_grs_a5a5 ; Fill all general regs with a fixed pattern 38 ;; fixme set ccr 39 40 ;; and.l #xx:32,Rd 41 and.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand 42 43 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 44 45 test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa 46 47 test_gr_a5a5 1 ; Make sure other general regs not disturbed 48 test_gr_a5a5 2 49 test_gr_a5a5 3 50 test_gr_a5a5 4 51 test_gr_a5a5 5 52 test_gr_a5a5 6 53 test_gr_a5a5 7 54 55 and_l_reg: 56 set_grs_a5a5 ; Fill all general regs with a fixed pattern 57 ;; fixme set ccr 58 59 ;; and.l Rs,Rd 60 mov.l #0xaaaaaaaa, er1 61 and.l er1, er0 ; Register operand 62 63 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 64 65 test_h_gr32 0xa0a0a0a0 er0 ; and result: a5a5a5a5 & aaaaaaaa 66 test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged 67 68 test_gr_a5a5 2 ; Make sure other general regs not disturbed 69 test_gr_a5a5 3 70 test_gr_a5a5 4 71 test_gr_a5a5 5 72 test_gr_a5a5 6 73 test_gr_a5a5 7 74 75 pass 76 77 exit 0 78
Indexes created Sat Feb 28 05:31:39 UTC 2026