1 # Hitachi H8 testcase 'cmp.w' 2 # mach(): all 3 # as(h8300): --defsym sim_cpu=0 4 # as(h8300h): --defsym sim_cpu=1 5 # as(h8300s): --defsym sim_cpu=2 6 # as(h8sx): --defsym sim_cpu=3 7 # ld(h8300h): -m h8300helf 8 # ld(h8300s): -m h8300self 9 # ld(h8sx): -m h8300sxelf 10 11 .include "testutils.inc" 12 13 start 14 15 .if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx 16 cmp_w_imm3: ; 17 set_grs_a5a5 ; Fill all general regs with a fixed pattern 18 ;; fixme set ccr 19 20 ;; cmp.w #xx:3,Rd ; Immediate 3-bit operand 21 mov.w #5, r0 22 cmp.w #5, r0 23 beq eq3 24 fail 25 eq3: 26 cmp.w #6, r0 27 blt lt3 28 fail 29 lt3: 30 cmp.w #4, r0 31 bgt gt3 32 fail 33 gt3: 34 35 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 36 test_h_gr32 0xa5a50005 er0 ; er0 unchanged 37 test_gr_a5a5 1 ; Make sure other general regs not disturbed 38 test_gr_a5a5 2 39 test_gr_a5a5 3 40 test_gr_a5a5 4 41 test_gr_a5a5 5 42 test_gr_a5a5 6 43 test_gr_a5a5 7 44 .endif 45 46 .if (sim_cpu) ; non-zero means h8300h, s, or sx 47 cmp_w_imm16: ; cmp.w immediate not available in h8300 mode. 48 set_grs_a5a5 ; Fill all general regs with a fixed pattern 49 ;; fixme set ccr 50 51 ;; cmp.w #xx:16,Rd 52 cmp.w #0xa5a5, r0 ; Immediate 16-bit operand 53 beq eqi 54 fail 55 eqi: cmp.w #0xa5a6, r0 56 blt lti 57 fail 58 lti: cmp.w #0xa5a4, r0 59 bgt gti 60 fail 61 gti: 62 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 63 test_h_gr16 0xa5a5 r0 ; r0 unchanged 64 .if (sim_cpu) ; non-zero means h8300h, s, or sx 65 test_h_gr32 0xa5a5a5a5 er0 ; er0 unchanged 66 .endif 67 test_gr_a5a5 1 ; Make sure other general regs not disturbed 68 test_gr_a5a5 2 69 test_gr_a5a5 3 70 test_gr_a5a5 4 71 test_gr_a5a5 5 72 test_gr_a5a5 6 73 test_gr_a5a5 7 74 75 cmp_w_imm16_less_than_zero: ; Test for less-than-zero immediate 76 set_grs_a5a5 77 ;; cmp.w #xx:16, Rd, where #xx < 0 (ie. #xx > 0x7fff). 78 sub.w r0, r0 79 cmp.w #0x8001, r0 80 bls ltz 81 fail 82 ltz: test_gr_a5a5 1 83 test_gr_a5a5 2 84 test_gr_a5a5 3 85 test_gr_a5a5 4 86 test_gr_a5a5 5 87 test_gr_a5a5 6 88 test_gr_a5a5 7 89 90 .endif 91 92 cmp_w_reg: 93 set_grs_a5a5 ; Fill all general regs with a fixed pattern 94 ;; fixme set ccr 95 96 ;; cmp.w Rs,Rd 97 mov.w #0xa5a5, r1 98 cmp.w r1, r0 ; Register operand 99 beq eqr 100 fail 101 eqr: mov.w #0xa5a6, r1 102 cmp.w r1, r0 103 blt ltr 104 fail 105 ltr: mov.w #0xa5a4, r1 106 cmp.w r1, r0 107 bgt gtr 108 fail 109 gtr: 110 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 111 test_h_gr16 0xa5a5 r0 ; r0 unchanged. 112 test_h_gr16 0xa5a4 r1 ; r1 unchanged. 113 .if (sim_cpu) ; non-zero means h8300h, s, or sx 114 test_h_gr32 0xa5a5a5a5 er0 ; r0 unchanged 115 test_h_gr32 0xa5a5a5a4 er1 ; r1 unchanged 116 .endif 117 test_gr_a5a5 2 ; Make sure other general regs not disturbed 118 test_gr_a5a5 3 119 test_gr_a5a5 4 120 test_gr_a5a5 5 121 test_gr_a5a5 6 122 test_gr_a5a5 7 123 124 pass 125 126 exit 0 127
Indexes created Sat Feb 28 05:31:39 UTC 2026