1 # Hitachi H8 testcase 'inc, inc.w, inc.l' 2 # mach(): all 3 # as(h8300): --defsym sim_cpu=0 4 # as(h8300h): --defsym sim_cpu=1 5 # as(h8300s): --defsym sim_cpu=2 6 # as(h8sx): --defsym sim_cpu=3 7 # ld(h8300h): -m h8300helf 8 # ld(h8300s): -m h8300self 9 # ld(h8sx): -m h8300sxelf 10 11 .include "testutils.inc" 12 13 start 14 15 inc_b: 16 set_grs_a5a5 ; Fill all general regs with a fixed pattern 17 ;; fixme set ccr 18 19 ;; inc.b Rd 20 inc.b r0h ; Increment 8-bit reg by one 21 22 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 23 test_h_gr16 0xa6a5 r0 ; inc result: a6|a5 24 .if (sim_cpu) ; non-zero means h8300h, s, or sx 25 test_h_gr32 0xa5a5a6a5 er0 ; inc result: a5|a5|a6|a5 26 .endif 27 test_gr_a5a5 1 ; Make sure other general regs not disturbed 28 test_gr_a5a5 2 29 test_gr_a5a5 3 30 test_gr_a5a5 4 31 test_gr_a5a5 5 32 test_gr_a5a5 6 33 test_gr_a5a5 7 34 35 .if (sim_cpu) ; non-zero means h8300h, s, or sx 36 inc_w_1: 37 set_grs_a5a5 ; Fill all general regs with a fixed pattern 38 ;; fixme set ccr 39 40 ;; inc.w #1, Rd 41 inc.w #1, r0 ; Increment 16-bit reg by one 42 43 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 44 test_h_gr16 0xa5a6 r0 ; inc result: a5|a6 45 46 test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6 47 48 test_gr_a5a5 1 ; Make sure other general regs not disturbed 49 test_gr_a5a5 2 50 test_gr_a5a5 3 51 test_gr_a5a5 4 52 test_gr_a5a5 5 53 test_gr_a5a5 6 54 test_gr_a5a5 7 55 56 inc_w_2: 57 set_grs_a5a5 ; Fill all general regs with a fixed pattern 58 ;; fixme set ccr 59 60 ;; inc.w #2, Rd 61 inc.w #2, r0 ; Increment 16-bit reg by two 62 63 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 64 test_h_gr16 0xa5a7 r0 ; inc result: a5|a7 65 66 test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7 67 68 test_gr_a5a5 1 ; Make sure other general regs not disturbed 69 test_gr_a5a5 2 70 test_gr_a5a5 3 71 test_gr_a5a5 4 72 test_gr_a5a5 5 73 test_gr_a5a5 6 74 test_gr_a5a5 7 75 76 inc_l_1: 77 set_grs_a5a5 ; Fill all general regs with a fixed pattern 78 ;; fixme set ccr 79 80 ;; inc.l #1, eRd 81 inc.l #1, er0 ; Increment 32-bit reg by one 82 83 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 84 85 test_h_gr32 0xa5a5a5a6 er0 ; inc result: a5|a5|a5|a6 86 87 test_gr_a5a5 1 ; Make sure other general regs not disturbed 88 test_gr_a5a5 2 89 test_gr_a5a5 3 90 test_gr_a5a5 4 91 test_gr_a5a5 5 92 test_gr_a5a5 6 93 test_gr_a5a5 7 94 95 inc_l_2: 96 set_grs_a5a5 ; Fill all general regs with a fixed pattern 97 ;; fixme set ccr 98 99 ;; inc.l #2, eRd 100 inc.l #2, er0 ; Increment 32-bit reg by two 101 102 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 103 104 test_h_gr32 0xa5a5a5a7 er0 ; inc result: a5|a5|a5|a7 105 106 test_gr_a5a5 1 ; Make sure other general regs not disturbed 107 test_gr_a5a5 2 108 test_gr_a5a5 3 109 test_gr_a5a5 4 110 test_gr_a5a5 5 111 test_gr_a5a5 6 112 test_gr_a5a5 7 113 .endif 114 115 pass 116 117 exit 0 118
Indexes created Sat Feb 28 05:31:39 UTC 2026