1 # Hitachi H8 testcase 'neg.b, neg.w, neg.l' 2 # mach(): all 3 # as(h8300): --defsym sim_cpu=0 4 # as(h8300h): --defsym sim_cpu=1 5 # as(h8300s): --defsym sim_cpu=2 6 # as(h8sx): --defsym sim_cpu=3 7 # ld(h8300h): -m h8300helf 8 # ld(h8300s): -m h8300self 9 # ld(h8sx): -m h8300sxelf 10 11 .include "testutils.inc" 12 13 # Instructions tested: 14 # neg.b rd ; 1 7 8 rd 15 # neg.b @erd ; 7 d rd ???? 1 7 8 ignore 16 # neg.b @erd+ ; 0 1 7 4 6 c rd 1??? 1 7 8 ignore 17 # neg.b @erd- ; 0 1 7 6 6 c rd 1??? 1 7 8 ignore 18 # neg.b @+erd ; 0 1 7 5 6 c rd 1??? 1 7 8 ignore 19 # neg.b @-erd ; 0 1 7 7 6 c rd 1??? 1 7 8 ignore 20 # neg.b @(d:2, erd) ; 0 1 7 01dd 6 8 rd 8 1 7 8 ignore 21 # neg.b @(d:16, erd) ; 0 1 7 4 6 e rd 1??? dd:16 1 7 8 ignore 22 # neg.b @(d:32, erd) ; 7 8 rd 4 6 a 2 1??? dd:32 1 7 8 ignore 23 # neg.b @aa:16 ; 6 a 1 1??? aa:16 1 7 8 ignore 24 # neg.b @aa:32 ; 6 a 3 1??? aa:32 1 7 8 ignore 25 # word operations 26 # long operations 27 # 28 # Coming soon: 29 # neg.b @aa:8 ; 7 f aaaaaaaa 1 7 8 ignore 30 # 31 32 .data 33 byte_dest: .byte 0xa5 34 .align 2 35 word_dest: .word 0xa5a5 36 .align 4 37 long_dest: .long 0xa5a5a5a5 38 start 39 40 # 41 # Note: apparently carry is set for neg of anything except zero. 42 # 43 44 # 45 # 8-bit byte operations 46 # 47 48 neg_b_reg8: 49 set_grs_a5a5 ; Fill all general regs with a fixed pattern 50 set_ccr_zero 51 52 ;; neg.b Rd 53 neg r0l ; 8-bit register 54 ;;; .word 0x1788 55 56 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 57 test_ovf_clear 58 test_zero_clear 59 test_neg_clear 60 61 cmp.b #0x5b, r0l ; result of "neg 0xa5" 62 beq .Lbrd 63 fail 64 .Lbrd: 65 test_h_gr16 0xa55b r0 ; r0 changed by 'neg' 66 .if (sim_cpu) ; non-zero means h8300h, s, or sx 67 test_h_gr32 0xa5a5a55b er0 ; er0 changed by 'neg' 68 .endif 69 test_gr_a5a5 1 ; Make sure other general regs not disturbed 70 test_gr_a5a5 2 71 test_gr_a5a5 3 72 test_gr_a5a5 4 73 test_gr_a5a5 5 74 test_gr_a5a5 6 75 test_gr_a5a5 7 76 77 .if (sim_cpu == h8sx) 78 neg_b_rdind: 79 set_grs_a5a5 ; Fill all general regs with a fixed pattern 80 set_ccr_zero 81 82 ;; neg.b @eRd 83 mov #byte_dest, er0 84 neg.b @er0 ; register indirect operand 85 ;;; .word 0x7d00 86 ;;; .word 0x1780 87 88 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 89 test_ovf_clear 90 test_zero_clear 91 test_neg_clear 92 93 test_h_gr32 byte_dest er0 ; er0 still contains address 94 cmp.b #0x5b, @er0 ; memory contents changed 95 beq .Lbind 96 fail 97 .Lbind: 98 test_gr_a5a5 1 ; Make sure other general regs not disturbed 99 test_gr_a5a5 2 100 test_gr_a5a5 3 101 test_gr_a5a5 4 102 test_gr_a5a5 5 103 test_gr_a5a5 6 104 test_gr_a5a5 7 105 106 neg_b_rdpostinc: 107 set_grs_a5a5 ; Fill all general regs with a fixed pattern 108 set_ccr_zero 109 110 ;; neg.b @eRd+ 111 mov #byte_dest, er0 ; register post-increment operand 112 neg.b @er0+ 113 ;;; .word 0x0174 114 ;;; .word 0x6c08 115 ;;; .word 0x1780 116 117 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 118 test_ovf_clear 119 test_zero_clear 120 test_neg_set 121 122 test_h_gr32 byte_dest+1 er0 ; er0 contains address plus one 123 cmp.b #0xa5, @-er0 124 beq .Lbpostinc 125 fail 126 .Lbpostinc: 127 test_gr_a5a5 1 ; Make sure other general regs not disturbed 128 test_gr_a5a5 2 129 test_gr_a5a5 3 130 test_gr_a5a5 4 131 test_gr_a5a5 5 132 test_gr_a5a5 6 133 test_gr_a5a5 7 134 135 neg_b_rdpostdec: 136 set_grs_a5a5 ; Fill all general regs with a fixed pattern 137 set_ccr_zero 138 139 ;; neg.b @eRd- 140 mov #byte_dest, er0 ; register post-decrement operand 141 neg.b @er0- 142 ;;; .word 0x0176 143 ;;; .word 0x6c08 144 ;;; .word 0x1780 145 146 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 147 test_ovf_clear 148 test_zero_clear 149 test_neg_clear 150 151 test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one 152 cmp.b #0x5b, @+er0 153 beq .Lbpostdec 154 fail 155 .Lbpostdec: 156 test_gr_a5a5 1 ; Make sure other general regs not disturbed 157 test_gr_a5a5 2 158 test_gr_a5a5 3 159 test_gr_a5a5 4 160 test_gr_a5a5 5 161 test_gr_a5a5 6 162 test_gr_a5a5 7 163 164 neg_b_rdpreinc: 165 set_grs_a5a5 ; Fill all general regs with a fixed pattern 166 set_ccr_zero 167 168 ;; neg.b @+eRd 169 mov #byte_dest-1, er0 170 neg.b @+er0 ; reg pre-increment operand 171 ;;; .word 0x0175 172 ;;; .word 0x6c08 173 ;;; .word 0x1780 174 175 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 176 test_ovf_clear 177 test_zero_clear 178 test_neg_set 179 180 cmp.b #0xa5, @er0 181 beq .Lbpreinc 182 fail 183 .Lbpreinc: 184 test_h_gr32 byte_dest er0 ; er0 contains destination address 185 test_gr_a5a5 1 ; Make sure other general regs not disturbed 186 test_gr_a5a5 2 187 test_gr_a5a5 3 188 test_gr_a5a5 4 189 test_gr_a5a5 5 190 test_gr_a5a5 6 191 test_gr_a5a5 7 192 193 neg_b_rdpredec: 194 set_grs_a5a5 ; Fill all general regs with a fixed pattern 195 set_ccr_zero 196 197 ;; neg.b @-eRd 198 mov #byte_dest+1, er0 199 neg.b @-er0 ; reg pre-decr operand 200 ;;; .word 0x0177 201 ;;; .word 0x6c08 202 ;;; .word 0x1780 203 204 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 205 test_ovf_clear 206 test_zero_clear 207 test_neg_clear 208 209 cmp.b #0x5b, @er0 210 beq .Lbpredec 211 fail 212 .Lbpredec: 213 test_h_gr32 byte_dest er0 ; er0 contains destination address 214 test_gr_a5a5 1 ; Make sure other general regs not disturbed 215 test_gr_a5a5 2 216 test_gr_a5a5 3 217 test_gr_a5a5 4 218 test_gr_a5a5 5 219 test_gr_a5a5 6 220 test_gr_a5a5 7 221 222 neg_b_disp2dst: 223 set_grs_a5a5 ; Fill all general regs with a fixed pattern 224 set_ccr_zero 225 226 ;; neg.b @(dd:2, erd) 227 mov #byte_dest-1, er0 228 neg.b @(1:2, er0) ; reg plus 2-bit displacement 229 ;;; .word 0x0175 230 ;;; .word 0x6808 231 ;;; .word 0x1780 232 233 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 234 test_ovf_clear 235 test_zero_clear 236 test_neg_set 237 238 cmp.b #0xa5, @+er0 239 beq .Lbdisp2 240 fail 241 .Lbdisp2: 242 test_h_gr32 byte_dest er0 ; er0 contains destination address 243 test_gr_a5a5 1 ; Make sure other general regs not disturbed 244 test_gr_a5a5 2 245 test_gr_a5a5 3 246 test_gr_a5a5 4 247 test_gr_a5a5 5 248 test_gr_a5a5 6 249 test_gr_a5a5 7 250 251 neg_b_disp16dst: 252 set_grs_a5a5 ; Fill all general regs with a fixed pattern 253 set_ccr_zero 254 255 ;; neg.b @(dd:16, erd) 256 mov #byte_dest+100, er0 257 neg.b @(-100:16, er0) ; reg plus 16-bit displacement 258 ;;; .word 0x0174 259 ;;; .word 0x6e08 260 ;;; .word -100 261 ;;; .word 0x1780 262 263 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 264 test_ovf_clear 265 test_zero_clear 266 test_neg_clear 267 268 cmp.b #0x5b, @byte_dest 269 beq .Lbdisp16 270 fail 271 .Lbdisp16: 272 test_h_gr32 byte_dest+100 er0 ; er0 contains destination address 273 test_gr_a5a5 1 ; Make sure other general regs not disturbed 274 test_gr_a5a5 2 275 test_gr_a5a5 3 276 test_gr_a5a5 4 277 test_gr_a5a5 5 278 test_gr_a5a5 6 279 test_gr_a5a5 7 280 281 neg_b_disp32dst: 282 set_grs_a5a5 ; Fill all general regs with a fixed pattern 283 set_ccr_zero 284 285 ;; neg.b @(dd:32, erd) 286 mov #byte_dest-0xfffff, er0 287 neg.b @(0xfffff:32, er0) ; reg plus 32-bit displacement 288 ;;; .word 0x7804 289 ;;; .word 0x6a28 290 ;;; .long 0xfffff 291 ;;; .word 0x1780 292 293 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 294 test_ovf_clear 295 test_zero_clear 296 test_neg_set 297 298 cmp.b #0xa5, @byte_dest 299 beq .Lbdisp32 300 fail 301 .Lbdisp32: 302 test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address 303 test_gr_a5a5 1 ; Make sure other general regs not disturbed 304 test_gr_a5a5 2 305 test_gr_a5a5 3 306 test_gr_a5a5 4 307 test_gr_a5a5 5 308 test_gr_a5a5 6 309 test_gr_a5a5 7 310 311 neg_b_abs16dst: 312 set_grs_a5a5 ; Fill all general regs with a fixed pattern 313 set_ccr_zero 314 315 ;; neg.b @aa:16 316 neg.b @byte_dest:16 ; 16-bit absolute address 317 ;;; .word 0x6a18 318 ;;; .word byte_dest 319 ;;; .word 0x1780 320 321 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 322 test_ovf_clear 323 test_zero_clear 324 test_neg_clear 325 326 cmp.b #0x5b, @byte_dest 327 beq .Lbabs16 328 fail 329 .Lbabs16: 330 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 331 test_gr_a5a5 1 332 test_gr_a5a5 2 333 test_gr_a5a5 3 334 test_gr_a5a5 4 335 test_gr_a5a5 5 336 test_gr_a5a5 6 337 test_gr_a5a5 7 338 339 neg_b_abs32dst: 340 set_grs_a5a5 ; Fill all general regs with a fixed pattern 341 set_ccr_zero 342 343 ;; neg.b @aa:32 344 neg.b @byte_dest:32 ; 32-bit absolute address 345 ;;; .word 0x6a38 346 ;;; .long byte_dest 347 ;;; .word 0x1780 348 349 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 350 test_ovf_clear 351 test_zero_clear 352 test_neg_set 353 354 cmp.b #0xa5, @byte_dest 355 beq .Lbabs32 356 fail 357 .Lbabs32: 358 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 359 test_gr_a5a5 1 360 test_gr_a5a5 2 361 test_gr_a5a5 3 362 test_gr_a5a5 4 363 test_gr_a5a5 5 364 test_gr_a5a5 6 365 test_gr_a5a5 7 366 .endif 367 368 # 369 # 16-bit word operations 370 # 371 372 .if (sim_cpu) ; any except plain-vanilla h8/300 373 neg_w_reg16: 374 set_grs_a5a5 ; Fill all general regs with a fixed pattern 375 set_ccr_zero 376 377 ;; neg.w Rd 378 neg r1 ; 16-bit register operand 379 ;;; .word 0x1791 380 381 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 382 test_ovf_clear 383 test_zero_clear 384 test_neg_clear 385 386 cmp.w #0x5a5b, r1 ; result of "neg 0xa5a5" 387 beq .Lwrd 388 fail 389 .Lwrd: 390 test_h_gr32 0xa5a55a5b er1 ; er1 changed by 'neg' 391 test_gr_a5a5 0 ; Make sure other general regs not disturbed 392 test_gr_a5a5 2 393 test_gr_a5a5 3 394 test_gr_a5a5 4 395 test_gr_a5a5 5 396 test_gr_a5a5 6 397 test_gr_a5a5 7 398 399 .if (sim_cpu == h8sx) 400 neg_w_rdind: 401 set_grs_a5a5 ; Fill all general regs with a fixed pattern 402 set_ccr_zero 403 404 ;; neg.w @eRd 405 mov #word_dest, er1 406 neg.w @er1 ; register indirect operand 407 ;;; .word 0x0154 408 ;;; .word 0x6d18 409 ;;; .word 0x1790 410 411 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 412 test_ovf_clear 413 test_zero_clear 414 test_neg_clear 415 416 cmp.w #0x5a5b, @word_dest ; memory contents changed 417 beq .Lwind 418 fail 419 .Lwind: 420 test_h_gr32 word_dest er1 ; er1 still contains address 421 test_gr_a5a5 0 ; Make sure other general regs not disturbed 422 test_gr_a5a5 2 423 test_gr_a5a5 3 424 test_gr_a5a5 4 425 test_gr_a5a5 5 426 test_gr_a5a5 6 427 test_gr_a5a5 7 428 429 neg_w_rdpostinc: 430 set_grs_a5a5 ; Fill all general regs with a fixed pattern 431 set_ccr_zero 432 433 ;; neg.w @eRd+ 434 mov #word_dest, er1 ; register post-increment operand 435 neg.w @er1+ 436 ;;; .word 0x0154 437 ;;; .word 0x6d18 438 ;;; .word 0x1790 439 440 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 441 test_ovf_clear 442 test_zero_clear 443 test_neg_set 444 445 cmp.w #0xa5a5, @word_dest 446 beq .Lwpostinc 447 fail 448 .Lwpostinc: 449 test_h_gr32 word_dest+2 er1 ; er1 contains address plus two 450 test_gr_a5a5 0 ; Make sure other general regs not disturbed 451 test_gr_a5a5 2 452 test_gr_a5a5 3 453 test_gr_a5a5 4 454 test_gr_a5a5 5 455 test_gr_a5a5 6 456 test_gr_a5a5 7 457 458 neg_w_rdpostdec: 459 set_grs_a5a5 ; Fill all general regs with a fixed pattern 460 set_ccr_zero 461 462 ;; neg.w @eRd- 463 mov #word_dest, er1 464 neg.w @er1- 465 ;;; .word 0x0156 466 ;;; .word 0x6d18 467 ;;; .word 0x1790 468 469 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 470 test_ovf_clear 471 test_zero_clear 472 test_neg_clear 473 474 cmp.w #0x5a5b, @word_dest 475 beq .Lwpostdec 476 fail 477 .Lwpostdec: 478 test_h_gr32 word_dest-2 er1 ; er1 contains address minus two 479 test_gr_a5a5 0 ; Make sure other general regs not disturbed 480 test_gr_a5a5 2 481 test_gr_a5a5 3 482 test_gr_a5a5 4 483 test_gr_a5a5 5 484 test_gr_a5a5 6 485 test_gr_a5a5 7 486 487 neg_w_rdpreinc: 488 set_grs_a5a5 ; Fill all general regs with a fixed pattern 489 set_ccr_zero 490 491 ;; neg.w @+eRd 492 mov #word_dest-2, er1 493 neg.w @+er1 ; reg pre-increment operand 494 ;;; .word 0x0155 495 ;;; .word 0x6d18 496 ;;; .word 0x1790 497 498 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 499 test_ovf_clear 500 test_zero_clear 501 test_neg_set 502 503 cmp.w #0xa5a5, @word_dest 504 beq .Lwpreinc 505 fail 506 .Lwpreinc: 507 test_h_gr32 word_dest er1 ; er1 contains destination address 508 test_gr_a5a5 0 ; Make sure other general regs not disturbed 509 test_gr_a5a5 2 510 test_gr_a5a5 3 511 test_gr_a5a5 4 512 test_gr_a5a5 5 513 test_gr_a5a5 6 514 test_gr_a5a5 7 515 516 neg_w_rdpredec: 517 set_grs_a5a5 ; Fill all general regs with a fixed pattern 518 set_ccr_zero 519 520 ;; neg.w @-eRd 521 mov #word_dest+2, er1 522 neg.w @-er1 ; reg pre-decr operand 523 ;;; .word 0x0157 524 ;;; .word 0x6d18 525 ;;; .word 0x1790 526 527 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 528 test_ovf_clear 529 test_zero_clear 530 test_neg_clear 531 532 cmp.w #0x5a5b, @word_dest 533 beq .Lwpredec 534 fail 535 .Lwpredec: 536 test_h_gr32 word_dest er1 ; er1 contains destination address 537 test_gr_a5a5 0 ; Make sure other general regs not disturbed 538 test_gr_a5a5 2 539 test_gr_a5a5 3 540 test_gr_a5a5 4 541 test_gr_a5a5 5 542 test_gr_a5a5 6 543 test_gr_a5a5 7 544 545 neg_w_disp2dst: 546 set_grs_a5a5 ; Fill all general regs with a fixed pattern 547 set_ccr_zero 548 549 ;; neg.w @(dd:2, erd) 550 mov #word_dest-2, er1 551 neg.w @(2:2, er1) ; reg plus 2-bit displacement 552 ;;; .word 0x0155 553 ;;; .word 0x6918 554 ;;; .word 0x1790 555 556 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 557 test_ovf_clear 558 test_zero_clear 559 test_neg_set 560 561 cmp.w #0xa5a5, @word_dest 562 beq .Lwdisp2 563 fail 564 .Lwdisp2: 565 test_h_gr32 word_dest-2 er1 ; er1 contains address minus one 566 test_gr_a5a5 0 ; Make sure other general regs not disturbed 567 test_gr_a5a5 2 568 test_gr_a5a5 3 569 test_gr_a5a5 4 570 test_gr_a5a5 5 571 test_gr_a5a5 6 572 test_gr_a5a5 7 573 574 neg_w_disp16dst: 575 set_grs_a5a5 ; Fill all general regs with a fixed pattern 576 set_ccr_zero 577 578 ;; neg.w @(dd:16, erd) 579 mov #word_dest+100, er1 580 neg.w @(-100:16, er1) ; reg plus 16-bit displacement 581 ;;; .word 0x0154 582 ;;; .word 0x6f18 583 ;;; .word -100 584 ;;; .word 0x1790 585 586 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 587 test_ovf_clear 588 test_zero_clear 589 test_neg_clear 590 591 cmp.w #0x5a5b, @word_dest 592 beq .Lwdisp16 593 fail 594 .Lwdisp16: 595 test_h_gr32 word_dest+100 er1 ; er1 contains destination address 596 test_gr_a5a5 0 ; Make sure other general regs not disturbed 597 test_gr_a5a5 2 598 test_gr_a5a5 3 599 test_gr_a5a5 4 600 test_gr_a5a5 5 601 test_gr_a5a5 6 602 test_gr_a5a5 7 603 604 neg_w_disp32dst: 605 set_grs_a5a5 ; Fill all general regs with a fixed pattern 606 set_ccr_zero 607 608 ;; neg.w @(dd:32, erd) 609 mov #word_dest-0xfffff, er1 610 neg.w @(0xfffff:32, er1) ; reg plus 32-bit displacement 611 ;;; .word 0x7814 612 ;;; .word 0x6b28 613 ;;; .long 0xfffff 614 ;;; .word 0x1790 615 616 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 617 test_ovf_clear 618 test_zero_clear 619 test_neg_set 620 621 cmp.w #0xa5a5, @word_dest 622 beq .Lwdisp32 623 fail 624 .Lwdisp32: 625 test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address 626 test_gr_a5a5 0 ; Make sure other general regs not disturbed 627 test_gr_a5a5 2 628 test_gr_a5a5 3 629 test_gr_a5a5 4 630 test_gr_a5a5 5 631 test_gr_a5a5 6 632 test_gr_a5a5 7 633 634 neg_w_abs16dst: 635 set_grs_a5a5 ; Fill all general regs with a fixed pattern 636 set_ccr_zero 637 638 ;; neg.w @aa:16 639 neg.w @word_dest:16 ; 16-bit absolute address 640 ;;; .word 0x6b18 641 ;;; .word word_dest 642 ;;; .word 0x1790 643 644 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 645 test_ovf_clear 646 test_zero_clear 647 test_neg_clear 648 649 cmp.w #0x5a5b, @word_dest 650 beq .Lwabs16 651 fail 652 .Lwabs16: 653 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 654 test_gr_a5a5 1 655 test_gr_a5a5 2 656 test_gr_a5a5 3 657 test_gr_a5a5 4 658 test_gr_a5a5 5 659 test_gr_a5a5 6 660 test_gr_a5a5 7 661 662 neg_w_abs32dst: 663 set_grs_a5a5 ; Fill all general regs with a fixed pattern 664 set_ccr_zero 665 666 ;; neg.w @aa:32 667 neg.w @word_dest:32 ; 32-bit absolute address 668 ;;; .word 0x6b38 669 ;;; .long word_dest 670 ;;; .word 0x1790 671 672 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 673 test_ovf_clear 674 test_zero_clear 675 test_neg_set 676 677 cmp.w #0xa5a5, @word_dest 678 beq .Lwabs32 679 fail 680 .Lwabs32: 681 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 682 test_gr_a5a5 1 683 test_gr_a5a5 2 684 test_gr_a5a5 3 685 test_gr_a5a5 4 686 test_gr_a5a5 5 687 test_gr_a5a5 6 688 test_gr_a5a5 7 689 690 .endif ; h8sx 691 .endif ; h8/300 692 693 # 694 # 32-bit word operations 695 # 696 697 .if (sim_cpu) ; any except plain-vanilla h8/300 698 neg_l_reg16: 699 set_grs_a5a5 ; Fill all general regs with a fixed pattern 700 set_ccr_zero 701 702 ;; neg.l eRd 703 neg er1 ; 32-bit register operand 704 ;;; .word 0x17b1 705 706 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 707 test_ovf_clear 708 test_zero_clear 709 test_neg_clear 710 711 cmp.l #0x5a5a5a5b, er1 ; result of "neg 0xa5a5a5a5" 712 beq .Llrd 713 fail 714 .Llrd: 715 test_h_gr32 0x5a5a5a5b er1 ; er1 changed by 'neg' 716 test_gr_a5a5 0 ; Make sure other general regs not disturbed 717 test_gr_a5a5 2 718 test_gr_a5a5 3 719 test_gr_a5a5 4 720 test_gr_a5a5 5 721 test_gr_a5a5 6 722 test_gr_a5a5 7 723 724 .if (sim_cpu == h8sx) 725 neg_l_rdind: 726 set_grs_a5a5 ; Fill all general regs with a fixed pattern 727 set_ccr_zero 728 729 ;; neg.l @eRd 730 mov #long_dest, er1 731 neg.l @er1 ; register indirect operand 732 ;;; .word 0x0104 733 ;;; .word 0x6d18 734 ;;; .word 0x17b0 735 736 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 737 test_ovf_clear 738 test_zero_clear 739 test_neg_clear 740 741 cmp.l #0x5a5a5a5b, @long_dest ; memory contents changed 742 beq .Llind 743 fail 744 .Llind: 745 test_h_gr32 long_dest er1 ; er1 still contains address 746 test_gr_a5a5 0 ; Make sure other general regs not disturbed 747 test_gr_a5a5 2 748 test_gr_a5a5 3 749 test_gr_a5a5 4 750 test_gr_a5a5 5 751 test_gr_a5a5 6 752 test_gr_a5a5 7 753 754 neg_l_rdpostinc: 755 set_grs_a5a5 ; Fill all general regs with a fixed pattern 756 set_ccr_zero 757 758 ;; neg.l @eRd+ 759 mov #long_dest, er1 ; register post-increment operand 760 neg.l @er1+ 761 ;;; .word 0x0104 762 ;;; .word 0x6d18 763 ;;; .word 0x17b0 764 765 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 766 test_ovf_clear 767 test_zero_clear 768 test_neg_set 769 770 cmp.l #0xa5a5a5a5, @long_dest 771 beq .Llpostinc 772 fail 773 .Llpostinc: 774 test_h_gr32 long_dest+4 er1 ; er1 contains address plus two 775 test_gr_a5a5 0 ; Make sure other general regs not disturbed 776 test_gr_a5a5 2 777 test_gr_a5a5 3 778 test_gr_a5a5 4 779 test_gr_a5a5 5 780 test_gr_a5a5 6 781 test_gr_a5a5 7 782 783 neg_l_rdpostdec: 784 set_grs_a5a5 ; Fill all general regs with a fixed pattern 785 set_ccr_zero 786 787 ;; neg.l @eRd- 788 mov #long_dest, er1 789 neg.l @er1- 790 ;;; .word 0x0106 791 ;;; .word 0x6d18 792 ;;; .word 0x17b0 793 794 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 795 test_ovf_clear 796 test_zero_clear 797 test_neg_clear 798 799 cmp.l #0x5a5a5a5b, @long_dest 800 beq .Llpostdec 801 fail 802 .Llpostdec: 803 test_h_gr32 long_dest-4 er1 ; er1 contains address minus two 804 test_gr_a5a5 0 ; Make sure other general regs not disturbed 805 test_gr_a5a5 2 806 test_gr_a5a5 3 807 test_gr_a5a5 4 808 test_gr_a5a5 5 809 test_gr_a5a5 6 810 test_gr_a5a5 7 811 812 neg_l_rdpreinc: 813 set_grs_a5a5 ; Fill all general regs with a fixed pattern 814 set_ccr_zero 815 816 ;; neg.l @+eRd 817 mov #long_dest-4, er1 818 neg.l @+er1 ; reg pre-increment operand 819 ;;; .word 0x0105 820 ;;; .word 0x6d18 821 ;;; .word 0x17b0 822 823 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 824 test_ovf_clear 825 test_zero_clear 826 test_neg_set 827 828 cmp.l #0xa5a5a5a5, @long_dest 829 beq .Llpreinc 830 fail 831 .Llpreinc: 832 test_h_gr32 long_dest er1 ; er1 contains destination address 833 test_gr_a5a5 0 ; Make sure other general regs not disturbed 834 test_gr_a5a5 2 835 test_gr_a5a5 3 836 test_gr_a5a5 4 837 test_gr_a5a5 5 838 test_gr_a5a5 6 839 test_gr_a5a5 7 840 841 neg_l_rdpredec: 842 set_grs_a5a5 ; Fill all general regs with a fixed pattern 843 set_ccr_zero 844 845 ;; neg.l @-eRd 846 mov #long_dest+4, er1 847 neg.l @-er1 ; reg pre-decr operand 848 ;;; .word 0x0107 849 ;;; .word 0x6d18 850 ;;; .word 0x17b0 851 852 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 853 test_ovf_clear 854 test_zero_clear 855 test_neg_clear 856 857 cmp.l #0x5a5a5a5b, @long_dest 858 beq .Llpredec 859 fail 860 .Llpredec: 861 test_h_gr32 long_dest er1 ; er1 contains destination address 862 test_gr_a5a5 0 ; Make sure other general regs not disturbed 863 test_gr_a5a5 2 864 test_gr_a5a5 3 865 test_gr_a5a5 4 866 test_gr_a5a5 5 867 test_gr_a5a5 6 868 test_gr_a5a5 7 869 870 neg_l_disp2dst: 871 set_grs_a5a5 ; Fill all general regs with a fixed pattern 872 set_ccr_zero 873 874 ;; neg.l @(dd:2, erd) 875 mov #long_dest-4, er1 876 neg.l @(4:2, er1) ; reg plus 2-bit displacement 877 ;;; .word 0x0105 878 ;;; .word 0x6918 879 ;;; .word 0x17b0 880 881 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 882 test_ovf_clear 883 test_zero_clear 884 test_neg_set 885 886 cmp.l #0xa5a5a5a5, @long_dest 887 beq .Lldisp2 888 fail 889 .Lldisp2: 890 test_h_gr32 long_dest-4 er1 ; er1 contains address minus one 891 test_gr_a5a5 0 ; Make sure other general regs not disturbed 892 test_gr_a5a5 2 893 test_gr_a5a5 3 894 test_gr_a5a5 4 895 test_gr_a5a5 5 896 test_gr_a5a5 6 897 test_gr_a5a5 7 898 899 neg_l_disp16dst: 900 set_grs_a5a5 ; Fill all general regs with a fixed pattern 901 set_ccr_zero 902 903 ;; neg.l @(dd:16, erd) 904 mov #long_dest+100, er1 905 neg.l @(-100:16, er1) ; reg plus 16-bit displacement 906 ;;; .word 0x0104 907 ;;; .word 0x6f18 908 ;;; .word -100 909 ;;; .word 0x17b0 910 911 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 912 test_ovf_clear 913 test_zero_clear 914 test_neg_clear 915 916 cmp.l #0x5a5a5a5b, @long_dest 917 beq .Lldisp16 918 fail 919 .Lldisp16: 920 test_h_gr32 long_dest+100 er1 ; er1 contains destination address 921 test_gr_a5a5 0 ; Make sure other general regs not disturbed 922 test_gr_a5a5 2 923 test_gr_a5a5 3 924 test_gr_a5a5 4 925 test_gr_a5a5 5 926 test_gr_a5a5 6 927 test_gr_a5a5 7 928 929 neg_l_disp32dst: 930 set_grs_a5a5 ; Fill all general regs with a fixed pattern 931 set_ccr_zero 932 933 ;; neg.l @(dd:32, erd) 934 mov #long_dest-0xfffff, er1 935 neg.l @(0xfffff:32, er1) ; reg plus 32-bit displacement 936 ;;; .word 0x7894 937 ;;; .word 0x6b28 938 ;;; .long 0xfffff 939 ;;; .word 0x17b0 940 941 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 942 test_ovf_clear 943 test_zero_clear 944 test_neg_set 945 946 cmp.l #0xa5a5a5a5, @long_dest 947 beq .Lldisp32 948 fail 949 .Lldisp32: 950 test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address 951 test_gr_a5a5 0 ; Make sure other general regs not disturbed 952 test_gr_a5a5 2 953 test_gr_a5a5 3 954 test_gr_a5a5 4 955 test_gr_a5a5 5 956 test_gr_a5a5 6 957 test_gr_a5a5 7 958 959 neg_l_abs16dst: 960 set_grs_a5a5 ; Fill all general regs with a fixed pattern 961 set_ccr_zero 962 963 ;; neg.l @aa:16 964 neg.l @long_dest:16 ; 16-bit absolute address 965 ;;; .word 0x0104 966 ;;; .word 0x6b08 967 ;;; .word long_dest 968 ;;; .word 0x17b0 969 970 test_carry_set ; H=0 N=0 Z=0 V=0 C=1 971 test_ovf_clear 972 test_zero_clear 973 test_neg_clear 974 975 cmp.l #0x5a5a5a5b, @long_dest 976 beq .Llabs16 977 fail 978 .Llabs16: 979 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 980 test_gr_a5a5 1 981 test_gr_a5a5 2 982 test_gr_a5a5 3 983 test_gr_a5a5 4 984 test_gr_a5a5 5 985 test_gr_a5a5 6 986 test_gr_a5a5 7 987 988 neg_l_abs32dst: 989 set_grs_a5a5 ; Fill all general regs with a fixed pattern 990 set_ccr_zero 991 992 ;; neg.l @aa:32 993 neg.l @long_dest:32 ; 32-bit absolute address 994 ;;; .word 0x0104 995 ;;; .word 0x6b28 996 ;;; .long long_dest 997 ;;; .word 0x17b0 998 999 test_carry_set ; H=0 N=1 Z=0 V=0 C=1 1000 test_ovf_clear 1001 test_zero_clear 1002 test_neg_set 1003 1004 cmp.l #0xa5a5a5a5, @long_dest 1005 beq .Llabs32 1006 fail 1007 .Llabs32: 1008 test_gr_a5a5 0 ; Make sure ALL general regs not disturbed 1009 test_gr_a5a5 1 1010 test_gr_a5a5 2 1011 test_gr_a5a5 3 1012 test_gr_a5a5 4 1013 test_gr_a5a5 5 1014 test_gr_a5a5 6 1015 test_gr_a5a5 7 1016 1017 .endif ; h8sx 1018 .endif ; h8/300 1019 1020 pass 1021 1022 exit 0 1023
Indexes created Sun Mar 01 05:31:48 UTC 2026