1 /* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger. 2 3 Copyright (C) 2011-2024 Free Software Foundation, Inc. 4 5 Contributed by Red Hat, Inc. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 21 22 #include "arch-utils.h" 23 #include "extract-store-integer.h" 24 #include "prologue-value.h" 25 #include "target.h" 26 #include "regcache.h" 27 #include "opcode/rl78.h" 28 #include "dis-asm.h" 29 #include "gdbtypes.h" 30 #include "frame.h" 31 #include "frame-unwind.h" 32 #include "frame-base.h" 33 #include "value.h" 34 #include "gdbcore.h" 35 #include "dwarf2/frame.h" 36 #include "reggroups.h" 37 #include "gdbarch.h" 38 #include "inferior.h" 39 40 #include "elf/rl78.h" 41 #include "elf-bfd.h" 42 43 /* Register Banks. */ 44 45 enum 46 { 47 RL78_BANK0 = 0, 48 RL78_BANK1 = 1, 49 RL78_BANK2 = 2, 50 RL78_BANK3 = 3, 51 RL78_NUMBANKS = 4, 52 RL78_REGS_PER_BANK = 8 53 }; 54 55 /* Register Numbers. */ 56 57 enum 58 { 59 /* All general purpose registers are 8 bits wide. */ 60 RL78_RAW_BANK0_R0_REGNUM = 0, 61 RL78_RAW_BANK0_R1_REGNUM, 62 RL78_RAW_BANK0_R2_REGNUM, 63 RL78_RAW_BANK0_R3_REGNUM, 64 RL78_RAW_BANK0_R4_REGNUM, 65 RL78_RAW_BANK0_R5_REGNUM, 66 RL78_RAW_BANK0_R6_REGNUM, 67 RL78_RAW_BANK0_R7_REGNUM, 68 69 RL78_RAW_BANK1_R0_REGNUM, 70 RL78_RAW_BANK1_R1_REGNUM, 71 RL78_RAW_BANK1_R2_REGNUM, 72 RL78_RAW_BANK1_R3_REGNUM, 73 RL78_RAW_BANK1_R4_REGNUM, 74 RL78_RAW_BANK1_R5_REGNUM, 75 RL78_RAW_BANK1_R6_REGNUM, 76 RL78_RAW_BANK1_R7_REGNUM, 77 78 RL78_RAW_BANK2_R0_REGNUM, 79 RL78_RAW_BANK2_R1_REGNUM, 80 RL78_RAW_BANK2_R2_REGNUM, 81 RL78_RAW_BANK2_R3_REGNUM, 82 RL78_RAW_BANK2_R4_REGNUM, 83 RL78_RAW_BANK2_R5_REGNUM, 84 RL78_RAW_BANK2_R6_REGNUM, 85 RL78_RAW_BANK2_R7_REGNUM, 86 87 RL78_RAW_BANK3_R0_REGNUM, 88 RL78_RAW_BANK3_R1_REGNUM, 89 RL78_RAW_BANK3_R2_REGNUM, 90 RL78_RAW_BANK3_R3_REGNUM, 91 RL78_RAW_BANK3_R4_REGNUM, 92 RL78_RAW_BANK3_R5_REGNUM, 93 RL78_RAW_BANK3_R6_REGNUM, 94 RL78_RAW_BANK3_R7_REGNUM, 95 96 RL78_PSW_REGNUM, /* 8 bits */ 97 RL78_ES_REGNUM, /* 8 bits */ 98 RL78_CS_REGNUM, /* 8 bits */ 99 RL78_RAW_PC_REGNUM, /* 20 bits; we'll use 32 bits for it. */ 100 101 /* Fixed address SFRs (some of those above are SFRs too.) */ 102 RL78_SPL_REGNUM, /* 8 bits; lower half of SP */ 103 RL78_SPH_REGNUM, /* 8 bits; upper half of SP */ 104 RL78_PMC_REGNUM, /* 8 bits */ 105 RL78_MEM_REGNUM, /* 8 bits ?? */ 106 107 RL78_NUM_REGS, 108 109 /* Pseudo registers. */ 110 RL78_PC_REGNUM = RL78_NUM_REGS, 111 RL78_SP_REGNUM, 112 113 RL78_X_REGNUM, 114 RL78_A_REGNUM, 115 RL78_C_REGNUM, 116 RL78_B_REGNUM, 117 RL78_E_REGNUM, 118 RL78_D_REGNUM, 119 RL78_L_REGNUM, 120 RL78_H_REGNUM, 121 122 RL78_AX_REGNUM, 123 RL78_BC_REGNUM, 124 RL78_DE_REGNUM, 125 RL78_HL_REGNUM, 126 127 RL78_BANK0_R0_REGNUM, 128 RL78_BANK0_R1_REGNUM, 129 RL78_BANK0_R2_REGNUM, 130 RL78_BANK0_R3_REGNUM, 131 RL78_BANK0_R4_REGNUM, 132 RL78_BANK0_R5_REGNUM, 133 RL78_BANK0_R6_REGNUM, 134 RL78_BANK0_R7_REGNUM, 135 136 RL78_BANK1_R0_REGNUM, 137 RL78_BANK1_R1_REGNUM, 138 RL78_BANK1_R2_REGNUM, 139 RL78_BANK1_R3_REGNUM, 140 RL78_BANK1_R4_REGNUM, 141 RL78_BANK1_R5_REGNUM, 142 RL78_BANK1_R6_REGNUM, 143 RL78_BANK1_R7_REGNUM, 144 145 RL78_BANK2_R0_REGNUM, 146 RL78_BANK2_R1_REGNUM, 147 RL78_BANK2_R2_REGNUM, 148 RL78_BANK2_R3_REGNUM, 149 RL78_BANK2_R4_REGNUM, 150 RL78_BANK2_R5_REGNUM, 151 RL78_BANK2_R6_REGNUM, 152 RL78_BANK2_R7_REGNUM, 153 154 RL78_BANK3_R0_REGNUM, 155 RL78_BANK3_R1_REGNUM, 156 RL78_BANK3_R2_REGNUM, 157 RL78_BANK3_R3_REGNUM, 158 RL78_BANK3_R4_REGNUM, 159 RL78_BANK3_R5_REGNUM, 160 RL78_BANK3_R6_REGNUM, 161 RL78_BANK3_R7_REGNUM, 162 163 RL78_BANK0_RP0_REGNUM, 164 RL78_BANK0_RP1_REGNUM, 165 RL78_BANK0_RP2_REGNUM, 166 RL78_BANK0_RP3_REGNUM, 167 168 RL78_BANK1_RP0_REGNUM, 169 RL78_BANK1_RP1_REGNUM, 170 RL78_BANK1_RP2_REGNUM, 171 RL78_BANK1_RP3_REGNUM, 172 173 RL78_BANK2_RP0_REGNUM, 174 RL78_BANK2_RP1_REGNUM, 175 RL78_BANK2_RP2_REGNUM, 176 RL78_BANK2_RP3_REGNUM, 177 178 RL78_BANK3_RP0_REGNUM, 179 RL78_BANK3_RP1_REGNUM, 180 RL78_BANK3_RP2_REGNUM, 181 RL78_BANK3_RP3_REGNUM, 182 183 /* These are the same as the above 16 registers, but have 184 a pointer type for use as base registers in expression 185 evaluation. These are not user visible registers. */ 186 RL78_BANK0_RP0_PTR_REGNUM, 187 RL78_BANK0_RP1_PTR_REGNUM, 188 RL78_BANK0_RP2_PTR_REGNUM, 189 RL78_BANK0_RP3_PTR_REGNUM, 190 191 RL78_BANK1_RP0_PTR_REGNUM, 192 RL78_BANK1_RP1_PTR_REGNUM, 193 RL78_BANK1_RP2_PTR_REGNUM, 194 RL78_BANK1_RP3_PTR_REGNUM, 195 196 RL78_BANK2_RP0_PTR_REGNUM, 197 RL78_BANK2_RP1_PTR_REGNUM, 198 RL78_BANK2_RP2_PTR_REGNUM, 199 RL78_BANK2_RP3_PTR_REGNUM, 200 201 RL78_BANK3_RP0_PTR_REGNUM, 202 RL78_BANK3_RP1_PTR_REGNUM, 203 RL78_BANK3_RP2_PTR_REGNUM, 204 RL78_BANK3_RP3_PTR_REGNUM, 205 206 RL78_NUM_TOTAL_REGS, 207 RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS 208 }; 209 210 #define RL78_SP_ADDR 0xffff8 211 212 /* Architecture specific data. */ 213 214 struct rl78_gdbarch_tdep : gdbarch_tdep_base 215 { 216 /* The ELF header flags specify the multilib used. */ 217 int elf_flags = 0; 218 219 struct type *rl78_void = nullptr, 220 *rl78_uint8 = nullptr, 221 *rl78_int8 = nullptr, 222 *rl78_uint16 = nullptr, 223 *rl78_int16 = nullptr, 224 *rl78_uint32 = nullptr, 225 *rl78_int32 = nullptr, 226 *rl78_data_pointer = nullptr, 227 *rl78_code_pointer = nullptr, 228 *rl78_psw_type = nullptr; 229 }; 230 231 /* This structure holds the results of a prologue analysis. */ 232 233 struct rl78_prologue 234 { 235 /* The offset from the frame base to the stack pointer --- always 236 zero or negative. 237 238 Calling this a "size" is a bit misleading, but given that the 239 stack grows downwards, using offsets for everything keeps one 240 from going completely sign-crazy: you never change anything's 241 sign for an ADD instruction; always change the second operand's 242 sign for a SUB instruction; and everything takes care of 243 itself. */ 244 int frame_size; 245 246 /* Non-zero if this function has initialized the frame pointer from 247 the stack pointer, zero otherwise. */ 248 int has_frame_ptr; 249 250 /* If has_frame_ptr is non-zero, this is the offset from the frame 251 base to where the frame pointer points. This is always zero or 252 negative. */ 253 int frame_ptr_offset; 254 255 /* The address of the first instruction at which the frame has been 256 set up and the arguments are where the debug info says they are 257 --- as best as we can tell. */ 258 CORE_ADDR prologue_end; 259 260 /* reg_offset[R] is the offset from the CFA at which register R is 261 saved, or 1 if register R has not been saved. (Real values are 262 always zero or negative.) */ 263 int reg_offset[RL78_NUM_TOTAL_REGS]; 264 }; 265 266 /* Construct type for PSW register. */ 267 268 static struct type * 269 rl78_psw_type (struct gdbarch *gdbarch) 270 { 271 rl78_gdbarch_tdep *tdep = gdbarch_tdep<rl78_gdbarch_tdep> (gdbarch); 272 273 if (tdep->rl78_psw_type == NULL) 274 { 275 tdep->rl78_psw_type = arch_flags_type (gdbarch, 276 "builtin_type_rl78_psw", 8); 277 append_flags_type_flag (tdep->rl78_psw_type, 0, "CY"); 278 append_flags_type_flag (tdep->rl78_psw_type, 1, "ISP0"); 279 append_flags_type_flag (tdep->rl78_psw_type, 2, "ISP1"); 280 append_flags_type_flag (tdep->rl78_psw_type, 3, "RBS0"); 281 append_flags_type_flag (tdep->rl78_psw_type, 4, "AC"); 282 append_flags_type_flag (tdep->rl78_psw_type, 5, "RBS1"); 283 append_flags_type_flag (tdep->rl78_psw_type, 6, "Z"); 284 append_flags_type_flag (tdep->rl78_psw_type, 7, "IE"); 285 } 286 287 return tdep->rl78_psw_type; 288 } 289 290 /* Implement the "register_type" gdbarch method. */ 291 292 static struct type * 293 rl78_register_type (struct gdbarch *gdbarch, int reg_nr) 294 { 295 rl78_gdbarch_tdep *tdep = gdbarch_tdep<rl78_gdbarch_tdep> (gdbarch); 296 297 if (reg_nr == RL78_PC_REGNUM) 298 return tdep->rl78_code_pointer; 299 else if (reg_nr == RL78_RAW_PC_REGNUM) 300 return tdep->rl78_uint32; 301 else if (reg_nr == RL78_PSW_REGNUM) 302 return rl78_psw_type (gdbarch); 303 else if (reg_nr <= RL78_MEM_REGNUM 304 || (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM) 305 || (RL78_BANK0_R0_REGNUM <= reg_nr 306 && reg_nr <= RL78_BANK3_R7_REGNUM)) 307 return tdep->rl78_int8; 308 else if (reg_nr == RL78_SP_REGNUM 309 || (RL78_BANK0_RP0_PTR_REGNUM <= reg_nr 310 && reg_nr <= RL78_BANK3_RP3_PTR_REGNUM)) 311 return tdep->rl78_data_pointer; 312 else 313 return tdep->rl78_int16; 314 } 315 316 /* Implement the "register_name" gdbarch method. */ 317 318 static const char * 319 rl78_register_name (struct gdbarch *gdbarch, int regnr) 320 { 321 static const char *const reg_names[] = 322 { 323 "", /* bank0_r0 */ 324 "", /* bank0_r1 */ 325 "", /* bank0_r2 */ 326 "", /* bank0_r3 */ 327 "", /* bank0_r4 */ 328 "", /* bank0_r5 */ 329 "", /* bank0_r6 */ 330 "", /* bank0_r7 */ 331 332 "", /* bank1_r0 */ 333 "", /* bank1_r1 */ 334 "", /* bank1_r2 */ 335 "", /* bank1_r3 */ 336 "", /* bank1_r4 */ 337 "", /* bank1_r5 */ 338 "", /* bank1_r6 */ 339 "", /* bank1_r7 */ 340 341 "", /* bank2_r0 */ 342 "", /* bank2_r1 */ 343 "", /* bank2_r2 */ 344 "", /* bank2_r3 */ 345 "", /* bank2_r4 */ 346 "", /* bank2_r5 */ 347 "", /* bank2_r6 */ 348 "", /* bank2_r7 */ 349 350 "", /* bank3_r0 */ 351 "", /* bank3_r1 */ 352 "", /* bank3_r2 */ 353 "", /* bank3_r3 */ 354 "", /* bank3_r4 */ 355 "", /* bank3_r5 */ 356 "", /* bank3_r6 */ 357 "", /* bank3_r7 */ 358 359 "psw", 360 "es", 361 "cs", 362 "", 363 364 "", /* spl */ 365 "", /* sph */ 366 "pmc", 367 "mem", 368 369 "pc", 370 "sp", 371 372 "x", 373 "a", 374 "c", 375 "b", 376 "e", 377 "d", 378 "l", 379 "h", 380 381 "ax", 382 "bc", 383 "de", 384 "hl", 385 386 "bank0_r0", 387 "bank0_r1", 388 "bank0_r2", 389 "bank0_r3", 390 "bank0_r4", 391 "bank0_r5", 392 "bank0_r6", 393 "bank0_r7", 394 395 "bank1_r0", 396 "bank1_r1", 397 "bank1_r2", 398 "bank1_r3", 399 "bank1_r4", 400 "bank1_r5", 401 "bank1_r6", 402 "bank1_r7", 403 404 "bank2_r0", 405 "bank2_r1", 406 "bank2_r2", 407 "bank2_r3", 408 "bank2_r4", 409 "bank2_r5", 410 "bank2_r6", 411 "bank2_r7", 412 413 "bank3_r0", 414 "bank3_r1", 415 "bank3_r2", 416 "bank3_r3", 417 "bank3_r4", 418 "bank3_r5", 419 "bank3_r6", 420 "bank3_r7", 421 422 "bank0_rp0", 423 "bank0_rp1", 424 "bank0_rp2", 425 "bank0_rp3", 426 427 "bank1_rp0", 428 "bank1_rp1", 429 "bank1_rp2", 430 "bank1_rp3", 431 432 "bank2_rp0", 433 "bank2_rp1", 434 "bank2_rp2", 435 "bank2_rp3", 436 437 "bank3_rp0", 438 "bank3_rp1", 439 "bank3_rp2", 440 "bank3_rp3", 441 442 /* The 16 register slots would be named 443 bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't 444 want these to be user visible registers. */ 445 "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "" 446 }; 447 448 return reg_names[regnr]; 449 } 450 451 /* Implement the "register_name" gdbarch method for the g10 variant. */ 452 453 static const char * 454 rl78_g10_register_name (struct gdbarch *gdbarch, int regnr) 455 { 456 static const char *const reg_names[] = 457 { 458 "", /* bank0_r0 */ 459 "", /* bank0_r1 */ 460 "", /* bank0_r2 */ 461 "", /* bank0_r3 */ 462 "", /* bank0_r4 */ 463 "", /* bank0_r5 */ 464 "", /* bank0_r6 */ 465 "", /* bank0_r7 */ 466 467 "", /* bank1_r0 */ 468 "", /* bank1_r1 */ 469 "", /* bank1_r2 */ 470 "", /* bank1_r3 */ 471 "", /* bank1_r4 */ 472 "", /* bank1_r5 */ 473 "", /* bank1_r6 */ 474 "", /* bank1_r7 */ 475 476 "", /* bank2_r0 */ 477 "", /* bank2_r1 */ 478 "", /* bank2_r2 */ 479 "", /* bank2_r3 */ 480 "", /* bank2_r4 */ 481 "", /* bank2_r5 */ 482 "", /* bank2_r6 */ 483 "", /* bank2_r7 */ 484 485 "", /* bank3_r0 */ 486 "", /* bank3_r1 */ 487 "", /* bank3_r2 */ 488 "", /* bank3_r3 */ 489 "", /* bank3_r4 */ 490 "", /* bank3_r5 */ 491 "", /* bank3_r6 */ 492 "", /* bank3_r7 */ 493 494 "psw", 495 "es", 496 "cs", 497 "", 498 499 "", /* spl */ 500 "", /* sph */ 501 "pmc", 502 "mem", 503 504 "pc", 505 "sp", 506 507 "x", 508 "a", 509 "c", 510 "b", 511 "e", 512 "d", 513 "l", 514 "h", 515 516 "ax", 517 "bc", 518 "de", 519 "hl", 520 521 "bank0_r0", 522 "bank0_r1", 523 "bank0_r2", 524 "bank0_r3", 525 "bank0_r4", 526 "bank0_r5", 527 "bank0_r6", 528 "bank0_r7", 529 530 "", 531 "", 532 "", 533 "", 534 "", 535 "", 536 "", 537 "", 538 539 "", 540 "", 541 "", 542 "", 543 "", 544 "", 545 "", 546 "", 547 548 "", 549 "", 550 "", 551 "", 552 "", 553 "", 554 "", 555 "", 556 557 "bank0_rp0", 558 "bank0_rp1", 559 "bank0_rp2", 560 "bank0_rp3", 561 562 "", 563 "", 564 "", 565 "", 566 567 "", 568 "", 569 "", 570 "", 571 572 "", 573 "", 574 "", 575 "", 576 577 /* The 16 register slots would be named 578 bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't 579 want these to be user visible registers. */ 580 "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "" 581 }; 582 583 return reg_names[regnr]; 584 } 585 586 /* Implement the "register_reggroup_p" gdbarch method. */ 587 588 static int 589 rl78_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 590 const struct reggroup *group) 591 { 592 if (group == all_reggroup) 593 return 1; 594 595 /* All other registers are saved and restored. */ 596 if (group == save_reggroup || group == restore_reggroup) 597 { 598 if ((regnum < RL78_NUM_REGS 599 && regnum != RL78_SPL_REGNUM 600 && regnum != RL78_SPH_REGNUM 601 && regnum != RL78_RAW_PC_REGNUM) 602 || regnum == RL78_SP_REGNUM 603 || regnum == RL78_PC_REGNUM) 604 return 1; 605 else 606 return 0; 607 } 608 609 if ((RL78_BANK0_R0_REGNUM <= regnum && regnum <= RL78_BANK3_R7_REGNUM) 610 || regnum == RL78_ES_REGNUM 611 || regnum == RL78_CS_REGNUM 612 || regnum == RL78_SPL_REGNUM 613 || regnum == RL78_SPH_REGNUM 614 || regnum == RL78_PMC_REGNUM 615 || regnum == RL78_MEM_REGNUM 616 || regnum == RL78_RAW_PC_REGNUM 617 || (RL78_BANK0_RP0_REGNUM <= regnum && regnum <= RL78_BANK3_RP3_REGNUM)) 618 return group == system_reggroup; 619 620 return group == general_reggroup; 621 } 622 623 /* Strip bits to form an instruction address. (When fetching a 624 32-bit address from the stack, the high eight bits are garbage. 625 This function strips off those unused bits.) */ 626 627 static CORE_ADDR 628 rl78_make_instruction_address (CORE_ADDR addr) 629 { 630 return addr & 0xffffff; 631 } 632 633 /* Set / clear bits necessary to make a data address. */ 634 635 static CORE_ADDR 636 rl78_make_data_address (CORE_ADDR addr) 637 { 638 return (addr & 0xffff) | 0xf0000; 639 } 640 641 /* Implement the "pseudo_register_read" gdbarch method. */ 642 643 static enum register_status 644 rl78_pseudo_register_read (struct gdbarch *gdbarch, 645 readable_regcache *regcache, 646 int reg, gdb_byte *buffer) 647 { 648 enum register_status status; 649 650 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM) 651 { 652 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM 653 + (reg - RL78_BANK0_R0_REGNUM); 654 655 status = regcache->raw_read (raw_regnum, buffer); 656 } 657 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM) 658 { 659 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM) 660 + RL78_RAW_BANK0_R0_REGNUM; 661 662 status = regcache->raw_read (raw_regnum, buffer); 663 if (status == REG_VALID) 664 status = regcache->raw_read (raw_regnum + 1, buffer + 1); 665 } 666 else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM) 667 { 668 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM) 669 + RL78_RAW_BANK0_R0_REGNUM; 670 671 status = regcache->raw_read (raw_regnum, buffer); 672 if (status == REG_VALID) 673 status = regcache->raw_read (raw_regnum + 1, buffer + 1); 674 } 675 else if (reg == RL78_SP_REGNUM) 676 { 677 status = regcache->raw_read (RL78_SPL_REGNUM, buffer); 678 if (status == REG_VALID) 679 status = regcache->raw_read (RL78_SPH_REGNUM, buffer + 1); 680 } 681 else if (reg == RL78_PC_REGNUM) 682 { 683 gdb_byte rawbuf[4]; 684 685 status = regcache->raw_read (RL78_RAW_PC_REGNUM, rawbuf); 686 memcpy (buffer, rawbuf, 3); 687 } 688 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM) 689 { 690 ULONGEST psw; 691 692 status = regcache->raw_read (RL78_PSW_REGNUM, &psw); 693 if (status == REG_VALID) 694 { 695 /* RSB0 is at bit 3; RSBS1 is at bit 5. */ 696 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1); 697 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK 698 + (reg - RL78_X_REGNUM); 699 status = regcache->raw_read (raw_regnum, buffer); 700 } 701 } 702 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM) 703 { 704 ULONGEST psw; 705 706 status = regcache->raw_read (RL78_PSW_REGNUM, &psw); 707 if (status == REG_VALID) 708 { 709 /* RSB0 is at bit 3; RSBS1 is at bit 5. */ 710 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1); 711 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK 712 + 2 * (reg - RL78_AX_REGNUM); 713 status = regcache->raw_read (raw_regnum, buffer); 714 if (status == REG_VALID) 715 status = regcache->raw_read (raw_regnum + 1, buffer + 1); 716 } 717 } 718 else 719 gdb_assert_not_reached ("invalid pseudo register number"); 720 return status; 721 } 722 723 /* Implement the "pseudo_register_write" gdbarch method. */ 724 725 static void 726 rl78_pseudo_register_write (struct gdbarch *gdbarch, 727 struct regcache *regcache, 728 int reg, const gdb_byte *buffer) 729 { 730 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM) 731 { 732 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM 733 + (reg - RL78_BANK0_R0_REGNUM); 734 735 regcache->raw_write (raw_regnum, buffer); 736 } 737 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM) 738 { 739 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM) 740 + RL78_RAW_BANK0_R0_REGNUM; 741 742 regcache->raw_write (raw_regnum, buffer); 743 regcache->raw_write (raw_regnum + 1, buffer + 1); 744 } 745 else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM) 746 { 747 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM) 748 + RL78_RAW_BANK0_R0_REGNUM; 749 750 regcache->raw_write (raw_regnum, buffer); 751 regcache->raw_write (raw_regnum + 1, buffer + 1); 752 } 753 else if (reg == RL78_SP_REGNUM) 754 { 755 regcache->raw_write (RL78_SPL_REGNUM, buffer); 756 regcache->raw_write (RL78_SPH_REGNUM, buffer + 1); 757 } 758 else if (reg == RL78_PC_REGNUM) 759 { 760 gdb_byte rawbuf[4]; 761 762 memcpy (rawbuf, buffer, 3); 763 rawbuf[3] = 0; 764 regcache->raw_write (RL78_RAW_PC_REGNUM, rawbuf); 765 } 766 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM) 767 { 768 ULONGEST psw; 769 int bank; 770 int raw_regnum; 771 772 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw); 773 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1); 774 /* RSB0 is at bit 3; RSBS1 is at bit 5. */ 775 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK 776 + (reg - RL78_X_REGNUM); 777 regcache->raw_write (raw_regnum, buffer); 778 } 779 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM) 780 { 781 ULONGEST psw; 782 int bank, raw_regnum; 783 784 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw); 785 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1); 786 /* RSB0 is at bit 3; RSBS1 is at bit 5. */ 787 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK 788 + 2 * (reg - RL78_AX_REGNUM); 789 regcache->raw_write (raw_regnum, buffer); 790 regcache->raw_write (raw_regnum + 1, buffer + 1); 791 } 792 else 793 gdb_assert_not_reached ("invalid pseudo register number"); 794 } 795 796 /* The documented BRK instruction is actually a two byte sequence, 797 {0x61, 0xcc}, but instructions may be as short as one byte. 798 Correspondence with Renesas revealed that the one byte sequence 799 0xff is used when a one byte breakpoint instruction is required. */ 800 constexpr gdb_byte rl78_break_insn[] = { 0xff }; 801 802 typedef BP_MANIPULATION (rl78_break_insn) rl78_breakpoint; 803 804 /* Define a "handle" struct for fetching the next opcode. */ 805 806 struct rl78_get_opcode_byte_handle 807 { 808 CORE_ADDR pc; 809 }; 810 811 static int 812 opc_reg_to_gdb_regnum (int opcreg) 813 { 814 switch (opcreg) 815 { 816 case RL78_Reg_X: 817 return RL78_X_REGNUM; 818 case RL78_Reg_A: 819 return RL78_A_REGNUM; 820 case RL78_Reg_C: 821 return RL78_C_REGNUM; 822 case RL78_Reg_B: 823 return RL78_B_REGNUM; 824 case RL78_Reg_E: 825 return RL78_E_REGNUM; 826 case RL78_Reg_D: 827 return RL78_D_REGNUM; 828 case RL78_Reg_L: 829 return RL78_L_REGNUM; 830 case RL78_Reg_H: 831 return RL78_H_REGNUM; 832 case RL78_Reg_AX: 833 return RL78_AX_REGNUM; 834 case RL78_Reg_BC: 835 return RL78_BC_REGNUM; 836 case RL78_Reg_DE: 837 return RL78_DE_REGNUM; 838 case RL78_Reg_HL: 839 return RL78_HL_REGNUM; 840 case RL78_Reg_SP: 841 return RL78_SP_REGNUM; 842 case RL78_Reg_PSW: 843 return RL78_PSW_REGNUM; 844 case RL78_Reg_CS: 845 return RL78_CS_REGNUM; 846 case RL78_Reg_ES: 847 return RL78_ES_REGNUM; 848 case RL78_Reg_PMC: 849 return RL78_PMC_REGNUM; 850 case RL78_Reg_MEM: 851 return RL78_MEM_REGNUM; 852 default: 853 internal_error (_("Undefined mapping for opc reg %d"), 854 opcreg); 855 } 856 857 /* Not reached. */ 858 return 0; 859 } 860 861 /* Fetch a byte on behalf of the opcode decoder. HANDLE contains 862 the memory address of the next byte to fetch. If successful, 863 the address in the handle is updated and the byte fetched is 864 returned as the value of the function. If not successful, -1 865 is returned. */ 866 867 static int 868 rl78_get_opcode_byte (void *handle) 869 { 870 struct rl78_get_opcode_byte_handle *opcdata 871 = (struct rl78_get_opcode_byte_handle *) handle; 872 int status; 873 gdb_byte byte; 874 875 status = target_read_memory (opcdata->pc, &byte, 1); 876 if (status == 0) 877 { 878 opcdata->pc += 1; 879 return byte; 880 } 881 else 882 return -1; 883 } 884 885 /* Function for finding saved registers in a 'struct pv_area'; this 886 function is passed to pv_area::scan. 887 888 If VALUE is a saved register, ADDR says it was saved at a constant 889 offset from the frame base, and SIZE indicates that the whole 890 register was saved, record its offset. */ 891 892 static void 893 check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size, 894 pv_t value) 895 { 896 struct rl78_prologue *result = (struct rl78_prologue *) result_untyped; 897 898 if (value.kind == pvk_register 899 && value.k == 0 900 && pv_is_register (addr, RL78_SP_REGNUM) 901 && size == register_size (current_inferior ()->arch (), value.reg)) 902 result->reg_offset[value.reg] = addr.k; 903 } 904 905 /* Analyze a prologue starting at START_PC, going no further than 906 LIMIT_PC. Fill in RESULT as appropriate. */ 907 908 static void 909 rl78_analyze_prologue (CORE_ADDR start_pc, 910 CORE_ADDR limit_pc, struct rl78_prologue *result) 911 { 912 CORE_ADDR pc, next_pc; 913 int rn; 914 pv_t reg[RL78_NUM_TOTAL_REGS]; 915 CORE_ADDR after_last_frame_setup_insn = start_pc; 916 int bank = 0; 917 918 memset (result, 0, sizeof (*result)); 919 920 for (rn = 0; rn < RL78_NUM_TOTAL_REGS; rn++) 921 { 922 reg[rn] = pv_register (rn, 0); 923 result->reg_offset[rn] = 1; 924 } 925 926 pv_area stack (RL78_SP_REGNUM, 927 gdbarch_addr_bit (current_inferior ()->arch ())); 928 929 /* The call instruction has saved the return address on the stack. */ 930 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -4); 931 stack.store (reg[RL78_SP_REGNUM], 4, reg[RL78_PC_REGNUM]); 932 933 pc = start_pc; 934 while (pc < limit_pc) 935 { 936 int bytes_read; 937 struct rl78_get_opcode_byte_handle opcode_handle; 938 RL78_Opcode_Decoded opc; 939 940 opcode_handle.pc = pc; 941 bytes_read = rl78_decode_opcode (pc, &opc, rl78_get_opcode_byte, 942 &opcode_handle, RL78_ISA_DEFAULT); 943 next_pc = pc + bytes_read; 944 945 if (opc.id == RLO_sel) 946 { 947 bank = opc.op[1].addend; 948 } 949 else if (opc.id == RLO_mov 950 && opc.op[0].type == RL78_Operand_PreDec 951 && opc.op[0].reg == RL78_Reg_SP 952 && opc.op[1].type == RL78_Operand_Register) 953 { 954 int rsrc = (bank * RL78_REGS_PER_BANK) 955 + 2 * (opc.op[1].reg - RL78_Reg_AX); 956 957 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1); 958 stack.store (reg[RL78_SP_REGNUM], 1, reg[rsrc]); 959 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1); 960 stack.store (reg[RL78_SP_REGNUM], 1, reg[rsrc + 1]); 961 after_last_frame_setup_insn = next_pc; 962 } 963 else if (opc.id == RLO_sub 964 && opc.op[0].type == RL78_Operand_Register 965 && opc.op[0].reg == RL78_Reg_SP 966 && opc.op[1].type == RL78_Operand_Immediate) 967 { 968 int addend = opc.op[1].addend; 969 970 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], 971 -addend); 972 after_last_frame_setup_insn = next_pc; 973 } 974 else if (opc.id == RLO_mov 975 && opc.size == RL78_Word 976 && opc.op[0].type == RL78_Operand_Register 977 && opc.op[1].type == RL78_Operand_Indirect 978 && opc.op[1].addend == RL78_SP_ADDR) 979 { 980 reg[opc_reg_to_gdb_regnum (opc.op[0].reg)] 981 = reg[RL78_SP_REGNUM]; 982 } 983 else if (opc.id == RLO_sub 984 && opc.size == RL78_Word 985 && opc.op[0].type == RL78_Operand_Register 986 && opc.op[1].type == RL78_Operand_Immediate) 987 { 988 int addend = opc.op[1].addend; 989 int regnum = opc_reg_to_gdb_regnum (opc.op[0].reg); 990 991 reg[regnum] = pv_add_constant (reg[regnum], -addend); 992 } 993 else if (opc.id == RLO_mov 994 && opc.size == RL78_Word 995 && opc.op[0].type == RL78_Operand_Indirect 996 && opc.op[0].addend == RL78_SP_ADDR 997 && opc.op[1].type == RL78_Operand_Register) 998 { 999 reg[RL78_SP_REGNUM] 1000 = reg[opc_reg_to_gdb_regnum (opc.op[1].reg)]; 1001 after_last_frame_setup_insn = next_pc; 1002 } 1003 else 1004 { 1005 /* Terminate the prologue scan. */ 1006 break; 1007 } 1008 1009 pc = next_pc; 1010 } 1011 1012 /* Is the frame size (offset, really) a known constant? */ 1013 if (pv_is_register (reg[RL78_SP_REGNUM], RL78_SP_REGNUM)) 1014 result->frame_size = reg[RL78_SP_REGNUM].k; 1015 1016 /* Record where all the registers were saved. */ 1017 stack.scan (check_for_saved, (void *) result); 1018 1019 result->prologue_end = after_last_frame_setup_insn; 1020 } 1021 1022 /* Implement the "addr_bits_remove" gdbarch method. */ 1023 1024 static CORE_ADDR 1025 rl78_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) 1026 { 1027 return addr & 0xffffff; 1028 } 1029 1030 /* Implement the "address_to_pointer" gdbarch method. */ 1031 1032 static void 1033 rl78_address_to_pointer (struct gdbarch *gdbarch, 1034 struct type *type, gdb_byte *buf, CORE_ADDR addr) 1035 { 1036 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1037 1038 store_unsigned_integer (buf, type->length (), byte_order, 1039 addr & 0xffffff); 1040 } 1041 1042 /* Implement the "pointer_to_address" gdbarch method. */ 1043 1044 static CORE_ADDR 1045 rl78_pointer_to_address (struct gdbarch *gdbarch, 1046 struct type *type, const gdb_byte *buf) 1047 { 1048 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1049 CORE_ADDR addr 1050 = extract_unsigned_integer (buf, type->length (), byte_order); 1051 1052 /* Is it a code address? */ 1053 if (type->target_type ()->code () == TYPE_CODE_FUNC 1054 || type->target_type ()->code () == TYPE_CODE_METHOD 1055 || TYPE_CODE_SPACE (type->target_type ()) 1056 || type->length () == 4) 1057 return rl78_make_instruction_address (addr); 1058 else 1059 return rl78_make_data_address (addr); 1060 } 1061 1062 /* Implement the "skip_prologue" gdbarch method. */ 1063 1064 static CORE_ADDR 1065 rl78_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 1066 { 1067 const char *name; 1068 CORE_ADDR func_addr, func_end; 1069 struct rl78_prologue p; 1070 1071 /* Try to find the extent of the function that contains PC. */ 1072 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end)) 1073 return pc; 1074 1075 rl78_analyze_prologue (pc, func_end, &p); 1076 return p.prologue_end; 1077 } 1078 1079 /* Implement the "unwind_pc" gdbarch method. */ 1080 1081 static CORE_ADDR 1082 rl78_unwind_pc (struct gdbarch *arch, const frame_info_ptr &next_frame) 1083 { 1084 return rl78_addr_bits_remove 1085 (arch, frame_unwind_register_unsigned (next_frame, 1086 RL78_PC_REGNUM)); 1087 } 1088 1089 /* Given a frame described by THIS_FRAME, decode the prologue of its 1090 associated function if there is not cache entry as specified by 1091 THIS_PROLOGUE_CACHE. Save the decoded prologue in the cache and 1092 return that struct as the value of this function. */ 1093 1094 static struct rl78_prologue * 1095 rl78_analyze_frame_prologue (const frame_info_ptr &this_frame, 1096 void **this_prologue_cache) 1097 { 1098 if (!*this_prologue_cache) 1099 { 1100 CORE_ADDR func_start, stop_addr; 1101 1102 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct rl78_prologue); 1103 1104 func_start = get_frame_func (this_frame); 1105 stop_addr = get_frame_pc (this_frame); 1106 1107 /* If we couldn't find any function containing the PC, then 1108 just initialize the prologue cache, but don't do anything. */ 1109 if (!func_start) 1110 stop_addr = func_start; 1111 1112 rl78_analyze_prologue (func_start, stop_addr, 1113 (struct rl78_prologue *) *this_prologue_cache); 1114 } 1115 1116 return (struct rl78_prologue *) *this_prologue_cache; 1117 } 1118 1119 /* Given a frame and a prologue cache, return this frame's base. */ 1120 1121 static CORE_ADDR 1122 rl78_frame_base (const frame_info_ptr &this_frame, void **this_prologue_cache) 1123 { 1124 struct rl78_prologue *p 1125 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache); 1126 CORE_ADDR sp = get_frame_register_unsigned (this_frame, RL78_SP_REGNUM); 1127 1128 return rl78_make_data_address (sp - p->frame_size); 1129 } 1130 1131 /* Implement the "frame_this_id" method for unwinding frames. */ 1132 1133 static void 1134 rl78_this_id (const frame_info_ptr &this_frame, 1135 void **this_prologue_cache, struct frame_id *this_id) 1136 { 1137 *this_id = frame_id_build (rl78_frame_base (this_frame, 1138 this_prologue_cache), 1139 get_frame_func (this_frame)); 1140 } 1141 1142 /* Implement the "frame_prev_register" method for unwinding frames. */ 1143 1144 static struct value * 1145 rl78_prev_register (const frame_info_ptr &this_frame, 1146 void **this_prologue_cache, int regnum) 1147 { 1148 struct rl78_prologue *p 1149 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache); 1150 CORE_ADDR frame_base = rl78_frame_base (this_frame, this_prologue_cache); 1151 1152 if (regnum == RL78_SP_REGNUM) 1153 return frame_unwind_got_constant (this_frame, regnum, frame_base); 1154 1155 else if (regnum == RL78_SPL_REGNUM) 1156 return frame_unwind_got_constant (this_frame, regnum, 1157 (frame_base & 0xff)); 1158 1159 else if (regnum == RL78_SPH_REGNUM) 1160 return frame_unwind_got_constant (this_frame, regnum, 1161 ((frame_base >> 8) & 0xff)); 1162 1163 /* If prologue analysis says we saved this register somewhere, 1164 return a description of the stack slot holding it. */ 1165 else if (p->reg_offset[regnum] != 1) 1166 { 1167 struct value *rv = 1168 frame_unwind_got_memory (this_frame, regnum, 1169 frame_base + p->reg_offset[regnum]); 1170 1171 if (regnum == RL78_PC_REGNUM) 1172 { 1173 ULONGEST pc = rl78_make_instruction_address (value_as_long (rv)); 1174 1175 return frame_unwind_got_constant (this_frame, regnum, pc); 1176 } 1177 return rv; 1178 } 1179 1180 /* Otherwise, presume we haven't changed the value of this 1181 register, and get it from the next frame. */ 1182 else 1183 return frame_unwind_got_register (this_frame, regnum, regnum); 1184 } 1185 1186 static const struct frame_unwind rl78_unwind = 1187 { 1188 "rl78 prologue", 1189 NORMAL_FRAME, 1190 default_frame_unwind_stop_reason, 1191 rl78_this_id, 1192 rl78_prev_register, 1193 NULL, 1194 default_frame_sniffer 1195 }; 1196 1197 /* Implement the "dwarf_reg_to_regnum" gdbarch method. */ 1198 1199 static int 1200 rl78_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) 1201 { 1202 if (0 <= reg && reg <= 31) 1203 { 1204 if ((reg & 1) == 0) 1205 /* Map even registers to their 16-bit counterparts which have a 1206 pointer type. This is usually what is required from the DWARF 1207 info. */ 1208 return (reg >> 1) + RL78_BANK0_RP0_PTR_REGNUM; 1209 else 1210 return reg; 1211 } 1212 else if (reg == 32) 1213 return RL78_SP_REGNUM; 1214 else if (reg == 33) 1215 return -1; /* ap */ 1216 else if (reg == 34) 1217 return RL78_PSW_REGNUM; 1218 else if (reg == 35) 1219 return RL78_ES_REGNUM; 1220 else if (reg == 36) 1221 return RL78_CS_REGNUM; 1222 else if (reg == 37) 1223 return RL78_PC_REGNUM; 1224 else 1225 return -1; 1226 } 1227 1228 /* Implement the `register_sim_regno' gdbarch method. */ 1229 1230 static int 1231 rl78_register_sim_regno (struct gdbarch *gdbarch, int regnum) 1232 { 1233 gdb_assert (regnum < RL78_NUM_REGS); 1234 1235 /* So long as regnum is in [0, RL78_NUM_REGS), it's valid. We 1236 just want to override the default here which disallows register 1237 numbers which have no names. */ 1238 return regnum; 1239 } 1240 1241 /* Implement the "return_value" gdbarch method. */ 1242 1243 static enum return_value_convention 1244 rl78_return_value (struct gdbarch *gdbarch, 1245 struct value *function, 1246 struct type *valtype, 1247 struct regcache *regcache, 1248 gdb_byte *readbuf, const gdb_byte *writebuf) 1249 { 1250 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1251 ULONGEST valtype_len = valtype->length (); 1252 rl78_gdbarch_tdep *tdep = gdbarch_tdep<rl78_gdbarch_tdep> (gdbarch); 1253 int is_g10 = tdep->elf_flags & E_FLAG_RL78_G10; 1254 1255 if (valtype_len > 8) 1256 return RETURN_VALUE_STRUCT_CONVENTION; 1257 1258 if (readbuf) 1259 { 1260 ULONGEST u; 1261 int argreg = RL78_RAW_BANK1_R0_REGNUM; 1262 CORE_ADDR g10_raddr = 0xffec8; 1263 int offset = 0; 1264 1265 while (valtype_len > 0) 1266 { 1267 if (is_g10) 1268 u = read_memory_integer (g10_raddr, 1, 1269 gdbarch_byte_order (gdbarch)); 1270 else 1271 regcache_cooked_read_unsigned (regcache, argreg, &u); 1272 store_unsigned_integer (readbuf + offset, 1, byte_order, u); 1273 valtype_len -= 1; 1274 offset += 1; 1275 argreg++; 1276 g10_raddr++; 1277 } 1278 } 1279 1280 if (writebuf) 1281 { 1282 ULONGEST u; 1283 int argreg = RL78_RAW_BANK1_R0_REGNUM; 1284 CORE_ADDR g10_raddr = 0xffec8; 1285 int offset = 0; 1286 1287 while (valtype_len > 0) 1288 { 1289 u = extract_unsigned_integer (writebuf + offset, 1, byte_order); 1290 if (is_g10) { 1291 gdb_byte b = u & 0xff; 1292 write_memory (g10_raddr, &b, 1); 1293 } 1294 else 1295 regcache_cooked_write_unsigned (regcache, argreg, u); 1296 valtype_len -= 1; 1297 offset += 1; 1298 argreg++; 1299 g10_raddr++; 1300 } 1301 } 1302 1303 return RETURN_VALUE_REGISTER_CONVENTION; 1304 } 1305 1306 1307 /* Implement the "frame_align" gdbarch method. */ 1308 1309 static CORE_ADDR 1310 rl78_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 1311 { 1312 return rl78_make_data_address (align_down (sp, 2)); 1313 } 1314 1315 1316 /* Implement the "dummy_id" gdbarch method. */ 1317 1318 static struct frame_id 1319 rl78_dummy_id (struct gdbarch *gdbarch, const frame_info_ptr &this_frame) 1320 { 1321 return 1322 frame_id_build (rl78_make_data_address 1323 (get_frame_register_unsigned 1324 (this_frame, RL78_SP_REGNUM)), 1325 get_frame_pc (this_frame)); 1326 } 1327 1328 1329 /* Implement the "push_dummy_call" gdbarch method. */ 1330 1331 static CORE_ADDR 1332 rl78_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 1333 struct regcache *regcache, CORE_ADDR bp_addr, 1334 int nargs, struct value **args, CORE_ADDR sp, 1335 function_call_return_method return_method, 1336 CORE_ADDR struct_addr) 1337 { 1338 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1339 gdb_byte buf[4]; 1340 int i; 1341 1342 /* Push arguments in reverse order. */ 1343 for (i = nargs - 1; i >= 0; i--) 1344 { 1345 struct type *value_type = args[i]->enclosing_type (); 1346 int len = value_type->length (); 1347 int container_len = (len + 1) & ~1; 1348 1349 sp -= container_len; 1350 write_memory (rl78_make_data_address (sp), 1351 args[i]->contents_all ().data (), len); 1352 } 1353 1354 /* Store struct value address. */ 1355 if (return_method == return_method_struct) 1356 { 1357 store_unsigned_integer (buf, 2, byte_order, struct_addr); 1358 sp -= 2; 1359 write_memory (rl78_make_data_address (sp), buf, 2); 1360 } 1361 1362 /* Store return address. */ 1363 sp -= 4; 1364 store_unsigned_integer (buf, 4, byte_order, bp_addr); 1365 write_memory (rl78_make_data_address (sp), buf, 4); 1366 1367 /* Finally, update the stack pointer... */ 1368 regcache_cooked_write_unsigned (regcache, RL78_SP_REGNUM, sp); 1369 1370 /* DWARF2/GCC uses the stack address *before* the function call as a 1371 frame's CFA. */ 1372 return rl78_make_data_address (sp + 4); 1373 } 1374 1375 /* Allocate and initialize a gdbarch object. */ 1376 1377 static struct gdbarch * 1378 rl78_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 1379 { 1380 int elf_flags; 1381 1382 /* Extract the elf_flags if available. */ 1383 if (info.abfd != NULL 1384 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) 1385 elf_flags = elf_elfheader (info.abfd)->e_flags; 1386 else 1387 elf_flags = 0; 1388 1389 1390 /* Try to find the architecture in the list of already defined 1391 architectures. */ 1392 for (arches = gdbarch_list_lookup_by_info (arches, &info); 1393 arches != NULL; 1394 arches = gdbarch_list_lookup_by_info (arches->next, &info)) 1395 { 1396 rl78_gdbarch_tdep *tdep 1397 = gdbarch_tdep<rl78_gdbarch_tdep> (arches->gdbarch); 1398 1399 if (tdep->elf_flags != elf_flags) 1400 continue; 1401 1402 return arches->gdbarch; 1403 } 1404 1405 /* None found, create a new architecture from the information 1406 provided. */ 1407 gdbarch *gdbarch 1408 = gdbarch_alloc (&info, gdbarch_tdep_up (new rl78_gdbarch_tdep)); 1409 rl78_gdbarch_tdep *tdep = gdbarch_tdep<rl78_gdbarch_tdep> (gdbarch); 1410 1411 tdep->elf_flags = elf_flags; 1412 1413 /* Initialize types. */ 1414 type_allocator alloc (gdbarch); 1415 tdep->rl78_void = alloc.new_type (TYPE_CODE_VOID, TARGET_CHAR_BIT, "void"); 1416 tdep->rl78_uint8 = init_integer_type (alloc, 8, 1, "uint8_t"); 1417 tdep->rl78_int8 = init_integer_type (alloc, 8, 0, "int8_t"); 1418 tdep->rl78_uint16 = init_integer_type (alloc, 16, 1, "uint16_t"); 1419 tdep->rl78_int16 = init_integer_type (alloc, 16, 0, "int16_t"); 1420 tdep->rl78_uint32 = init_integer_type (alloc, 32, 1, "uint32_t"); 1421 tdep->rl78_int32 = init_integer_type (alloc, 32, 0, "int32_t"); 1422 1423 tdep->rl78_data_pointer 1424 = init_pointer_type (alloc, 16, "rl78_data_addr_t", tdep->rl78_void); 1425 tdep->rl78_code_pointer 1426 = init_pointer_type (alloc, 32, "rl78_code_addr_t", tdep->rl78_void); 1427 1428 /* Registers. */ 1429 set_gdbarch_num_regs (gdbarch, RL78_NUM_REGS); 1430 set_gdbarch_num_pseudo_regs (gdbarch, RL78_NUM_PSEUDO_REGS); 1431 if (tdep->elf_flags & E_FLAG_RL78_G10) 1432 set_gdbarch_register_name (gdbarch, rl78_g10_register_name); 1433 else 1434 set_gdbarch_register_name (gdbarch, rl78_register_name); 1435 set_gdbarch_register_type (gdbarch, rl78_register_type); 1436 set_gdbarch_pc_regnum (gdbarch, RL78_PC_REGNUM); 1437 set_gdbarch_sp_regnum (gdbarch, RL78_SP_REGNUM); 1438 set_gdbarch_pseudo_register_read (gdbarch, rl78_pseudo_register_read); 1439 set_gdbarch_deprecated_pseudo_register_write (gdbarch, 1440 rl78_pseudo_register_write); 1441 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rl78_dwarf_reg_to_regnum); 1442 set_gdbarch_register_reggroup_p (gdbarch, rl78_register_reggroup_p); 1443 set_gdbarch_register_sim_regno (gdbarch, rl78_register_sim_regno); 1444 1445 /* Data types. */ 1446 set_gdbarch_char_signed (gdbarch, 0); 1447 set_gdbarch_short_bit (gdbarch, 16); 1448 set_gdbarch_int_bit (gdbarch, 16); 1449 set_gdbarch_long_bit (gdbarch, 32); 1450 set_gdbarch_long_long_bit (gdbarch, 64); 1451 set_gdbarch_ptr_bit (gdbarch, 16); 1452 set_gdbarch_addr_bit (gdbarch, 32); 1453 set_gdbarch_dwarf2_addr_size (gdbarch, 4); 1454 set_gdbarch_float_bit (gdbarch, 32); 1455 set_gdbarch_float_format (gdbarch, floatformats_ieee_single); 1456 set_gdbarch_double_bit (gdbarch, 32); 1457 set_gdbarch_long_double_bit (gdbarch, 64); 1458 set_gdbarch_double_format (gdbarch, floatformats_ieee_single); 1459 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); 1460 set_gdbarch_pointer_to_address (gdbarch, rl78_pointer_to_address); 1461 set_gdbarch_address_to_pointer (gdbarch, rl78_address_to_pointer); 1462 set_gdbarch_addr_bits_remove (gdbarch, rl78_addr_bits_remove); 1463 1464 /* Breakpoints. */ 1465 set_gdbarch_breakpoint_kind_from_pc (gdbarch, rl78_breakpoint::kind_from_pc); 1466 set_gdbarch_sw_breakpoint_from_kind (gdbarch, rl78_breakpoint::bp_from_kind); 1467 set_gdbarch_decr_pc_after_break (gdbarch, 1); 1468 1469 /* Frames, prologues, etc. */ 1470 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 1471 set_gdbarch_skip_prologue (gdbarch, rl78_skip_prologue); 1472 set_gdbarch_unwind_pc (gdbarch, rl78_unwind_pc); 1473 set_gdbarch_frame_align (gdbarch, rl78_frame_align); 1474 1475 dwarf2_append_unwinders (gdbarch); 1476 frame_unwind_append_unwinder (gdbarch, &rl78_unwind); 1477 1478 /* Dummy frames, return values. */ 1479 set_gdbarch_dummy_id (gdbarch, rl78_dummy_id); 1480 set_gdbarch_push_dummy_call (gdbarch, rl78_push_dummy_call); 1481 set_gdbarch_return_value (gdbarch, rl78_return_value); 1482 1483 /* Virtual tables. */ 1484 set_gdbarch_vbit_in_delta (gdbarch, 1); 1485 1486 return gdbarch; 1487 } 1488 1489 /* Register the above initialization routine. */ 1490 1491 void _initialize_rl78_tdep (); 1492 void 1493 _initialize_rl78_tdep () 1494 { 1495 gdbarch_register (bfd_arch_rl78, rl78_gdbarch_init); 1496 } 1497
Indexes created Sun Mar 01 05:31:48 UTC 2026