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      1 /* Common Blackfin device stuff.
      2 
      3    Copyright (C) 2010-2024 Free Software Foundation, Inc.
      4    Contributed by Analog Devices, Inc.
      5 
      6    This file is part of simulators.
      7 
      8    This program is free software; you can redistribute it and/or modify
      9    it under the terms of the GNU General Public License as published by
     10    the Free Software Foundation; either version 3 of the License, or
     11    (at your option) any later version.
     12 
     13    This program is distributed in the hope that it will be useful,
     14    but WITHOUT ANY WARRANTY; without even the implied warranty of
     15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     16    GNU General Public License for more details.
     17 
     18    You should have received a copy of the GNU General Public License
     19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
     20 
     21 #ifndef DEVICES_H
     22 #define DEVICES_H
     23 
     24 #include "hw-base.h"
     25 #include "hw-main.h"
     26 #include "hw-device.h"
     27 #include "hw-tree.h"
     28 
     29 #include "bfin-sim.h"
     30 
     31 /* We keep the same initial structure layout with DMA enabled devices.  */
     32 struct dv_bfin {
     33   bu32 base;
     34   struct hw *dma_master;
     35   bool acked;
     36 };
     37 
     38 #define BFIN_MMR_16(mmr) mmr, __pad_##mmr
     39 
     40 /* Most peripherals have either one interrupt or these three.  */
     41 #define DV_PORT_TX   0
     42 #define DV_PORT_RX   1
     43 #define DV_PORT_STAT 2
     44 
     45 unsigned int dv_get_bus_num (struct hw *);
     46 
     47 static inline bu8 dv_load_1 (const void *ptr)
     49 {
     50   const unsigned char *c = ptr;
     51   return c[0];
     52 }
     53 
     54 static inline void dv_store_1 (void *ptr, bu8 val)
     55 {
     56   unsigned char *c = ptr;
     57   c[0] = val;
     58 }
     59 
     60 static inline bu16 dv_load_2 (const void *ptr)
     61 {
     62   const unsigned char *c = ptr;
     63   return (c[1] << 8) | dv_load_1 (ptr);
     64 }
     65 
     66 static inline void dv_store_2 (void *ptr, bu16 val)
     67 {
     68   unsigned char *c = ptr;
     69   c[1] = val >> 8;
     70   dv_store_1 (ptr, val);
     71 }
     72 
     73 static inline bu32 dv_load_4 (const void *ptr)
     74 {
     75   const unsigned char *c = ptr;
     76   return (c[3] << 24) | (c[2] << 16) | dv_load_2 (ptr);
     77 }
     78 
     79 static inline void dv_store_4 (void *ptr, bu32 val)
     80 {
     81   unsigned char *c = ptr;
     82   c[3] = val >> 24;
     83   c[2] = val >> 16;
     84   dv_store_2 (ptr, val);
     85 }
     86 
     87 /* Helpers for MMRs where only the specified bits are W1C.  The
     89    rest are left unmodified.  */
     90 #define dv_w1c(ptr, val, bits) (*(ptr) &= ~((val) & (bits)))
     91 static inline void dv_w1c_2 (bu16 *ptr, bu16 val, bu16 bits)
     92 {
     93   dv_w1c (ptr, val, bits);
     94 }
     95 static inline void dv_w1c_4 (bu32 *ptr, bu32 val, bu32 bits)
     96 {
     97   dv_w1c (ptr, val, bits);
     98 }
     99 
    100 /* Helpers for MMRs where all bits are RW except for the specified
    101    bits -- those ones are W1C.  */
    102 #define dv_w1c_partial(ptr, val, bits) \
    103   (*(ptr) = ((val) | (*(ptr) & (bits))) & ~((val) & (bits)))
    104 static inline void dv_w1c_2_partial (bu16 *ptr, bu16 val, bu16 bits)
    105 {
    106   dv_w1c_partial (ptr, val, bits);
    107 }
    108 static inline void dv_w1c_4_partial (bu32 *ptr, bu32 val, bu32 bits)
    109 {
    110   dv_w1c_partial (ptr, val, bits);
    111 }
    112 
    113 /* XXX: Grubbing around in device internals is probably wrong, but
    115         until someone shows me what's right ...  */
    116 static inline struct hw *
    117 dv_get_device (SIM_CPU *cpu, const char *device_name)
    118 {
    119   SIM_DESC sd = CPU_STATE (cpu);
    120   void *root = STATE_HW (sd);
    121   return hw_tree_find_device (root, device_name);
    122 }
    123 
    124 static inline void *
    125 dv_get_state (SIM_CPU *cpu, const char *device_name)
    126 {
    127   return hw_data (dv_get_device (cpu, device_name));
    128 }
    129 
    130 #define DV_STATE(cpu, dv) dv_get_state (cpu, "/core/bfin_"#dv)
    131 
    132 #define DV_STATE_CACHED(cpu, dv) \
    133   ({ \
    134     struct bfin_##dv *__##dv = BFIN_CPU_STATE.dv##_cache; \
    135     if (!__##dv) \
    136       BFIN_CPU_STATE.dv##_cache = __##dv = dv_get_state (cpu, "/core/bfin_"#dv); \
    137     __##dv; \
    138   })
    139 
    140 void dv_bfin_mmr_invalid (struct hw *, address_word, unsigned nr_bytes, bool write);
    142 bool dv_bfin_mmr_require (struct hw *, address_word, unsigned nr_bytes, unsigned size, bool write);
    143 /* For 32-bit memory mapped registers that allow 16-bit or 32-bit access.  */
    144 bool dv_bfin_mmr_require_16_32 (struct hw *, address_word, unsigned nr_bytes, bool write);
    145 /* For 32-bit memory mapped registers that only allow 16-bit access.  */
    146 #define dv_bfin_mmr_require_16(hw, addr, nr_bytes, write) dv_bfin_mmr_require (hw, addr, nr_bytes, 2, write)
    147 /* For 32-bit memory mapped registers that only allow 32-bit access.  */
    148 #define dv_bfin_mmr_require_32(hw, addr, nr_bytes, write) dv_bfin_mmr_require (hw, addr, nr_bytes, 4, write)
    149 
    150 #define HW_TRACE_WRITE() \
    152   HW_TRACE ((me, "write 0x%08lx (%s) length %u with 0x%x", \
    153 	     (unsigned long) addr, mmr_name (mmr_off), nr_bytes, value))
    154 #define HW_TRACE_READ() \
    155   HW_TRACE ((me, "read 0x%08lx (%s) length %u", \
    156 	     (unsigned long) addr, mmr_name (mmr_off), nr_bytes))
    157 
    158 #define HW_TRACE_DMA_WRITE() \
    159   HW_TRACE ((me, "dma write 0x%08lx length %u", \
    160 	     (unsigned long) addr, nr_bytes))
    161 #define HW_TRACE_DMA_READ() \
    162   HW_TRACE ((me, "dma read 0x%08lx length %u", \
    163 	     (unsigned long) addr, nr_bytes))
    164 
    165 #endif
    166