1 // -*- C -*- 2 3 // Simulator definition for the MIPS DSP REV 2 ASE. 4 // Copyright (C) 2007-2025 Free Software Foundation, Inc. 5 // Contributed by MIPS Technologies, Inc. 6 // Written by Chao-ying Fu (fu (a] mips.com). 7 // 8 // This file is part of the MIPS sim 9 // 10 // This program is free software; you can redistribute it and/or modify 11 // it under the terms of the GNU General Public License as published by 12 // the Free Software Foundation; either version 3 of the License, or 13 // (at your option) any later version. 14 // 15 // This program is distributed in the hope that it will be useful, 16 // but WITHOUT ANY WARRANTY; without even the implied warranty of 17 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 // GNU General Public License for more details. 19 // 20 // You should have received a copy of the GNU General Public License 21 // along with this program. If not, see <http://www.gnu.org/licenses/>. 22 23 24 // op: 0 = ADD, 1 = SUB 25 // sat: 0 = no saturation, 1 = saturation 26 :function:::void:do_u_ph_op:int rd, int rs, int rt, int op, int sat 27 { 28 int i; 29 uint32_t h0; 30 uint16_t h1, h2; 31 uint32_t v1 = GPR[rs]; 32 uint32_t v2 = GPR[rt]; 33 uint32_t result = 0; 34 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) 35 { 36 h1 = (uint16_t)(v1 & 0xffff); 37 h2 = (uint16_t)(v2 & 0xffff); 38 if (op == 0) // ADD 39 h0 = (uint32_t)h1 + (uint32_t)h2; 40 else // SUB 41 h0 = (uint32_t)h1 - (uint32_t)h2; 42 if (op == 0 && (h0 > (uint32_t)0x0000ffff)) // ADD SAT 43 { 44 DSPCR |= DSPCR_OUFLAG4; 45 if (sat == 1) 46 h0 = 0xffff; 47 } 48 else if (op == 1 && h1 < h2) // SUB SAT 49 { 50 DSPCR |= DSPCR_OUFLAG4; 51 if (sat == 1) 52 h0 = 0x0; 53 } 54 result |= ((uint32_t)((uint16_t)h0) << i); 55 } 56 GPR[rd] = EXTEND32 (result); 57 } 58 59 // op: 0 = ADD, 1 = SUB 60 // round: 0 = no rounding, 1 = rounding 61 :function:::void:do_uh_qb_op:int rd, int rs, int rt, int op, int round 62 { 63 int i; 64 uint32_t h0; 65 uint8_t h1, h2; 66 uint32_t v1 = GPR[rs]; 67 uint32_t v2 = GPR[rt]; 68 uint32_t result = 0; 69 for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8) 70 { 71 h1 = (uint8_t)(v1 & 0xff); 72 h2 = (uint8_t)(v2 & 0xff); 73 if (op == 0) // ADD 74 h0 = (uint32_t)h1 + (uint32_t)h2; 75 else // SUB 76 h0 = (uint32_t)h1 - (uint32_t)h2; 77 if (round == 1) 78 h0 = (h0 + 1) >> 1; 79 else 80 h0 = h0 >> 1; 81 result |= ((uint32_t)((uint8_t)h0) << i); 82 } 83 GPR[rd] = EXTEND32 (result); 84 } 85 86 // op: 0 = EQ, 1 = LT, 2 = LE 87 :function:::void:do_qb_cmpgdu:int rd, int rs, int rt, int op 88 { 89 int i, j; 90 uint32_t v1 = GPR[rs]; 91 uint32_t v2 = GPR[rt]; 92 uint8_t h1, h2; 93 uint32_t result = 0; 94 uint32_t mask; 95 for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8) 96 { 97 h1 = (uint8_t)(v1 & 0xff); 98 h2 = (uint8_t)(v2 & 0xff); 99 mask = ~(1 << (DSPCR_CCOND_SHIFT + j)); 100 DSPCR &= mask; 101 if (op == 0) // EQ 102 { 103 result |= ((h1 == h2) << j); 104 DSPCR |= ((h1 == h2) << (DSPCR_CCOND_SHIFT + j)); 105 } 106 else if (op == 1) // LT 107 { 108 result |= ((h1 < h2) << j); 109 DSPCR |= ((h1 < h2) << (DSPCR_CCOND_SHIFT + j)); 110 } 111 else // LE 112 { 113 result |= ((h1 <= h2) << j); 114 DSPCR |= ((h1 <= h2) << (DSPCR_CCOND_SHIFT + j)); 115 } 116 } 117 GPR[rd] = EXTEND32 (result); 118 } 119 120 // op: 0 = DPA 1 = DPS 121 :function:::void:do_w_ph_dot_product:int ac, int rs, int rt, int op 122 { 123 int i; 124 uint32_t v1 = GPR[rs]; 125 uint32_t v2 = GPR[rt]; 126 int16_t h1, h2; 127 int32_t result; 128 uint32_t lo = DSPLO(ac); 129 uint32_t hi = DSPHI(ac); 130 int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); 131 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) 132 { 133 h1 = (int16_t)(v1 & 0xffff); 134 h2 = (int16_t)(v2 & 0xffff); 135 result = (int32_t)h1 * (int32_t)h2; 136 if (op == 0) // DPA 137 prod += (int64_t)result; 138 else // DPS 139 prod -= (int64_t)result; 140 } 141 DSPLO(ac) = EXTEND32 (prod); 142 DSPHI(ac) = EXTEND32 (prod >> 32); 143 } 144 145 // round: 0 = no rounding, 1 = rounding 146 :function:::void:do_w_mulq:int rd, int rs, int rt, int round 147 { 148 uint32_t v1 = GPR[rs]; 149 uint32_t v2 = GPR[rt]; 150 int32_t w1, w2; 151 int64_t prod; 152 uint32_t result; 153 w1 = (int32_t) v1; 154 w2 = (int32_t) v2; 155 if (w1 == (int32_t) 0x80000000 && w2 == (int32_t) 0x80000000) 156 { 157 DSPCR |= DSPCR_OUFLAG5; 158 prod = 0x7fffffff; 159 } 160 else 161 { 162 prod = ((int64_t) w1 * (int64_t) w2) << 1; 163 if (round == 1) 164 prod += 0x0000000080000000LL; 165 prod = prod >> 32; 166 } 167 result = (uint32_t) prod; 168 GPR[rd] = EXTEND32 (result); 169 } 170 171 // round: 0 = no rounding, 1 = rounding 172 :function:::void:do_precr_sra:int rt, int rs, int sa, int round 173 { 174 uint32_t v1 = GPR[rt]; 175 uint32_t v2 = GPR[rs]; 176 int32_t w1 = (int32_t) v1; 177 int32_t w2 = (int32_t) v2; 178 int32_t result; 179 if (sa != 0) 180 { 181 if (round == 1 && (w1 & (1 << (sa - 1)))) 182 w1 = (w1 >> sa) + 1; 183 else 184 w1 = w1 >> sa; 185 186 if (round == 1 && (w2 & (1 << (sa - 1)))) 187 w2 = (w2 >> sa) + 1; 188 else 189 w2 = w2 >> sa; 190 } 191 result = (w1 << 16) | (w2 & 0xffff); 192 GPR[rt] = EXTEND32 (result); 193 } 194 195 // round: 0 = no rounding, 1 = rounding 196 :function:::void:do_qb_shra:int rd, int rt, int shift, int round 197 { 198 int i; 199 int8_t q0; 200 uint32_t v1 = GPR[rt]; 201 uint32_t result = 0; 202 for (i = 0; i < 32; i += 8, v1 >>= 8) 203 { 204 q0 = (int8_t)(v1 & 0xff); 205 if (shift != 0) 206 { 207 if (round == 1 && (q0 & (1 << (shift - 1)))) 208 q0 = (q0 >> shift) + 1; 209 else 210 q0 = q0 >> shift; 211 } 212 result |= ((uint32_t)((uint8_t)q0) << i); 213 } 214 GPR[rd] = EXTEND32 (result); 215 } 216 217 :function:::void:do_ph_shrl:int rd, int rt, int shift 218 { 219 int i; 220 uint16_t h0; 221 uint32_t v1 = GPR[rt]; 222 uint32_t result = 0; 223 for (i = 0; i < 32; i += 16, v1 >>= 16) 224 { 225 h0 = (uint16_t)(v1 & 0xffff); 226 h0 = h0 >> shift; 227 result |= ((uint32_t)h0 << i); 228 } 229 GPR[rd] = EXTEND32 (result); 230 } 231 232 // op: 0 = ADD, 1 = SUB 233 // round: 0 = no rounding, 1 = rounding 234 :function:::void:do_qh_ph_op:int rd, int rs, int rt, int op, int round 235 { 236 int i; 237 int32_t h0; 238 int16_t h1, h2; 239 uint32_t v1 = GPR[rs]; 240 uint32_t v2 = GPR[rt]; 241 uint32_t result = 0; 242 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) 243 { 244 h1 = (int16_t)(v1 & 0xffff); 245 h2 = (int16_t)(v2 & 0xffff); 246 if (op == 0) // ADD 247 h0 = (int32_t)h1 + (int32_t)h2; 248 else // SUB 249 h0 = (int32_t)h1 - (int32_t)h2; 250 if (round == 1) 251 h0 = (h0 + 1) >> 1; 252 else 253 h0 = h0 >> 1; 254 result |= ((uint32_t)((uint16_t)h0) << i); 255 } 256 GPR[rd] = EXTEND32 (result); 257 } 258 259 // op: 0 = ADD, 1 = SUB 260 // round: 0 = no rounding, 1 = rounding 261 :function:::void:do_qh_w_op:int rd, int rs, int rt, int op, int round 262 { 263 int64_t v0; 264 int32_t v1 = (int32_t)GPR[rs]; 265 int32_t v2 = (int32_t)GPR[rt]; 266 if (op == 0) // ADD 267 v0 = (int64_t)v1 + (int64_t)v2; 268 else // SUB 269 v0 = (int64_t)v1 - (int64_t)v2; 270 if (round == 1) 271 v0 = (v0 + 1) >> 1; 272 else 273 v0 = v0 >> 1; 274 GPR[rd] = EXTEND32 (v0); 275 } 276 277 // op: 0 = DPAX, 1 = DPSX 278 :function:::void:do_x_w_ph_dot_product:int ac, int rs, int rt, int op 279 { 280 int i; 281 uint32_t v1 = GPR[rs]; 282 uint32_t v2 = GPR[rt]; 283 int16_t h1, h2; 284 int32_t result; 285 uint32_t lo = DSPLO(ac); 286 uint32_t hi = DSPHI(ac); 287 int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); 288 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16) 289 { 290 h1 = (int16_t)(v1 & 0xffff); 291 h2 = (int16_t)((v2 & 0xffff0000) >> 16); 292 result = (int32_t)h1 * (int32_t)h2; 293 if (op == 0) // DPAX 294 prod += (int64_t)result; 295 else // DPSX 296 prod -= (int64_t)result; 297 } 298 DSPLO(ac) = EXTEND32 (prod); 299 DSPHI(ac) = EXTEND32 (prod >> 32); 300 } 301 302 // op: 0 = DPAQX, 1 = DPSQX 303 // sat: 0 = no saturation, 1 = saturation of the accumulator 304 :function:::void:do_qx_w_ph_dot_product:int ac, int rs, int rt, int op, int sat 305 { 306 int i; 307 uint32_t v1 = GPR[rs]; 308 uint32_t v2 = GPR[rt]; 309 int16_t h1, h2; 310 int32_t result; 311 uint32_t lo = DSPLO(ac); 312 uint32_t hi = DSPHI(ac); 313 int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); 314 int64_t max, min; 315 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16) 316 { 317 h1 = (int16_t)(v1 & 0xffff); 318 h2 = (int16_t)((v2 & 0xffff0000) >> 16); 319 if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000) 320 { 321 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); 322 result = 0x7fffffff; 323 } 324 else 325 result = ((int32_t)h1 * (int32_t)h2) << 1; 326 if (op == 0) // DPAQX 327 prod += (int64_t)result; 328 else // DPSQX 329 prod -= (int64_t)result; 330 } 331 // Saturation on the accumulator. 332 if (sat == 1) 333 { 334 max = (int64_t) 0x7fffffffLL; 335 min = (int64_t) 0xffffffff80000000LL; 336 if (prod > max) 337 { 338 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); 339 prod = max; 340 } 341 else if (prod < min) 342 { 343 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); 344 prod = min; 345 } 346 } 347 DSPLO(ac) = EXTEND32 (prod); 348 DSPHI(ac) = EXTEND32 (prod >> 32); 349 } 350 351 011111,00000,5.RT,5.RD,00001,010010:SPECIAL3:32::ABSQ_S.QB 352 "absq_s.qb r<RD>, r<RT>" 353 *dsp2: 354 { 355 do_qb_s_absq (SD_, RD, RT); 356 } 357 358 011111,5.RS,5.RT,5.RD,01000,010000:SPECIAL3:32::ADDU.PH 359 "addu.ph r<RD>, r<RS>, r<RT>" 360 *dsp2: 361 { 362 do_u_ph_op (SD_, RD, RS, RT, 0, 0); 363 } 364 365 011111,5.RS,5.RT,5.RD,01100,010000:SPECIAL3:32::ADDU_S.PH 366 "addu_s.ph r<RD>, r<RS>, r<RT>" 367 *dsp2: 368 { 369 do_u_ph_op (SD_, RD, RS, RT, 0, 1); 370 } 371 372 011111,5.RS,5.RT,5.RD,00000,011000:SPECIAL3:32::ADDUH.QB 373 "adduh.qb r<RD>, r<RS>, r<RT>" 374 *dsp2: 375 { 376 do_uh_qb_op (SD_, RD, RS, RT, 0, 0); 377 } 378 379 011111,5.RS,5.RT,5.RD,00010,011000:SPECIAL3:32::ADDUH_R.QB 380 "adduh_r.qb r<RD>, r<RS>, r<RT>" 381 *dsp2: 382 { 383 do_uh_qb_op (SD_, RD, RS, RT, 0, 1); 384 } 385 386 011111,5.RS,5.RT,5.SA,00000,110001:SPECIAL3:32::APPEND 387 "append r<RT>, r<RS>, <SA>" 388 *dsp2: 389 { 390 do_append (SD_, RT, RS, SA); 391 } 392 393 011111,5.RS,5.RT,000,2.BP,10000,110001:SPECIAL3:32::BALIGN 394 "balign r<RT>, r<RS>, <BP>" 395 *dsp2: 396 { 397 do_balign (SD_, RT, RS, BP); 398 } 399 400 011111,5.RS,5.RT,5.RD,11000,010001:SPECIAL3:32::CMPGDU.EQ.QB 401 "cmpgdu.eq.qb r<RD>, r<RS>, r<RT>" 402 *dsp2: 403 { 404 do_qb_cmpgdu (SD_, RD, RS, RT, 0); 405 } 406 407 011111,5.RS,5.RT,5.RD,11001,010001:SPECIAL3:32::CMPGDU.LT.QB 408 "cmpgdu.lt.qb r<RD>, r<RS>, r<RT>" 409 *dsp2: 410 { 411 do_qb_cmpgdu (SD_, RD, RS, RT, 1); 412 } 413 414 011111,5.RS,5.RT,5.RD,11010,010001:SPECIAL3:32::CMPGDU.LE.QB 415 "cmpgdu.le.qb r<RD>, r<RS>, r<RT>" 416 *dsp2: 417 { 418 do_qb_cmpgdu (SD_, RD, RS, RT, 2); 419 } 420 421 011111,5.RS,5.RT,000,2.AC,00000,110000:SPECIAL3:32::DPA.W.PH 422 "dpa.w.ph ac<AC>, r<RS>, r<RT>" 423 *dsp2: 424 { 425 do_w_ph_dot_product (SD_, AC, RS, RT, 0); 426 } 427 428 011111,5.RS,5.RT,000,2.AC,00001,110000:SPECIAL3:32::DPS.W.PH 429 "dps.w.ph ac<AC>, r<RS>, r<RT>" 430 *dsp2: 431 { 432 do_w_ph_dot_product (SD_, AC, RS, RT, 1); 433 } 434 435 011111,5.RS,5.RT,5.RD,01100,011000:SPECIAL3:32::MUL.PH 436 "mul.ph r<RD>, r<RS>, r<RT>" 437 *dsp2: 438 { 439 do_ph_op (SD_, RD, RS, RT, 2, 0); 440 } 441 442 011111,5.RS,5.RT,5.RD,01110,011000:SPECIAL3:32::MUL_S.PH 443 "mul_s.ph r<RD>, r<RS>, r<RT>" 444 *dsp2: 445 { 446 do_ph_op (SD_, RD, RS, RT, 2, 1); 447 } 448 449 011111,5.RS,5.RT,5.RD,10111,011000:SPECIAL3:32::MULQ_RS.W 450 "mulq_rs.w r<RD>, r<RS>, r<RT>" 451 *dsp2: 452 { 453 do_w_mulq (SD_, RD, RS, RT, 1); 454 } 455 456 011111,5.RS,5.RT,5.RD,11110,010000:SPECIAL3:32::MULQ_S.PH 457 "mulq_s.ph r<RD>, r<RS>, r<RT>" 458 *dsp2: 459 { 460 do_ph_mulq (SD_, RD, RS, RT, 0); 461 } 462 463 011111,5.RS,5.RT,5.RD,10110,011000:SPECIAL3:32::MULQ_S.W 464 "mulq_s.w r<RD>, r<RS>, r<RT>" 465 *dsp2: 466 { 467 do_w_mulq (SD_, RD, RS, RT, 0); 468 } 469 470 011111,5.RS,5.RT,000,2.AC,00010,110000:SPECIAL3:32::MULSA.W.PH 471 "mulsa.w.ph ac<AC>, r<RS>, r<RT>" 472 *dsp2: 473 { 474 do_ph_w_mulsa (SD_, AC, RS, RT); 475 } 476 477 011111,5.RS,5.RT,5.RD,01101,010001:SPECIAL3:32::PRECR.QB.PH 478 "precr.qb.ph r<RD>, r<RS>, r<RT>" 479 *dsp2: 480 { 481 do_ph_qb_precr (SD_, RD, RS, RT); 482 } 483 484 011111,5.RS,5.RT,5.SA,11110,010001:SPECIAL3:32::PRECR_SRA.PH.W 485 "precr_sra.ph.w r<RT>, r<RS>, <SA>" 486 *dsp2: 487 { 488 do_precr_sra (SD_, RT, RS, SA, 0); 489 } 490 491 011111,5.RS,5.RT,5.SA,11111,010001:SPECIAL3:32::PRECR_SRA_R.PH.W 492 "precr_sra_r.ph.w r<RT>, r<RS>, <SA>" 493 *dsp2: 494 { 495 do_precr_sra (SD_, RT, RS, SA, 1); 496 } 497 498 011111,5.RS,5.RT,5.SA,00001,110001:SPECIAL3:32::PREPEND 499 "prepend r<RT>, r<RS>, <SA>" 500 *dsp2: 501 { 502 do_prepend (SD_, RT, RS, SA); 503 } 504 505 011111,00,3.SHIFT3,5.RT,5.RD,00100,010011:SPECIAL3:32::SHRA.QB 506 "shra.qb r<RD>, r<RT>, <SHIFT3>" 507 *dsp2: 508 { 509 do_qb_shra (SD_, RD, RT, SHIFT3, 0); 510 } 511 512 011111,00,3.SHIFT3,5.RT,5.RD,00101,010011:SPECIAL3:32::SHRA_R.QB 513 "shra_r.qb r<RD>, r<RT>, <SHIFT3>" 514 *dsp2: 515 { 516 do_qb_shra (SD_, RD, RT, SHIFT3, 1); 517 } 518 519 011111,5.RS,5.RT,5.RD,00110,010011:SPECIAL3:32::SHRAV.QB 520 "shrav.qb r<RD>, r<RT>, r<RS>" 521 *dsp2: 522 { 523 do_qb_shrav (SD_, RD, RT, RS, 0); 524 } 525 526 011111,5.RS,5.RT,5.RD,00111,010011:SPECIAL3:32::SHRAV_R.QB 527 "shrav_r.qb r<RD>, r<RT>, r<RS>" 528 *dsp2: 529 { 530 do_qb_shrav (SD_, RD, RT, RS, 1); 531 } 532 533 011111,0,4.SHIFT4,5.RT,5.RD,11001,010011:SPECIAL3:32::SHRL.PH 534 "shrl.ph r<RD>, r<RT>, <SHIFT4>" 535 *dsp2: 536 { 537 do_ph_shrl (SD_, RD, RT, SHIFT4); 538 } 539 540 011111,5.RS,5.RT,5.RD,11011,010011:SPECIAL3:32::SHRLV.PH 541 "shrlv.ph r<RD>, r<RT>, r<RS>" 542 *dsp2: 543 { 544 do_ph_shrlv (SD_, RD, RT, RS); 545 } 546 547 011111,5.RS,5.RT,5.RD,01001,010000:SPECIAL3:32::SUBU.PH 548 "subu.ph r<RD>, r<RS>, r<RT>" 549 *dsp2: 550 { 551 do_u_ph_op (SD_, RD, RS, RT, 1, 0); 552 } 553 554 011111,5.RS,5.RT,5.RD,01101,010000:SPECIAL3:32::SUBU_S.PH 555 "subu_s.ph r<RD>, r<RS>, r<RT>" 556 *dsp2: 557 { 558 do_u_ph_op (SD_, RD, RS, RT, 1, 1); 559 } 560 561 011111,5.RS,5.RT,5.RD,00001,011000:SPECIAL3:32::SUBUH.QB 562 "subuh.qb r<RD>, r<RS>, r<RT>" 563 *dsp2: 564 { 565 do_uh_qb_op (SD_, RD, RS, RT, 1, 0); 566 } 567 568 011111,5.RS,5.RT,5.RD,00011,011000:SPECIAL3:32::SUBUH_R.QB 569 "subuh_r.qb r<RD>, r<RS>, r<RT>" 570 *dsp2: 571 { 572 do_uh_qb_op (SD_, RD, RS, RT, 1, 1); 573 } 574 575 011111,5.RS,5.RT,5.RD,01000,011000:SPECIAL3:32::ADDQH.PH 576 "addqh.ph r<RD>, r<RS>, r<RT>" 577 *dsp2: 578 { 579 do_qh_ph_op (SD_, RD, RS, RT, 0, 0); 580 } 581 582 011111,5.RS,5.RT,5.RD,01010,011000:SPECIAL3:32::ADDQH_R.PH 583 "addqh_r.ph r<RD>, r<RS>, r<RT>" 584 *dsp2: 585 { 586 do_qh_ph_op (SD_, RD, RS, RT, 0, 1); 587 } 588 589 011111,5.RS,5.RT,5.RD,10000,011000:SPECIAL3:32::ADDQH.W 590 "addqh.w r<RD>, r<RS>, r<RT>" 591 *dsp2: 592 { 593 do_qh_w_op (SD_, RD, RS, RT, 0, 0); 594 } 595 596 011111,5.RS,5.RT,5.RD,10010,011000:SPECIAL3:32::ADDQH_R.W 597 "addqh_r.w r<RD>, r<RS>, r<RT>" 598 *dsp2: 599 { 600 do_qh_w_op (SD_, RD, RS, RT, 0, 1); 601 } 602 603 011111,5.RS,5.RT,5.RD,01001,011000:SPECIAL3:32::SUBQH.PH 604 "subqh.ph r<RD>, r<RS>, r<RT>" 605 *dsp2: 606 { 607 do_qh_ph_op (SD_, RD, RS, RT, 1, 0); 608 } 609 610 011111,5.RS,5.RT,5.RD,01011,011000:SPECIAL3:32::SUBQH_R.PH 611 "subqh_r.ph r<RD>, r<RS>, r<RT>" 612 *dsp2: 613 { 614 do_qh_ph_op (SD_, RD, RS, RT, 1, 1); 615 } 616 617 011111,5.RS,5.RT,5.RD,10001,011000:SPECIAL3:32::SUBQH.W 618 "subqh.w r<RD>, r<RS>, r<RT>" 619 *dsp2: 620 { 621 do_qh_w_op (SD_, RD, RS, RT, 1, 0); 622 } 623 624 011111,5.RS,5.RT,5.RD,10011,011000:SPECIAL3:32::SUBQH_R.W 625 "subqh_r.w r<RD>, r<RS>, r<RT>" 626 *dsp2: 627 { 628 do_qh_w_op (SD_, RD, RS, RT, 1, 1); 629 } 630 631 011111,5.RS,5.RT,000,2.AC,01000,110000:SPECIAL3:32::DPAX.W.PH 632 "dpax.w.ph ac<AC>, r<RS>, r<RT>" 633 *dsp2: 634 { 635 do_x_w_ph_dot_product (SD_, AC, RS, RT, 0); 636 } 637 638 011111,5.RS,5.RT,000,2.AC,01001,110000:SPECIAL3:32::DPSX.W.PH 639 "dpsx.w.ph ac<AC>, r<RS>, r<RT>" 640 *dsp2: 641 { 642 do_x_w_ph_dot_product (SD_, AC, RS, RT, 1); 643 } 644 645 011111,5.RS,5.RT,000,2.AC,11000,110000:SPECIAL3:32::DPAQX_S.W.PH 646 "dpaqx_s.w.ph ac<AC>, r<RS>, r<RT>" 647 *dsp2: 648 { 649 do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 0); 650 } 651 652 011111,5.RS,5.RT,000,2.AC,11010,110000:SPECIAL3:32::DPAQX_SA.W.PH 653 "dpaqx_sa.w.ph ac<AC>, r<RS>, r<RT>" 654 *dsp2: 655 { 656 do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 1); 657 } 658 659 011111,5.RS,5.RT,000,2.AC,11001,110000:SPECIAL3:32::DPSQX_S.W.PH 660 "dpsqx_s.w.ph ac<AC>, r<RS>, r<RT>" 661 *dsp2: 662 { 663 do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 0); 664 } 665 666 011111,5.RS,5.RT,000,2.AC,11011,110000:SPECIAL3:32::DPSQX_SA.W.PH 667 "dpsqx_sa.w.ph ac<AC>, r<RS>, r<RT>" 668 *dsp2: 669 { 670 do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 1); 671 } 672
Indexes created Wed Sep 16 00:24:39 UTC 2026