1 # Intel(r) Wireless MMX(tm) technology testcase for WPACK 2 # mach: xscale 3 # as: -mcpu=xscale+iwmmxt 4 5 .include "testutils.inc" 6 7 start 8 9 .global wpack 10 wpack: 11 # Enable access to CoProcessors 0 & 1 before 12 # we attempt these instructions. 13 14 mvi_h_gr r1, 3 15 mcr p15, 0, r1, cr15, cr1, 0 16 17 # Test Halfword, Unsigned Saturation, Packing 18 19 mvi_h_gr r0, 0x12345678 20 mvi_h_gr r1, 0x9abcdef0 21 mvi_h_gr r2, 0x11111111 22 mvi_h_gr r3, 0x00000000 23 mvi_h_gr r4, 0 24 mvi_h_gr r5, 0 25 26 tmcrr wr0, r0, r1 27 tmcrr wr1, r2, r3 28 tmcrr wr2, r4, r5 29 30 wpackhus wr2, wr0, wr1 31 32 tmrrc r0, r1, wr0 33 tmrrc r2, r3, wr1 34 tmrrc r4, r5, wr2 35 36 test_h_gr r0, 0x12345678 37 test_h_gr r1, 0x9abcdef0 38 test_h_gr r2, 0x11111111 39 test_h_gr r3, 0x00000000 40 test_h_gr r4, 0x0000ffff 41 test_h_gr r5, 0x0000ffff 42 43 # Test Halfword, Signed Saturation, Packing 44 45 mvi_h_gr r0, 0x12345678 46 mvi_h_gr r1, 0x9abcdef0 47 mvi_h_gr r2, 0x11111111 48 mvi_h_gr r3, 0x00000000 49 mvi_h_gr r4, 0 50 mvi_h_gr r5, 0 51 52 tmcrr wr0, r0, r1 53 tmcrr wr1, r2, r3 54 tmcrr wr2, r4, r5 55 56 wpackhss wr2, wr0, wr1 57 58 tmrrc r0, r1, wr0 59 tmrrc r2, r3, wr1 60 tmrrc r4, r5, wr2 61 62 test_h_gr r0, 0x12345678 63 test_h_gr r1, 0x9abcdef0 64 test_h_gr r2, 0x11111111 65 test_h_gr r3, 0x00000000 66 test_h_gr r4, 0x80807f7f 67 test_h_gr r5, 0x00007f7f 68 69 # Test Word, Unsigned Saturation, Packing 70 71 mvi_h_gr r0, 0x12345678 72 mvi_h_gr r1, 0x9abcdef0 73 mvi_h_gr r2, 0x11111111 74 mvi_h_gr r3, 0x00000000 75 mvi_h_gr r4, 0 76 mvi_h_gr r5, 0 77 78 tmcrr wr0, r0, r1 79 tmcrr wr1, r2, r3 80 tmcrr wr2, r4, r5 81 82 wpackwus wr2, wr0, wr1 83 84 tmrrc r0, r1, wr0 85 tmrrc r2, r3, wr1 86 tmrrc r4, r5, wr2 87 88 test_h_gr r0, 0x12345678 89 test_h_gr r1, 0x9abcdef0 90 test_h_gr r2, 0x11111111 91 test_h_gr r3, 0x00000000 92 test_h_gr r4, 0x0000ffff 93 test_h_gr r5, 0x0000ffff 94 95 # Test Word, Signed Saturation, Packing 96 97 mvi_h_gr r0, 0x12345678 98 mvi_h_gr r1, 0x9abcdef0 99 mvi_h_gr r2, 0x11111111 100 mvi_h_gr r3, 0x00000000 101 mvi_h_gr r4, 0 102 mvi_h_gr r5, 0 103 104 tmcrr wr0, r0, r1 105 tmcrr wr1, r2, r3 106 tmcrr wr2, r4, r5 107 108 wpackwss wr2, wr0, wr1 109 110 tmrrc r0, r1, wr0 111 tmrrc r2, r3, wr1 112 tmrrc r4, r5, wr2 113 114 test_h_gr r0, 0x12345678 115 test_h_gr r1, 0x9abcdef0 116 test_h_gr r2, 0x11111111 117 test_h_gr r3, 0x00000000 118 test_h_gr r4, 0x80007fff 119 test_h_gr r5, 0x00007fff 120 121 # Test Double Word, Unsigned Saturation, Packing 122 123 mvi_h_gr r0, 0x12345678 124 mvi_h_gr r1, 0x9abcdef0 125 mvi_h_gr r2, 0x11111111 126 mvi_h_gr r3, 0x00000000 127 mvi_h_gr r4, 0 128 mvi_h_gr r5, 0 129 130 tmcrr wr0, r0, r1 131 tmcrr wr1, r2, r3 132 tmcrr wr2, r4, r5 133 134 wpackdus wr2, wr0, wr1 135 136 tmrrc r0, r1, wr0 137 tmrrc r2, r3, wr1 138 tmrrc r4, r5, wr2 139 140 test_h_gr r0, 0x12345678 141 test_h_gr r1, 0x9abcdef0 142 test_h_gr r2, 0x11111111 143 test_h_gr r3, 0x00000000 144 test_h_gr r4, 0x00000000 145 test_h_gr r5, 0x11111111 146 147 # Test Double Word, Signed Saturation, Packing 148 149 mvi_h_gr r0, 0x12345678 150 mvi_h_gr r1, 0x9abcdef0 151 mvi_h_gr r2, 0x11111111 152 mvi_h_gr r3, 0x00000000 153 mvi_h_gr r4, 0 154 mvi_h_gr r5, 0 155 156 tmcrr wr0, r0, r1 157 tmcrr wr1, r2, r3 158 tmcrr wr2, r4, r5 159 160 wpackdss wr2, wr0, wr1 161 162 tmrrc r0, r1, wr0 163 tmrrc r2, r3, wr1 164 tmrrc r4, r5, wr2 165 166 test_h_gr r0, 0x12345678 167 test_h_gr r1, 0x9abcdef0 168 test_h_gr r2, 0x11111111 169 test_h_gr r3, 0x00000000 170 test_h_gr r4, 0x80000000 171 test_h_gr r5, 0x11111111 172 173 pass 174
Indexes created Sun Jun 28 00:24:58 UTC 2026