1 //Original:/testcases/core/c_alu2op_shadd_1/c_alu2op_shadd_1.dsp 2 // Spec Reference: alu2op shadd 1 3 # mach: bfin 4 5 .include "testutils.inc" 6 start 7 8 9 10 imm32 r0, 0x03417990; 11 imm32 r1, 0x12315678; 12 imm32 r2, 0x23416789; 13 imm32 r3, 0x3451789a; 14 imm32 r4, 0x856189ab; 15 imm32 r5, 0x96719abc; 16 imm32 r6, 0xa781abcd; 17 imm32 r7, 0xb891bcde; 18 R1 = ( R1 + R0 ) << 1; 19 R2 = ( R2 + R0 ) << 1; 20 R3 = ( R3 + R0 ) << 1; 21 R4 = ( R4 + R0 ) << 1; 22 R5 = ( R5 + R0 ) << 1; 23 R6 = ( R6 + R0 ) << 1; 24 R7 = ( R7 + R0 ) << 1; 25 R0 = ( R0 + R0 ) << 1; 26 CHECKREG r0, 0x0D05E640; 27 CHECKREG r1, 0x2AE5A010; 28 CHECKREG r2, 0x4D05C232; 29 CHECKREG r3, 0x6F25E454; 30 CHECKREG r4, 0x11460676; 31 CHECKREG r5, 0x33662898; 32 CHECKREG r6, 0x55864ABA; 33 CHECKREG r7, 0x77A66CDC; 34 35 imm32 r0, 0x03457290; 36 imm32 r1, 0x12345278; 37 imm32 r2, 0x23456289; 38 imm32 r3, 0x3456729a; 39 imm32 r4, 0x856782ab; 40 imm32 r5, 0x967892bc; 41 imm32 r6, 0xa789a2cd; 42 imm32 r7, 0xb89ab2de; 43 R0 = ( R0 + R1 ) << 1; 44 R2 = ( R2 + R1 ) << 1; 45 R3 = ( R3 + R1 ) << 1; 46 R4 = ( R4 + R1 ) << 1; 47 R5 = ( R5 + R1 ) << 1; 48 R6 = ( R6 + R1 ) << 1; 49 R7 = ( R7 + R1 ) << 1; 50 R1 = ( R1 + R1 ) << 1; 51 CHECKREG r0, 0x2AF38A10; 52 CHECKREG r1, 0x48D149E0; 53 CHECKREG r2, 0x6AF36A02; 54 CHECKREG r3, 0x8D158A24; 55 CHECKREG r4, 0x2F37AA46; 56 CHECKREG r5, 0x5159CA68; 57 CHECKREG r6, 0x737BEA8A; 58 CHECKREG r7, 0x959E0AAC; 59 60 imm32 r0, 0x03457930; 61 imm32 r1, 0x12345638; 62 imm32 r2, 0x23456739; 63 imm32 r3, 0x3456783a; 64 imm32 r4, 0x8567893b; 65 imm32 r5, 0x96789a3c; 66 imm32 r6, 0xa789ab3d; 67 imm32 r7, 0xb89abc3e; 68 R0 = ( R0 + R2 ) << 1; 69 R1 = ( R1 + R2 ) << 1; 70 R3 = ( R3 + R2 ) << 1; 71 R4 = ( R4 + R2 ) << 1; 72 R5 = ( R5 + R2 ) << 1; 73 R6 = ( R6 + R2 ) << 1; 74 R7 = ( R7 + R2 ) << 1; 75 R2 = ( R2 + R2 ) << 1; 76 CHECKREG r0, 0x4D15C0D2; 77 CHECKREG r1, 0x6AF37AE2; 78 CHECKREG r2, 0x8D159CE4; 79 CHECKREG r3, 0xAF37BEE6; 80 CHECKREG r4, 0x5159E0E8; 81 CHECKREG r5, 0x737C02EA; 82 CHECKREG r6, 0x959E24EC; 83 CHECKREG r7, 0xB7C046EE; 84 85 imm32 r0, 0x04457990; 86 imm32 r1, 0x14345678; 87 imm32 r2, 0x24456789; 88 imm32 r3, 0x3456789a; 89 imm32 r4, 0x846789ab; 90 imm32 r5, 0x94789abc; 91 imm32 r6, 0xa489abcd; 92 imm32 r7, 0xb49abcde; 93 R0 = ( R0 + R3 ) << 1; 94 R1 = ( R1 + R3 ) << 1; 95 R2 = ( R2 + R3 ) << 1; 96 R4 = ( R4 + R3 ) << 1; 97 R5 = ( R5 + R3 ) << 1; 98 R6 = ( R6 + R3 ) << 1; 99 R7 = ( R7 + R3 ) << 1; 100 R3 = ( R3 + R3 ) << 1; 101 CHECKREG r0, 0x7137E454; 102 CHECKREG r1, 0x91159E24; 103 CHECKREG r2, 0xB137C046; 104 CHECKREG r3, 0xD159E268; 105 CHECKREG r4, 0x717C048A; 106 CHECKREG r5, 0x919E26AC; 107 CHECKREG r6, 0xB1C048CE; 108 CHECKREG r7, 0xD1E26AF0; 109 110 imm32 r0, 0x03417990; 111 imm32 r1, 0x12315678; 112 imm32 r2, 0x23416789; 113 imm32 r3, 0x3451789a; 114 imm32 r4, 0x856189ab; 115 imm32 r5, 0x96719abc; 116 imm32 r6, 0xa781abcd; 117 imm32 r7, 0xb891bcde; 118 R0 = ( R0 + R4 ) << 1; 119 R1 = ( R1 + R4 ) << 1; 120 R2 = ( R2 + R4 ) << 1; 121 R3 = ( R3 + R4 ) << 1; 122 R5 = ( R5 + R4 ) << 1; 123 R6 = ( R6 + R4 ) << 1; 124 R7 = ( R7 + R4 ) << 1; 125 R4 = ( R4 + R4 ) << 1; 126 CHECKREG r0, 0x11460676; 127 CHECKREG r1, 0x2F25C046; 128 CHECKREG r2, 0x5145E268; 129 CHECKREG r3, 0x7366048A; 130 CHECKREG r4, 0x158626AC; 131 CHECKREG r5, 0x37A648CE; 132 CHECKREG r6, 0x59C66AF0; 133 CHECKREG r7, 0x7BE68D12; 134 135 imm32 r0, 0x03457290; 136 imm32 r1, 0x12345278; 137 imm32 r2, 0x23456289; 138 imm32 r3, 0x3456729a; 139 imm32 r4, 0x856782ab; 140 imm32 r5, 0x967892bc; 141 imm32 r6, 0xa789a2cd; 142 imm32 r7, 0xb89ab2de; 143 R0 = ( R0 + R5 ) << 1; 144 R1 = ( R1 + R5 ) << 1; 145 R2 = ( R2 + R5 ) << 1; 146 R3 = ( R3 + R5 ) << 1; 147 R4 = ( R4 + R5 ) << 1; 148 R6 = ( R6 + R5 ) << 1; 149 R7 = ( R7 + R5 ) << 1; 150 R5 = ( R5 + R5 ) << 1; 151 CHECKREG r0, 0x337C0A98; 152 CHECKREG r1, 0x5159CA68; 153 CHECKREG r2, 0x737BEA8A; 154 CHECKREG r3, 0x959E0AAC; 155 CHECKREG r4, 0x37C02ACE; 156 CHECKREG r5, 0x59E24AF0; 157 CHECKREG r6, 0x7C046B12; 158 CHECKREG r7, 0x9E268B34; 159 160 imm32 r0, 0x03457930; 161 imm32 r1, 0x12345638; 162 imm32 r2, 0x23456739; 163 imm32 r3, 0x3456783a; 164 imm32 r4, 0x8567893b; 165 imm32 r5, 0x96789a3c; 166 imm32 r6, 0xa789ab3d; 167 imm32 r7, 0xb89abc3e; 168 R0 = ( R0 + R6 ) << 1; 169 R1 = ( R1 + R6 ) << 1; 170 R2 = ( R2 + R6 ) << 1; 171 R3 = ( R3 + R6 ) << 1; 172 R4 = ( R4 + R6 ) << 1; 173 R5 = ( R5 + R6 ) << 1; 174 R7 = ( R7 + R6 ) << 1; 175 R6 = ( R6 + R6 ) << 1; 176 CHECKREG r0, 0x559E48DA; 177 CHECKREG r1, 0x737C02EA; 178 CHECKREG r2, 0x959E24EC; 179 CHECKREG r3, 0xB7C046EE; 180 CHECKREG r4, 0x59E268F0; 181 CHECKREG r5, 0x7C048AF2; 182 CHECKREG r6, 0x9E26ACF4; 183 CHECKREG r7, 0xC048CEF6; 184 185 imm32 r0, 0x04457990; 186 imm32 r1, 0x14345678; 187 imm32 r2, 0x24456789; 188 imm32 r3, 0x3456789a; 189 imm32 r4, 0x846789ab; 190 imm32 r5, 0x94789abc; 191 imm32 r6, 0xa489abcd; 192 imm32 r7, 0xb49abcde; 193 R0 = ( R0 + R7 ) << 1; 194 R1 = ( R1 + R7 ) << 1; 195 R2 = ( R2 + R7 ) << 1; 196 R3 = ( R3 + R7 ) << 1; 197 R4 = ( R4 + R7 ) << 1; 198 R5 = ( R5 + R7 ) << 1; 199 R6 = ( R6 + R7 ) << 1; 200 R7 = ( R7 + R7 ) << 1; 201 CHECKREG r0, 0x71C06CDC; 202 CHECKREG r1, 0x919E26AC; 203 CHECKREG r2, 0xB1C048CE; 204 CHECKREG r3, 0xD1E26AF0; 205 CHECKREG r4, 0x72048D12; 206 CHECKREG r5, 0x9226AF34; 207 CHECKREG r6, 0xB248D156; 208 CHECKREG r7, 0xD26AF378; 209 pass 210
Indexes created Tue Aug 11 00:25:38 UTC 2026