1 //Original:/testcases/core/c_alu2op_shadd_2/c_alu2op_shadd_2.dsp 2 // Spec Reference: alu2op shadd 2 3 # mach: bfin 4 5 .include "testutils.inc" 6 start 7 8 9 10 imm32 r0, 0x03417990; 11 imm32 r1, 0x12315678; 12 imm32 r2, 0x23416789; 13 imm32 r3, 0x3451789a; 14 imm32 r4, 0x856189ab; 15 imm32 r5, 0x96719abc; 16 imm32 r6, 0xa781abcd; 17 imm32 r7, 0xb891bcde; 18 R1 = ( R1 + R0 ) << 2; 19 R2 = ( R2 + R0 ) << 2; 20 R3 = ( R3 + R0 ) << 2; 21 R4 = ( R4 + R0 ) << 2; 22 R5 = ( R5 + R0 ) << 2; 23 R6 = ( R6 + R0 ) << 2; 24 R7 = ( R7 + R0 ) << 2; 25 R0 = ( R0 + R0 ) << 2; 26 CHECKREG r0, 0x1A0BCC80; 27 CHECKREG r1, 0x55CB4020; 28 CHECKREG r2, 0x9A0B8464; 29 CHECKREG r3, 0xDE4BC8A8; 30 CHECKREG r4, 0x228C0CEC; 31 CHECKREG r5, 0x66CC5130; 32 CHECKREG r6, 0xAB0C9574; 33 CHECKREG r7, 0xEF4CD9B8; 34 35 imm32 r0, 0x03457290; 36 imm32 r1, 0x12345278; 37 imm32 r2, 0x23456289; 38 imm32 r3, 0x3456729a; 39 imm32 r4, 0x856782ab; 40 imm32 r5, 0x967892bc; 41 imm32 r6, 0xa789a2cd; 42 imm32 r7, 0xb89ab2de; 43 R0 = ( R0 + R1 ) << 2; 44 R2 = ( R2 + R1 ) << 2; 45 R3 = ( R3 + R1 ) << 2; 46 R4 = ( R4 + R1 ) << 2; 47 R5 = ( R5 + R1 ) << 2; 48 R6 = ( R6 + R1 ) << 2; 49 R7 = ( R7 + R1 ) << 2; 50 R1 = ( R1 + R1 ) << 2; 51 CHECKREG r0, 0x55E71420; 52 CHECKREG r1, 0x91A293C0; 53 CHECKREG r2, 0xD5E6D404; 54 CHECKREG r3, 0x1A2B1448; 55 CHECKREG r4, 0x5E6F548C; 56 CHECKREG r5, 0xA2B394D0; 57 CHECKREG r6, 0xE6F7D514; 58 CHECKREG r7, 0x2B3C1558; 59 60 imm32 r0, 0x03457930; 61 imm32 r1, 0x12345638; 62 imm32 r2, 0x23456739; 63 imm32 r3, 0x3456783a; 64 imm32 r4, 0x8567893b; 65 imm32 r5, 0x96789a3c; 66 imm32 r6, 0xa789ab3d; 67 imm32 r7, 0xb89abc3e; 68 R0 = ( R0 + R2 ) << 2; 69 R1 = ( R1 + R2 ) << 2; 70 R3 = ( R3 + R2 ) << 2; 71 R4 = ( R4 + R2 ) << 2; 72 R5 = ( R5 + R2 ) << 2; 73 R6 = ( R6 + R2 ) << 2; 74 R7 = ( R7 + R2 ) << 2; 75 R2 = ( R2 + R2 ) << 2; 76 CHECKREG r0, 0x9A2B81A4; 77 CHECKREG r1, 0xD5E6F5C4; 78 CHECKREG r2, 0x1A2B39C8; 79 CHECKREG r3, 0x5E6F7DCC; 80 CHECKREG r4, 0xA2B3C1D0; 81 CHECKREG r5, 0xE6F805D4; 82 CHECKREG r6, 0x2B3C49D8; 83 CHECKREG r7, 0x6F808DDC; 84 85 imm32 r0, 0x04457990; 86 imm32 r1, 0x14345678; 87 imm32 r2, 0x24456789; 88 imm32 r3, 0x3456789a; 89 imm32 r4, 0x846789ab; 90 imm32 r5, 0x94789abc; 91 imm32 r6, 0xa489abcd; 92 imm32 r7, 0xb49abcde; 93 R0 = ( R0 + R3 ) << 2; 94 R1 = ( R1 + R3 ) << 2; 95 R2 = ( R2 + R3 ) << 2; 96 R4 = ( R4 + R3 ) << 2; 97 R5 = ( R5 + R3 ) << 2; 98 R6 = ( R6 + R3 ) << 2; 99 R7 = ( R7 + R3 ) << 2; 100 R3 = ( R3 + R3 ) << 2; 101 CHECKREG r0, 0xE26FC8A8; 102 CHECKREG r1, 0x222B3C48; 103 CHECKREG r2, 0x626F808C; 104 CHECKREG r3, 0xA2B3C4D0; 105 CHECKREG r4, 0xE2F80914; 106 CHECKREG r5, 0x233C4D58; 107 CHECKREG r6, 0x6380919C; 108 CHECKREG r7, 0xA3C4D5E0; 109 110 imm32 r0, 0x03417990; 111 imm32 r1, 0x12315678; 112 imm32 r2, 0x23416789; 113 imm32 r3, 0x3451789a; 114 imm32 r4, 0x856189ab; 115 imm32 r5, 0x96719abc; 116 imm32 r6, 0xa781abcd; 117 imm32 r7, 0xb891bcde; 118 R0 = ( R0 + R4 ) << 2; 119 R1 = ( R1 + R4 ) << 2; 120 R2 = ( R2 + R4 ) << 2; 121 R3 = ( R3 + R4 ) << 2; 122 R5 = ( R5 + R4 ) << 2; 123 R6 = ( R6 + R4 ) << 2; 124 R7 = ( R7 + R4 ) << 2; 125 R4 = ( R4 + R4 ) << 2; 126 CHECKREG r0, 0x228C0CEC; 127 CHECKREG r1, 0x5E4B808C; 128 CHECKREG r2, 0xA28BC4D0; 129 CHECKREG r3, 0xE6CC0914; 130 CHECKREG r4, 0x2B0C4D58; 131 CHECKREG r5, 0x6F4C919C; 132 CHECKREG r6, 0xB38CD5E0; 133 CHECKREG r7, 0xF7CD1A24; 134 135 imm32 r0, 0x03457290; 136 imm32 r1, 0x12345278; 137 imm32 r2, 0x23456289; 138 imm32 r3, 0x3456729a; 139 imm32 r4, 0x856782ab; 140 imm32 r5, 0x967892bc; 141 imm32 r6, 0xa789a2cd; 142 imm32 r7, 0xb89ab2de; 143 R0 = ( R0 + R5 ) << 2; 144 R1 = ( R1 + R5 ) << 2; 145 R2 = ( R2 + R5 ) << 2; 146 R3 = ( R3 + R5 ) << 2; 147 R4 = ( R4 + R5 ) << 2; 148 R6 = ( R6 + R5 ) << 2; 149 R7 = ( R7 + R5 ) << 2; 150 R5 = ( R5 + R5 ) << 2; 151 CHECKREG r0, 0x66F81530; 152 CHECKREG r1, 0xA2B394D0; 153 CHECKREG r2, 0xE6F7D514; 154 CHECKREG r3, 0x2B3C1558; 155 CHECKREG r4, 0x6F80559C; 156 CHECKREG r5, 0xB3C495E0; 157 CHECKREG r6, 0xF808D624; 158 CHECKREG r7, 0x3C4D1668; 159 160 imm32 r0, 0x03457930; 161 imm32 r1, 0x12345638; 162 imm32 r2, 0x23456739; 163 imm32 r3, 0x3456783a; 164 imm32 r4, 0x8567893b; 165 imm32 r5, 0x96789a3c; 166 imm32 r6, 0xa789ab3d; 167 imm32 r7, 0xb89abc3e; 168 R0 = ( R0 + R6 ) << 2; 169 R1 = ( R1 + R6 ) << 2; 170 R2 = ( R2 + R6 ) << 2; 171 R3 = ( R3 + R6 ) << 2; 172 R4 = ( R4 + R6 ) << 2; 173 R5 = ( R5 + R6 ) << 2; 174 R7 = ( R7 + R6 ) << 2; 175 R6 = ( R6 + R6 ) << 2; 176 CHECKREG r0, 0xAB3C91B4; 177 CHECKREG r1, 0xE6F805D4; 178 CHECKREG r2, 0x2B3C49D8; 179 CHECKREG r3, 0x6F808DDC; 180 CHECKREG r4, 0xB3C4D1E0; 181 CHECKREG r5, 0xF80915E4; 182 CHECKREG r6, 0x3C4D59E8; 183 CHECKREG r7, 0x80919DEC; 184 185 imm32 r0, 0x04457990; 186 imm32 r1, 0x14345678; 187 imm32 r2, 0x24456789; 188 imm32 r3, 0x3456789a; 189 imm32 r4, 0x846789ab; 190 imm32 r5, 0x94789abc; 191 imm32 r6, 0xa489abcd; 192 imm32 r7, 0xb49abcde; 193 R0 = ( R0 + R7 ) << 2; 194 R1 = ( R1 + R7 ) << 2; 195 R2 = ( R2 + R7 ) << 2; 196 R3 = ( R3 + R7 ) << 2; 197 R4 = ( R4 + R7 ) << 2; 198 R5 = ( R5 + R7 ) << 2; 199 R6 = ( R6 + R7 ) << 2; 200 R7 = ( R7 + R7 ) << 2; 201 CHECKREG r0, 0xE380D9B8; 202 CHECKREG r1, 0x233C4D58; 203 CHECKREG r2, 0x6380919C; 204 CHECKREG r3, 0xA3C4D5E0; 205 CHECKREG r4, 0xE4091A24; 206 CHECKREG r5, 0x244D5E68; 207 CHECKREG r6, 0x6491A2AC; 208 CHECKREG r7, 0xA4D5E6F0; 209 pass 210