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      1 //Original:/testcases/core/c_dsp32mac_dr_a0_i/c_dsp32mac_dr_a0_i.dsp
      2 // Spec Reference: dsp32mac dr a0 i (signed int)
      3 # mach: bfin
      4 
      5 .include "testutils.inc"
      6 	start
      7 
      8 
      9 
     10 
     11 A1 = A0 = 0;
     12 
     13 // The result accumulated in A , and stored to a reg half
     14 imm32 r0, 0xa3545abd;
     15 imm32 r1, 0x9dbcfec7;
     16 imm32 r2, 0xc9248679;
     17 imm32 r3, 0xd0969007;
     18 imm32 r4, 0xefb94569;
     19 imm32 r5, 0xcd35900b;
     20 imm32 r6, 0xe00c890d;
     21 imm32 r7, 0xf78e909f;
     22 A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (IS);
     23 R1 = A0.w;
     24 A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (IS);
     25 R3 = A0.w;
     26 A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (IS);
     27 R5 = A0.w;
     28 A1 += R6.H * R7.H, R6.L = ( A0 -= R6.L * R7.H ) (IS);
     29 R7 = A0.w;
     30 CHECKREG r0, 0xA3548000;
     31 CHECKREG r1, 0xFF910EEB;
     32 CHECKREG r2, 0xC9247FFF;
     33 CHECKREG r3, 0x17FEBFFC;
     34 CHECKREG r4, 0xEFB97FFF;
     35 CHECKREG r5, 0x1B398649;
     36 CHECKREG r6, 0xE00C7FFF;
     37 CHECKREG r7, 0x174CF613;
     38 
     39 // The result accumulated in A , and stored to a reg half (MNOP)
     40 imm32 r0, 0x68548abd;
     41 imm32 r1, 0x7d8cfec7;
     42 imm32 r2, 0xa1285679;
     43 imm32 r3, 0xb0068007;
     44 imm32 r4, 0xcfbc4869;
     45 imm32 r5, 0xd235c08b;
     46 imm32 r6, 0xe00ca008;
     47 imm32 r7, 0x678e700f;
     48 R0.L = ( A0 -= R1.L * R0.L ) (IS);
     49 R1 = A0.w;
     50 R2.L = ( A0 += R2.L * R3.H ) (IS);
     51 R3 = A0.w;
     52 R4.L = ( A0 = R4.H * R5.L ) (IS);
     53 R5 = A0.w;
     54 R6.L = ( A0 -= R6.H * R7.H ) (IS);
     55 R7 = A0.w;
     56 CHECKREG r0, 0x68547FFF;
     57 CHECKREG r1, 0x16BD9728;
     58 CHECKREG r2, 0xA1288000;
     59 CHECKREG r3, 0xFBB9CDFE;
     60 CHECKREG r4, 0xCFBC7FFF;
     61 CHECKREG r5, 0x0BF6CB14;
     62 CHECKREG r6, 0xE00C7FFF;
     63 CHECKREG r7, 0x18E3B06C;
     64 
     65 // The result accumulated in A , and stored to a reg half (MNOP)
     66 imm32 r0, 0x7b54babd;
     67 imm32 r1, 0xb7bcdec7;
     68 imm32 r2, 0x7b7be679;
     69 imm32 r3, 0x80b77007;
     70 imm32 r4, 0x9fbb7569;
     71 imm32 r5, 0xa235b70b;
     72 imm32 r6, 0xb00c3b7d;
     73 imm32 r7, 0xc78ea0b7;
     74 R0.L = ( A0 = R1.L * R0.L ) (IS);
     75 R1 = A0.w;
     76 R2.L = ( A0 -= R2.H * R3.L ) (IS);
     77 R3 = A0.w;
     78 R4.L = ( A0 = R4.H * R5.H ) (IS);
     79 R5 = A0.w;
     80 R6.L = ( A0 += R6.L * R7.H ) (IS);
     81 R7 = A0.w;
     82 CHECKREG r0, 0x7B547FFF;
     83 CHECKREG r1, 0x08FD0EEB;
     84 CHECKREG r2, 0x7B7B8000;
     85 CHECKREG r3, 0xD2F3DE8E;
     86 CHECKREG r4, 0x9FBB7FFF;
     87 CHECKREG r5, 0x234567B7;
     88 CHECKREG r6, 0xB00C7FFF;
     89 CHECKREG r7, 0x1627920D;
     90 
     91 // The result accumulated in A , and stored to a reg half
     92 imm32 r0, 0xe3545abd;
     93 imm32 r1, 0x5ebcfec7;
     94 imm32 r2, 0x71e45679;
     95 imm32 r3, 0x900e0007;
     96 imm32 r4, 0xafbce569;
     97 imm32 r5, 0xd2359e0b;
     98 imm32 r6, 0xc00ca0ed;
     99 imm32 r7, 0x678ed00e;
    100 A1 -= R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (IS);
    101 R3 = A0.w;
    102 A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L ) (IS);
    103 R7 = A0.w;
    104 A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (IS);
    105 R5 = A0.w;
    106 A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (IS);
    107 R1 = A0.w;
    108 CHECKREG r0, 0xE3547FFF;
    109 CHECKREG r1, 0x2E5AD9ED;
    110 CHECKREG r2, 0x71E47FFF;
    111 CHECKREG r3, 0x15B8A0F8;
    112 CHECKREG r4, 0xAFBC7FFF;
    113 CHECKREG r5, 0x0E5B99EC;
    114 CHECKREG r6, 0xC00C7FFF;
    115 CHECKREG r7, 0x3FFFCC18;
    116 
    117 
    118 
    119 pass
    120