1 //Original:/testcases/core/c_dsp32mac_dr_a1_ih/c_dsp32mac_dr_a1_ih.dsp 2 // Spec Reference: dsp32mac dr_a1 ih (int multiplication with word extraction) 3 # mach: bfin 4 5 .include "testutils.inc" 6 start 7 8 9 10 11 A1 = A0 = 0; 12 13 // The result accumulated in A1 , and stored to a reg half 14 imm32 r0, 0x93545abd; 15 imm32 r1, 0x1dbcfec7; 16 imm32 r2, 0x52248679; 17 imm32 r3, 0xd6069007; 18 imm32 r4, 0xef7c4569; 19 imm32 r5, 0xcd38500b; 20 imm32 r6, 0xe00c900d; 21 imm32 r7, 0xf78e990f; 22 R0.H = ( A1 = R1.L * R0.L ), A0 -= R1.L * R0.L (IH); 23 R1 = A1.w; 24 R2.H = ( A1 += R2.L * R3.H ), A0 -= R2.H * R3.L (IH); 25 R3 = A1.w; 26 R4.H = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (IH); 27 R5 = A1.w; 28 R6.H = ( A1 = R6.H * R7.H ), A0 = R6.L * R7.H (IH); 29 R7 = A1.w; 30 CHECKREG r0, 0xFF915ABD; 31 CHECKREG r1, 0xFF910EEB; 32 CHECKREG r2, 0x137E8679; 33 CHECKREG r3, 0x137E5BC1; 34 CHECKREG r4, 0x18A84569; 35 CHECKREG r5, 0x18A8516D; 36 CHECKREG r6, 0x010E900D; 37 CHECKREG r7, 0x010DDAA8; 38 39 // The result accumulated in A1, and stored to a reg half (MNOP) 40 imm32 r0, 0x83548abd; 41 imm32 r1, 0x76bcfec7; 42 imm32 r2, 0xa1745679; 43 imm32 r3, 0xb0269007; 44 imm32 r4, 0xcfb34569; 45 imm32 r5, 0xd235600b; 46 imm32 r6, 0xe00ca70d; 47 imm32 r7, 0x678e708f; 48 R0.H = ( A1 -= R1.L * R0.L ) (IH); 49 R1 = A1.w; 50 R2.H = ( A1 += R2.L * R3.H ) (IH); 51 R3 = A1.w; 52 R4.H = ( A1 = R4.H * R5.L ) (IH); 53 R5 = A1.w; 54 R6.H = ( A1 -= R6.H * R7.H ) (IH); 55 R7 = A1.w; 56 CHECKREG r0, 0x007E8ABD; 57 CHECKREG r1, 0x007E7BBD; 58 CHECKREG r2, 0xE5865679; 59 CHECKREG r3, 0xE58581B3; 60 CHECKREG r4, 0xEDE14569; 61 CHECKREG r5, 0xEDE10CB1; 62 CHECKREG r6, 0xFACEA70D; 63 CHECKREG r7, 0xFACDF209; 64 65 // The result accumulated in A1 , and stored to a reg half (MNOP) 66 imm32 r0, 0x5354babd; 67 imm32 r1, 0x9dbcdec7; 68 imm32 r2, 0x7724e679; 69 imm32 r3, 0x80567007; 70 imm32 r4, 0x9fb34569; 71 imm32 r5, 0xa235200b; 72 imm32 r6, 0xb00c100d; 73 imm32 r7, 0x9876a10f; 74 R0.H = A1 , A0 = R1.L * R0.L (IH); 75 R1 = A1.w; 76 R2.H = A1 , A0 += R2.H * R3.L (IH); 77 R3 = A1.w; 78 R4.H = A1 , A0 -= R4.H * R5.H (IH); 79 R5 = A1.w; 80 R6.H = A1 , A0 += R6.L * R7.H (IH); 81 R7 = A1.w; 82 CHECKREG r0, 0xFACEBABD; 83 CHECKREG r1, 0xFACDF209; 84 CHECKREG r2, 0xFACEE679; 85 CHECKREG r3, 0xFACDF209; 86 CHECKREG r4, 0xFACE4569; 87 CHECKREG r5, 0xFACDF209; 88 CHECKREG r6, 0xFACE100D; 89 CHECKREG r7, 0xFACDF209; 90 91 // The result accumulated in A1 , and stored to a reg half 92 imm32 r0, 0x33545abd; 93 imm32 r1, 0x9dbcfec7; 94 imm32 r2, 0x81245679; 95 imm32 r3, 0x97060007; 96 imm32 r4, 0xaf6c4569; 97 imm32 r5, 0xd235900b; 98 imm32 r6, 0xc00c400d; 99 imm32 r7, 0x678ed30f; 100 R0.H = ( A1 = R1.L * R0.L ) (M), A0 -= R1.L * R0.L (IH); 101 R1 = A1.w; 102 R2.H = ( A1 += R2.L * R3.H ) (M), A0 += R2.H * R3.L (IH); 103 R3 = A1.w; 104 R4.H = ( A1 = R4.H * R5.L ) (M), A0 += R4.H * R5.H (IH); 105 R5 = A1.w; 106 R6.H = ( A1 = R6.H * R7.H ) (M), A0 -= R6.L * R7.H (IH); 107 R7 = A1.w; 108 CHECKREG r0, 0xFF915ABD; 109 CHECKREG r1, 0xFF910EEB; 110 CHECKREG r2, 0x32945679; 111 CHECKREG r3, 0x329474C1; 112 CHECKREG r4, 0xD2A94569; 113 CHECKREG r5, 0xD2A949A4; 114 CHECKREG r6, 0xE621400D; 115 CHECKREG r7, 0xE6215AA8; 116 117 // The result accumulated in A1 MM=0, and stored to a reg half (MNOP) 118 imm32 r0, 0x92005ABD; 119 imm32 r1, 0x09300000; 120 imm32 r2, 0x56749679; 121 imm32 r3, 0x30A95000; 122 imm32 r4, 0xa0009669; 123 imm32 r5, 0x01000970; 124 imm32 r6, 0xdf45609D; 125 imm32 r7, 0x12345679; 126 R0.H = ( A1 -= R1.L * R0.L ) (M,IH); 127 R1 = A1.w; 128 R2.H = ( A1 += R2.L * R3.H ) (M,IH); 129 R3 = A1.w; 130 R4.H = ( A1 = R4.H * R5.L ) (M,IH); 131 R5 = A1.w; 132 R6.H = ( A1 += R6.H * R7.H ) (M,IH); 133 R7 = A1.w; 134 CHECKREG r0, 0xE6215ABD; 135 CHECKREG r1, 0xE6215AA8; 136 CHECKREG r2, 0xD2129679; 137 CHECKREG r3, 0xD2126089; 138 CHECKREG r4, 0xFC769669; 139 CHECKREG r5, 0xFC760000; 140 CHECKREG r6, 0xFA22609D; 141 CHECKREG r7, 0xFA223404; 142 143 144 145 pass 146
Indexes created Wed Aug 12 00:25:48 UTC 2026