1 //Original:/testcases/core/c_dsp32mult_dr_s/c_dsp32mult_dr_s.dsp 2 // Spec Reference: dsp32mult single dr s 3 # mach: bfin 4 5 .include "testutils.inc" 6 start 7 8 imm32 r0, 0x8b235625; 9 imm32 r1, 0x98ba5127; 10 imm32 r2, 0xa3846725; 11 imm32 r3, 0x00080027; 12 imm32 r4, 0xb0ab8d29; 13 imm32 r5, 0x10ace82b; 14 imm32 r6, 0xc00c008d; 15 imm32 r7, 0xd2467028; 16 R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (S2RND); 17 R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (S2RND); 18 R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (S2RND); 19 R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (S2RND); 20 R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (S2RND); 21 R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (S2RND); 22 R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (S2RND); 23 R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (S2RND); 24 CHECKREG r0, 0x73F473F4; 25 CHECKREG r1, 0x7FFF8000; 26 CHECKREG r2, 0x80007FFF; 27 CHECKREG r3, 0x7FFF7FFF; 28 CHECKREG r4, 0x73F473F4; 29 CHECKREG r5, 0x6D3B8000; 30 CHECKREG r6, 0x6D3B8000; 31 CHECKREG r7, 0x66E77FFF; 32 33 imm32 r0, 0x9923a635; 34 imm32 r1, 0x6f995137; 35 imm32 r2, 0x1324b735; 36 imm32 r3, 0x99060037; 37 imm32 r4, 0x809bcd39; 38 imm32 r5, 0xb0a99f3b; 39 imm32 r6, 0xa00c093d; 40 imm32 r7, 0x12467093; 41 R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (S2RND); 42 R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (S2RND); 43 R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (S2RND); 44 R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (S2RND); 45 R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (S2RND); 46 R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (S2RND); 47 R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (S2RND); 48 R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (S2RND); 49 CHECKREG r0, 0xF416F416; 50 CHECKREG r1, 0x132C132C; 51 CHECKREG r2, 0xEA3BEA3B; 52 CHECKREG r3, 0x23072307; 53 CHECKREG r4, 0xEA3BEA3B; 54 CHECKREG r5, 0x7520E134; 55 CHECKREG r6, 0xFFC10010; 56 CHECKREG r7, 0xFFA8FFA8; 57 58 imm32 r0, 0x19235655; 59 imm32 r1, 0xc9ba5157; 60 imm32 r2, 0x63246755; 61 imm32 r3, 0x0a060055; 62 imm32 r4, 0x90abc509; 63 imm32 r5, 0x10acef5b; 64 imm32 r6, 0xb00a005d; 65 imm32 r7, 0x1246a05f; 66 R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (S2RND); 67 R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (S2RND); 68 R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (S2RND); 69 R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (S2RND); 70 R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (S2RND); 71 R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (S2RND); 72 R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (S2RND); 73 R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (S2RND); 74 CHECKREG r0, 0x66933653; 75 CHECKREG r1, 0x1CF4F0A4; 76 CHECKREG r2, 0xF0A4F0A4; 77 CHECKREG r3, 0x04540458; 78 CHECKREG r4, 0x66933653; 79 CHECKREG r5, 0xE553F1DF; 80 CHECKREG r6, 0xF402E95B; 81 CHECKREG r7, 0x05E40B1E; 82 83 imm32 r0, 0xbb235666; 84 imm32 r1, 0xefba5166; 85 imm32 r2, 0x13248766; 86 imm32 r3, 0xe0060066; 87 imm32 r4, 0x9eab9d69; 88 imm32 r5, 0x10ecef6b; 89 imm32 r6, 0x800ee06d; 90 imm32 r7, 0x12467e6f; 91 // test the unsigned U=1 92 R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (S2RND); 93 R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (S2RND); 94 R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (S2RND); 95 R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (S2RND); 96 R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (S2RND); 97 R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (S2RND); 98 R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (S2RND); 99 R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (S2RND); 100 CHECKREG r0, 0x7FFF0F94; 101 CHECKREG r1, 0xDB78F6FC; 102 CHECKREG r2, 0xDB78F6FC; 103 CHECKREG r3, 0x05380538; 104 CHECKREG r4, 0x491708E5; 105 CHECKREG r5, 0x14DF14DF; 106 CHECKREG r6, 0x7FFF0F94; 107 CHECKREG r7, 0x248C0473; 108 109 // mix order 110 imm32 r0, 0xac23a675; 111 imm32 r1, 0xcfba5127; 112 imm32 r2, 0x13c46705; 113 imm32 r3, 0x00060007; 114 imm32 r4, 0x90accd09; 115 imm32 r5, 0x10acdfdb; 116 imm32 r6, 0x000cc00d; 117 imm32 r7, 0x1246fc0f; 118 R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (S2RND); 119 R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (S2RND); 120 R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (S2RND); 121 R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (S2RND); 122 R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (S2RND); 123 R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (S2RND); 124 R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (S2RND); 125 R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (S2RND); 126 CHECKREG r0, 0x0584E80E; 127 CHECKREG r1, 0xAEE9000F; 128 CHECKREG r2, 0xF613F613; 129 CHECKREG r3, 0xFFFAFFFA; 130 CHECKREG r4, 0x00050005; 131 CHECKREG r5, 0xFD6AFD6A; 132 CHECKREG r6, 0xFFF1FFF1; 133 CHECKREG r7, 0xF92A0193; 134 135 imm32 r0, 0xab235a75; 136 imm32 r1, 0xcfba5127; 137 imm32 r2, 0xdd246905; 138 imm32 r3, 0x00d6d007; 139 imm32 r4, 0x90abcd09; 140 imm32 r5, 0x10aceddb; 141 imm32 r6, 0x000c0d0d; 142 imm32 r7, 0x1246700f; 143 R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (S2RND); 144 R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (S2RND); 145 R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (S2RND); 146 R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (S2RND); 147 R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (S2RND); 148 R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (S2RND); 149 R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (S2RND); 150 R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (S2RND); 151 CHECKREG r0, 0xE7C519D4; 152 CHECKREG r1, 0xFFF7108C; 153 CHECKREG r2, 0xF6EB1B5B; 154 CHECKREG r3, 0xFE8C5374; 155 CHECKREG r4, 0x02870128; 156 CHECKREG r5, 0xFDA20293; 157 CHECKREG r6, 0x0000FFFE; 158 CHECKREG r7, 0x0760F915; 159 160 imm32 r0, 0xfb235675; 161 imm32 r1, 0xcfba5127; 162 imm32 r2, 0x13f46705; 163 imm32 r3, 0x000f0007; 164 imm32 r4, 0x90abfd09; 165 imm32 r5, 0x10acefdb; 166 imm32 r6, 0x000c00fd; 167 imm32 r7, 0x1246700f; 168 R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (S2RND); 169 R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (S2RND); 170 R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (S2RND); 171 R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (S2RND); 172 R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (S2RND); 173 R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (S2RND); 174 R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (S2RND); 175 R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (S2RND); 176 CHECKREG r0, 0x0016FFE6; 177 CHECKREG r1, 0x94D30A65; 178 CHECKREG r2, 0x01560010; 179 CHECKREG r3, 0xF238AB7A; 180 CHECKREG r4, 0xFFFFFDAD; 181 CHECKREG r5, 0x037AE9FB; 182 CHECKREG r6, 0x00000000; 183 CHECKREG r7, 0xD97200FE; 184 185 imm32 r0, 0xab2d5675; 186 imm32 r1, 0xcfbad127; 187 imm32 r2, 0x13246d05; 188 imm32 r3, 0x000600d7; 189 imm32 r4, 0x908bcd09; 190 imm32 r5, 0x10a9efdb; 191 imm32 r6, 0x000c500d; 192 imm32 r7, 0x1246760f; 193 R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (S2RND); 194 R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (S2RND); 195 R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (S2RND); 196 R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (S2RND); 197 R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (S2RND); 198 R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (S2RND); 199 R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (S2RND); 200 R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (S2RND); 201 CHECKREG r0, 0xF718CD46; 202 CHECKREG r1, 0xF2CC0CCC; 203 CHECKREG r2, 0x00020000; 204 CHECKREG r3, 0xFF56FFE2; 205 CHECKREG r4, 0xE480FB2C; 206 CHECKREG r5, 0x00000004; 207 CHECKREG r6, 0x00000008; 208 CHECKREG r7, 0xFA8000FF; 209 210 211 212 pass 213
Indexes created Tue Aug 11 00:25:38 UTC 2026