1 //Original:/testcases/core/c_dsp32shift_ahalf_rn_s/c_dsp32shift_ahalf_rn_s.dsp 2 // Spec Reference: dsp32shift ashift s 3 # mach: bfin 4 5 .include "testutils.inc" 6 start 7 8 9 10 // Ashift : positive data, count (+)=left (half reg) 11 // d_lo = ashft (d_lo BY d_lo) 12 // RLx by RLx 13 imm32 r0, 0x00000000; 14 R0.L = -1; 15 imm32 r1, 0x00008001; 16 imm32 r2, 0x00008002; 17 imm32 r3, 0x00008003; 18 imm32 r4, 0x00008004; 19 imm32 r5, 0x00008005; 20 imm32 r6, 0x00008006; 21 imm32 r7, 0x00008007; 22 //rl0 = ashift (rl0 by rl0); 23 R1.L = ASHIFT R1.L BY R0.L (S); 24 R2.L = ASHIFT R2.L BY R0.L (S); 25 R3.L = ASHIFT R3.L BY R0.L (S); 26 R4.L = ASHIFT R4.L BY R0.L (S); 27 R5.L = ASHIFT R5.L BY R0.L (S); 28 R6.L = ASHIFT R6.L BY R0.L (S); 29 R7.L = ASHIFT R7.L BY R0.L (S); 30 //CHECKREG r0, 0x00000000; 31 CHECKREG r1, 0x0000c000; 32 CHECKREG r2, 0x0000c001; 33 CHECKREG r3, 0x0000c001; 34 CHECKREG r4, 0x0000c002; 35 CHECKREG r5, 0x0000c002; 36 CHECKREG r6, 0x0000c003; 37 CHECKREG r7, 0x0000c003; 38 39 imm32 r0, 0x00008001; 40 R1.L = -1; 41 imm32 r2, 0x00008002; 42 imm32 r3, 0x00008003; 43 imm32 r4, 0x00008004; 44 imm32 r5, 0x00008005; 45 imm32 r6, 0x00008006; 46 imm32 r7, 0x00008007; 47 R0.L = ASHIFT R0.L BY R1.L (S); 48 //rl1 = ashift (rl1 by rl1); 49 R2.L = ASHIFT R2.L BY R1.L (S); 50 R3.L = ASHIFT R3.L BY R1.L (S); 51 R4.L = ASHIFT R4.L BY R1.L (S); 52 R5.L = ASHIFT R5.L BY R1.L (S); 53 R6.L = ASHIFT R6.L BY R1.L (S); 54 R7.L = ASHIFT R7.L BY R1.L (S); 55 CHECKREG r0, 0x0000c000; 56 //CHECKREG r1, 0x00000001; 57 CHECKREG r2, 0x0000c001; 58 CHECKREG r3, 0x0000c001; 59 CHECKREG r4, 0x0000c002; 60 CHECKREG r5, 0x0000c002; 61 CHECKREG r6, 0x0000c003; 62 CHECKREG r7, 0x0000c003; 63 64 65 imm32 r0, 0x00008001; 66 imm32 r1, 0x00008001; 67 R2.L = -15; 68 imm32 r3, 0x00008003; 69 imm32 r4, 0x00008004; 70 imm32 r5, 0x00008005; 71 imm32 r6, 0x00008006; 72 imm32 r7, 0x00008007; 73 R0.L = ASHIFT R0.L BY R2.L (S); 74 R1.L = ASHIFT R1.L BY R2.L (S); 75 //rl2 = ashift (rl2 by rl2); 76 R3.L = ASHIFT R3.L BY R2.L (S); 77 R4.L = ASHIFT R4.L BY R2.L (S); 78 R5.L = ASHIFT R5.L BY R2.L (S); 79 R6.L = ASHIFT R6.L BY R2.L (S); 80 R7.L = ASHIFT R7.L BY R2.L (S); 81 CHECKREG r0, 0x0000ffff; 82 CHECKREG r1, 0x0000ffff; 83 //CHECKREG r2, 0x0000000f; 84 CHECKREG r3, 0x0000ffff; 85 CHECKREG r4, 0x0000ffff; 86 CHECKREG r5, 0x0000ffff; 87 CHECKREG r6, 0x0000ffff; 88 CHECKREG r7, 0x0000ffff; 89 90 imm32 r0, 0x00008001; 91 imm32 r1, 0x00008001; 92 imm32 r2, 0x00008002; 93 R3.L = -16; 94 imm32 r4, 0x00008004; 95 imm32 r5, 0x00008005; 96 imm32 r6, 0x00008006; 97 imm32 r7, 0x00008007; 98 R0.L = ASHIFT R0.L BY R3.L (S); 99 R1.L = ASHIFT R1.L BY R3.L (S); 100 R2.L = ASHIFT R2.L BY R3.L (S); 101 //rl3 = ashift (rl3 by rl3); 102 R4.L = ASHIFT R4.L BY R3.L (S); 103 R5.L = ASHIFT R5.L BY R3.L (S); 104 R6.L = ASHIFT R6.L BY R3.L (S); 105 R7.L = ASHIFT R7.L BY R3.L (S); 106 CHECKREG r0, 0x0000ffff; 107 CHECKREG r1, 0x0000ffff; 108 CHECKREG r2, 0x0000ffff; 109 //CHECKREG r3, 0x00000010; 110 CHECKREG r4, 0x0000ffff; 111 CHECKREG r5, 0x0000ffff; 112 CHECKREG r6, 0x0000ffff; 113 CHECKREG r7, 0x0000ffff; 114 115 // d_lo = ashft (d_hi BY d_lo) 116 // RHx by RLx 117 imm32 r0, 0x00000000; 118 imm32 r1, 0x80010000; 119 imm32 r2, 0x80020000; 120 imm32 r3, 0x80030000; 121 imm32 r4, 0x80040000; 122 imm32 r5, 0x80050000; 123 imm32 r6, 0x80060000; 124 imm32 r7, 0x80070000; 125 R0.L = ASHIFT R0.H BY R0.L (S); 126 R1.L = ASHIFT R1.H BY R0.L (S); 127 R2.L = ASHIFT R2.H BY R0.L (S); 128 R3.L = ASHIFT R3.H BY R0.L (S); 129 R4.L = ASHIFT R4.H BY R0.L (S); 130 R5.L = ASHIFT R5.H BY R0.L (S); 131 R6.L = ASHIFT R6.H BY R0.L (S); 132 R7.L = ASHIFT R7.H BY R0.L (S); 133 CHECKREG r0, 0x00000000; 134 CHECKREG r1, 0x80018001; 135 CHECKREG r2, 0x80028002; 136 CHECKREG r3, 0x80038003; 137 CHECKREG r4, 0x80048004; 138 CHECKREG r5, 0x80058005; 139 CHECKREG r6, 0x80068006; 140 CHECKREG r7, 0x80078007; 141 142 imm32 r0, 0x80010000; 143 R1.L = -1; 144 imm32 r2, 0x80020000; 145 imm32 r3, 0x80030000; 146 imm32 r4, 0x80040000; 147 imm32 r5, 0x80050000; 148 imm32 r6, 0x80060000; 149 imm32 r7, 0x80070000; 150 R0.L = ASHIFT R0.H BY R1.L (S); 151 //rl1 = ashift (rh1 by rl1); 152 R2.L = ASHIFT R2.H BY R1.L (S); 153 R3.L = ASHIFT R3.H BY R1.L (S); 154 R4.L = ASHIFT R4.H BY R1.L (S); 155 R5.L = ASHIFT R5.H BY R1.L (S); 156 R6.L = ASHIFT R6.H BY R1.L (S); 157 R7.L = ASHIFT R7.H BY R1.L (S); 158 CHECKREG r0, 0x8001c000; 159 //CHECKREG r1, 0x00010001; 160 CHECKREG r2, 0x8002c001; 161 CHECKREG r3, 0x8003c001; 162 CHECKREG r4, 0x8004c002; 163 CHECKREG r5, 0x8005c002; 164 CHECKREG r6, 0x8006c003; 165 CHECKREG r7, 0x8007c003; 166 167 168 imm32 r0, 0xa0010000; 169 imm32 r1, 0xa0010000; 170 R2.L = -15; 171 imm32 r3, 0xa0030000; 172 imm32 r4, 0xa0040000; 173 imm32 r5, 0xa0050000; 174 imm32 r6, 0xa0060000; 175 imm32 r7, 0xa0070000; 176 R0.L = ASHIFT R0.H BY R2.L (S); 177 R1.L = ASHIFT R1.H BY R2.L (S); 178 //rl2 = ashift (rh2 by rl2); 179 R3.L = ASHIFT R3.H BY R2.L (S); 180 R4.L = ASHIFT R4.H BY R2.L (S); 181 R5.L = ASHIFT R5.H BY R2.L (S); 182 R6.L = ASHIFT R6.H BY R2.L (S); 183 R7.L = ASHIFT R7.H BY R2.L (S); 184 CHECKREG r0, 0xa001ffff; 185 CHECKREG r1, 0xa001ffff; 186 //CHECKREG r2, 0x2002000f; 187 CHECKREG r3, 0xa003ffff; 188 CHECKREG r4, 0xa004ffff; 189 CHECKREG r5, 0xa005ffff; 190 CHECKREG r6, 0xa006ffff; 191 CHECKREG r7, 0xa007ffff; 192 193 imm32 r0, 0xb0010001; 194 imm32 r1, 0xb0010001; 195 imm32 r2, 0xb0020002; 196 R3.L = -16; 197 imm32 r4, 0xb0040004; 198 imm32 r5, 0xb0050005; 199 imm32 r6, 0xb0060006; 200 imm32 r7, 0xb0070007; 201 R0.L = ASHIFT R0.H BY R3.L (S); 202 R1.L = ASHIFT R1.H BY R3.L (S); 203 R2.L = ASHIFT R2.H BY R3.L (S); 204 //rl3 = ashift (rh3 by rl3); 205 R4.L = ASHIFT R4.H BY R3.L (S); 206 R5.L = ASHIFT R5.H BY R3.L (S); 207 R6.L = ASHIFT R6.H BY R3.L (S); 208 R7.L = ASHIFT R7.H BY R3.L (S); 209 CHECKREG r0, 0xb001ffff; 210 CHECKREG r1, 0xb001ffff; 211 CHECKREG r2, 0xb002ffff; 212 //CHECKREG r3, 0x30030010; 213 CHECKREG r4, 0xb004ffff; 214 CHECKREG r5, 0xb005ffff; 215 CHECKREG r6, 0xb006ffff; 216 CHECKREG r7, 0xb007ffff; 217 218 // d_hi = ashft (d_lo BY d_lo) 219 // RLx by RLx 220 imm32 r0, 0x00000001; 221 imm32 r1, 0x00000001; 222 imm32 r2, 0x00000002; 223 imm32 r3, 0x00000003; 224 imm32 r4, 0x00000000; 225 imm32 r5, 0x00000005; 226 imm32 r6, 0x00000006; 227 imm32 r7, 0x00000007; 228 R0.H = ASHIFT R0.L BY R4.L (S); 229 R1.H = ASHIFT R1.L BY R4.L (S); 230 R2.H = ASHIFT R2.L BY R4.L (S); 231 R3.H = ASHIFT R3.L BY R4.L (S); 232 //rh4 = ashift (rl4 by rl4); 233 R5.H = ASHIFT R5.L BY R4.L (S); 234 R6.H = ASHIFT R6.L BY R4.L (S); 235 R7.H = ASHIFT R7.L BY R4.L (S); 236 CHECKREG r0, 0x00010001; 237 CHECKREG r1, 0x00010001; 238 CHECKREG r2, 0x00020002; 239 CHECKREG r3, 0x00030003; 240 //CHECKREG r4, 0x00040004; 241 CHECKREG r5, 0x00050005; 242 CHECKREG r6, 0x00060006; 243 CHECKREG r7, 0x00070007; 244 245 imm32 r0, 0x00008001; 246 imm32 r1, 0x00008001; 247 imm32 r2, 0x00008002; 248 imm32 r3, 0x00008003; 249 imm32 r4, 0x00008004; 250 R5.L = -1; 251 imm32 r6, 0x00008006; 252 imm32 r7, 0x00008007; 253 R0.H = ASHIFT R0.L BY R5.L (S); 254 R1.H = ASHIFT R1.L BY R5.L (S); 255 R2.H = ASHIFT R2.L BY R5.L (S); 256 R3.H = ASHIFT R3.L BY R5.L (S); 257 R4.H = ASHIFT R4.L BY R5.L (S); 258 //rh5 = ashift (rl5 by rl5); 259 R6.H = ASHIFT R6.L BY R5.L (S); 260 R7.H = ASHIFT R7.L BY R5.L (S); 261 CHECKREG r0, 0xc0008001; 262 CHECKREG r1, 0xc0008001; 263 CHECKREG r2, 0xc0018002; 264 CHECKREG r3, 0xc0018003; 265 CHECKREG r4, 0xc0028004; 266 //CHECKREG r5, 0x00020005; 267 CHECKREG r6, 0xc0038006; 268 CHECKREG r7, 0xc0038007; 269 270 271 imm32 r0, 0x00009001; 272 imm32 r1, 0x00009001; 273 imm32 r2, 0x00009002; 274 imm32 r3, 0x00009003; 275 imm32 r4, 0x00009004; 276 imm32 r5, 0x00009005; 277 R6.L = -15; 278 imm32 r7, 0x00009007; 279 R0.H = ASHIFT R0.L BY R6.L (S); 280 R1.H = ASHIFT R1.L BY R6.L (S); 281 R2.H = ASHIFT R2.L BY R6.L (S); 282 R3.H = ASHIFT R3.L BY R6.L (S); 283 R4.H = ASHIFT R4.L BY R6.L (S); 284 R5.H = ASHIFT R5.L BY R6.L (S); 285 //rh6 = ashift (rl6 by rl6); 286 R7.H = ASHIFT R7.L BY R6.L; 287 CHECKREG r0, 0xffff9001; 288 CHECKREG r1, 0xffff9001; 289 CHECKREG r2, 0xffff9002; 290 CHECKREG r3, 0xffff9003; 291 CHECKREG r4, 0xffff9004; 292 CHECKREG r5, 0xffff9005; 293 //CHECKREG r6, 0x00006006; 294 CHECKREG r7, 0xffff9007; 295 296 imm32 r0, 0x0000a001; 297 imm32 r1, 0x0000a001; 298 imm32 r2, 0x0000a002; 299 imm32 r3, 0x0000a003; 300 imm32 r4, 0x0000a004; 301 imm32 r5, 0x0000a005; 302 imm32 r6, 0x0000a006; 303 R7.L = -16; 304 R0.H = ASHIFT R0.L BY R7.L (S); 305 R1.H = ASHIFT R1.L BY R7.L (S); 306 R2.H = ASHIFT R2.L BY R7.L (S); 307 R3.H = ASHIFT R3.L BY R7.L (S); 308 R4.H = ASHIFT R4.L BY R7.L (S); 309 R5.H = ASHIFT R5.L BY R7.L (S); 310 R6.H = ASHIFT R6.L BY R7.L (S); 311 R7.H = ASHIFT R7.L BY R7.L (S); 312 CHECKREG r0, 0xffffa001; 313 CHECKREG r1, 0xffffa001; 314 CHECKREG r2, 0xffffa002; 315 CHECKREG r3, 0xffffa003; 316 CHECKREG r4, 0xffffa004; 317 CHECKREG r5, 0xffffa005; 318 CHECKREG r6, 0xffffa006; 319 //CHECKREG r7, 0x00007007; 320 321 // d_lo = ashft (d_hi BY d_lo) 322 // RHx by RLx 323 imm32 r0, 0x80010000; 324 imm32 r1, 0x80010000; 325 imm32 r2, 0x80020000; 326 imm32 r3, 0x80030000; 327 R4.L = -1; 328 imm32 r5, 0x80050000; 329 imm32 r6, 0x80060000; 330 imm32 r7, 0x80070000; 331 R0.H = ASHIFT R0.H BY R4.L (S); 332 R1.H = ASHIFT R1.H BY R4.L (S); 333 R2.H = ASHIFT R2.H BY R4.L (S); 334 R3.H = ASHIFT R3.H BY R4.L (S); 335 //rh4 = ashift (rh4 by rl4); 336 R5.H = ASHIFT R5.H BY R4.L (S); 337 R6.H = ASHIFT R6.H BY R4.L (S); 338 R7.H = ASHIFT R7.H BY R4.L (S); 339 CHECKREG r0, 0xc0000000; 340 CHECKREG r1, 0xc0000000; 341 CHECKREG r2, 0xc0010000; 342 CHECKREG r3, 0xc0010000; 343 //CHECKREG r4, 0x00020000; 344 CHECKREG r5, 0xc0020000; 345 CHECKREG r6, 0xc0030000; 346 CHECKREG r7, 0xc0030000; 347 348 imm32 r0, 0x80010000; 349 imm32 r1, 0x80010000; 350 imm32 r2, 0x80020000; 351 imm32 r3, 0x80030000; 352 imm32 r4, 0x80040000; 353 R5.L = -1; 354 imm32 r6, 0x80060000; 355 imm32 r7, 0x80070000; 356 R0.H = ASHIFT R0.H BY R5.L (S); 357 R1.H = ASHIFT R1.H BY R5.L (S); 358 R2.H = ASHIFT R2.H BY R5.L (S); 359 R3.H = ASHIFT R3.H BY R5.L (S); 360 R4.H = ASHIFT R4.H BY R5.L (S); 361 //rh5 = ashift (rh5 by rl5); 362 R6.H = ASHIFT R6.H BY R5.L (S); 363 R7.H = ASHIFT R7.H BY R5.L (S); 364 CHECKREG r0, 0xc0000000; 365 CHECKREG r1, 0xc0000000; 366 CHECKREG r2, 0xc0010000; 367 CHECKREG r3, 0xc0010000; 368 CHECKREG r4, 0xc0020000; 369 //CHECKREG r5, 0x28020000; 370 CHECKREG r6, 0xc0030000; 371 CHECKREG r7, 0xc0030000; 372 373 374 imm32 r0, 0xd0010000; 375 imm32 r1, 0xd0010000; 376 imm32 r2, 0xd0020000; 377 imm32 r3, 0xd0030000; 378 imm32 r4, 0xd0040000; 379 imm32 r5, 0xd0050000; 380 R6.L = -15; 381 imm32 r7, 0xd0070000; 382 R0.L = ASHIFT R0.H BY R6.L (S); 383 R1.L = ASHIFT R1.H BY R6.L (S); 384 R2.L = ASHIFT R2.H BY R6.L (S); 385 R3.L = ASHIFT R3.H BY R6.L (S); 386 R4.L = ASHIFT R4.H BY R6.L (S); 387 R5.L = ASHIFT R5.H BY R6.L (S); 388 //rl6 = ashift (rh6 by rl6); 389 R7.L = ASHIFT R7.H BY R6.L; 390 CHECKREG r0, 0xd001ffff; 391 CHECKREG r1, 0xd001ffff; 392 CHECKREG r2, 0xd002ffff; 393 CHECKREG r3, 0xd003ffff; 394 CHECKREG r4, 0xd004ffff; 395 CHECKREG r5, 0xd005ffff; 396 //CHECKREG r6, 0x60060000; 397 CHECKREG r7, 0xd007ffff; 398 399 imm32 r0, 0xe0010000; 400 imm32 r1, 0xe0010000; 401 imm32 r2, 0xe0020000; 402 imm32 r3, 0xe0030000; 403 imm32 r4, 0xe0040000; 404 imm32 r5, 0xe0050000; 405 imm32 r6, 0xe0060000; 406 R7.L = -16; 407 R0.H = ASHIFT R0.H BY R7.L (S); 408 R1.H = ASHIFT R1.H BY R7.L (S); 409 R2.H = ASHIFT R2.H BY R7.L (S); 410 R3.H = ASHIFT R3.H BY R7.L (S); 411 R4.H = ASHIFT R4.H BY R7.L (S); 412 R5.H = ASHIFT R5.H BY R7.L (S); 413 R6.H = ASHIFT R6.H BY R7.L (S); 414 //rh7 = ashift (rh7 by rl7); 415 CHECKREG r0, 0xffff0000; 416 CHECKREG r1, 0xffff0000; 417 CHECKREG r2, 0xffff0000; 418 CHECKREG r3, 0xffff0000; 419 CHECKREG r4, 0xffff0000; 420 CHECKREG r5, 0xffff0000; 421 CHECKREG r6, 0xffff0000; 422 //CHECKREG r7, -16; 423 424 pass 425
Indexes created Wed Aug 12 00:25:48 UTC 2026