1 //Original:/testcases/core/c_dsp32shift_align24/c_dsp32shift_align24.dsp 2 // Spec Reference: dsp32shift align24 3 # mach: bfin 4 5 .include "testutils.inc" 6 start 7 8 imm32 r0, 0x00000001; 9 imm32 r1, 0x01000801; 10 imm32 r2, 0x08200802; 11 imm32 r3, 0x08030803; 12 imm32 r4, 0x08004804; 13 imm32 r5, 0x08000505; 14 imm32 r6, 0x08000866; 15 imm32 r7, 0x08000807; 16 R1 = ALIGN24 ( R1 , R0 ); 17 R2 = ALIGN24 ( R2 , R0 ); 18 R3 = ALIGN24 ( R3 , R0 ); 19 R4 = ALIGN24 ( R4 , R0 ); 20 R5 = ALIGN24 ( R5 , R0 ); 21 R6 = ALIGN24 ( R6 , R0 ); 22 R7 = ALIGN24 ( R7 , R0 ); 23 R0 = ALIGN24 ( R0 , R0 ); 24 CHECKREG r0, 0x00000100; 25 CHECKREG r1, 0x00080100; 26 CHECKREG r2, 0x20080200; 27 CHECKREG r3, 0x03080300; 28 CHECKREG r4, 0x00480400; 29 CHECKREG r5, 0x00050500; 30 CHECKREG r6, 0x00086600; 31 CHECKREG r7, 0x00080700; 32 33 imm32 r0, 0x0900d001; 34 imm32 r1, 0x09000002; 35 imm32 r2, 0x09400002; 36 imm32 r3, 0x09100003; 37 imm32 r4, 0x09020004; 38 imm32 r5, 0x09003005; 39 imm32 r6, 0x09000406; 40 imm32 r7, 0x09000057; 41 R0 = ALIGN24 ( R0 , R1 ); 42 R2 = ALIGN24 ( R2 , R1 ); 43 R3 = ALIGN24 ( R3 , R1 ); 44 R4 = ALIGN24 ( R4 , R1 ); 45 R5 = ALIGN24 ( R5 , R1 ); 46 R6 = ALIGN24 ( R6 , R1 ); 47 R7 = ALIGN24 ( R7 , R1 ); 48 R1 = ALIGN24 ( R1 , R1 ); 49 CHECKREG r0, 0x00D00109; 50 CHECKREG r1, 0x00000209; 51 CHECKREG r2, 0x40000209; 52 CHECKREG r3, 0x10000309; 53 CHECKREG r4, 0x02000409; 54 CHECKREG r5, 0x00300509; 55 CHECKREG r6, 0x00040609; 56 CHECKREG r7, 0x00005709; 57 58 59 imm32 r0, 0x0a00e001; 60 imm32 r1, 0x0a00e001; 61 imm32 r2, 0x0a00000f; 62 imm32 r3, 0x0a400010; 63 imm32 r4, 0x0a05e004; 64 imm32 r5, 0x0a006005; 65 imm32 r6, 0x0a00e706; 66 imm32 r7, 0x0a00e087; 67 R0 = ALIGN24 ( R0 , R2 ); 68 R1 = ALIGN24 ( R1 , R2 ); 69 R3 = ALIGN24 ( R3 , R2 ); 70 R4 = ALIGN24 ( R4 , R2 ); 71 R5 = ALIGN24 ( R5 , R2 ); 72 R6 = ALIGN24 ( R6 , R2 ); 73 R7 = ALIGN24 ( R7 , R2 ); 74 R2 = ALIGN24 ( R2 , R2 ); 75 CHECKREG r0, 0x00E0010A; 76 CHECKREG r1, 0x00E0010A; 77 CHECKREG r2, 0x00000F0A; 78 CHECKREG r3, 0x4000100A; 79 CHECKREG r4, 0x05E0040A; 80 CHECKREG r5, 0x0060050A; 81 CHECKREG r6, 0x00E7060A; 82 CHECKREG r7, 0x00E0870A; 83 84 imm32 r0, 0x2b00f001; 85 imm32 r1, 0x0300f001; 86 imm32 r2, 0x0b40f002; 87 imm32 r3, 0x0b050010; 88 imm32 r4, 0x0b006004; 89 imm32 r5, 0x0b00f705; 90 imm32 r6, 0x0b00f086; 91 imm32 r7, 0x0b00f009; 92 R0 = ALIGN24 ( R0 , R3 ); 93 R1 = ALIGN24 ( R1 , R3 ); 94 R2 = ALIGN24 ( R2 , R3 ); 95 R4 = ALIGN24 ( R4 , R3 ); 96 R5 = ALIGN24 ( R5 , R3 ); 97 R6 = ALIGN24 ( R6 , R3 ); 98 R7 = ALIGN24 ( R7 , R3 ); 99 R3 = ALIGN24 ( R3 , R3 ); 100 CHECKREG r0, 0x00F0010B; 101 CHECKREG r1, 0x00F0010B; 102 CHECKREG r2, 0x40F0020B; 103 CHECKREG r3, 0x0500100B; 104 CHECKREG r4, 0x0060040B; 105 CHECKREG r5, 0x00F7050B; 106 CHECKREG r6, 0x00F0860B; 107 CHECKREG r7, 0x00F0090B; 108 109 imm32 r0, 0x4c0000c0; 110 imm32 r1, 0x050100c0; 111 imm32 r2, 0x0c6200c0; 112 imm32 r3, 0x0c0700c0; 113 imm32 r4, 0x0c04800c; 114 imm32 r5, 0x0c0509c0; 115 imm32 r6, 0x0c060000; 116 imm32 r7, 0x0c0700ca; 117 R0 = ALIGN24 ( R0 , R4 ); 118 R1 = ALIGN24 ( R1 , R4 ); 119 R2 = ALIGN24 ( R2 , R4 ); 120 R3 = ALIGN24 ( R3 , R4 ); 121 R5 = ALIGN24 ( R5 , R4 ); 122 R6 = ALIGN24 ( R6 , R4 ); 123 R7 = ALIGN24 ( R7 , R4 ); 124 R4 = ALIGN24 ( R4 , R4 ); 125 CHECKREG r0, 0x0000C00C; 126 CHECKREG r1, 0x0100C00C; 127 CHECKREG r2, 0x6200C00C; 128 CHECKREG r3, 0x0700C00C; 129 CHECKREG r4, 0x04800C0C; 130 CHECKREG r5, 0x0509C00C; 131 CHECKREG r6, 0x0600000C; 132 CHECKREG r7, 0x0700CA0C; 133 134 imm32 r0, 0xa00100d0; 135 imm32 r1, 0xa00100d1; 136 imm32 r2, 0xa00200d0; 137 imm32 r3, 0xa00300d0; 138 imm32 r4, 0xa00400d0; 139 imm32 r5, 0xa0050007; 140 imm32 r6, 0xa00600d0; 141 imm32 r7, 0xa00700d0; 142 R0 = ALIGN24 ( R0 , R5 ); 143 R1 = ALIGN24 ( R1 , R5 ); 144 R2 = ALIGN24 ( R2 , R5 ); 145 R3 = ALIGN24 ( R3 , R5 ); 146 R4 = ALIGN24 ( R4 , R5 ); 147 R6 = ALIGN24 ( R6 , R5 ); 148 R7 = ALIGN24 ( R7 , R5 ); 149 R5 = ALIGN24 ( R5 , R5 ); 150 CHECKREG r0, 0x0100D0A0; 151 CHECKREG r1, 0x0100D1A0; 152 CHECKREG r2, 0x0200D0A0; 153 CHECKREG r3, 0x0300D0A0; 154 CHECKREG r4, 0x0400D0A0; 155 CHECKREG r5, 0x050007A0; 156 CHECKREG r6, 0x0600D0A0; 157 CHECKREG r7, 0x0700D0A0; 158 159 imm32 r0, 0xb2010000; 160 imm32 r1, 0xb0310000; 161 imm32 r2, 0xb042000f; 162 imm32 r3, 0xbf030000; 163 imm32 r4, 0xba040000; 164 imm32 r5, 0xbb050000; 165 imm32 r6, 0xbc060009; 166 imm32 r7, 0xb0e70000; 167 R0 = ALIGN24 ( R0 , R6 ); 168 R1 = ALIGN24 ( R1 , R6 ); 169 R2 = ALIGN24 ( R2 , R6 ); 170 R3 = ALIGN24 ( R3 , R6 ); 171 R4 = ALIGN24 ( R4 , R6 ); 172 R5 = ALIGN24 ( R5 , R6 ); 173 R6 = ALIGN24 ( R6 , R6 ); 174 R7 = ALIGN24 ( R7 , R6 ); 175 CHECKREG r0, 0x010000BC; 176 CHECKREG r1, 0x310000BC; 177 CHECKREG r2, 0x42000FBC; 178 CHECKREG r3, 0x030000BC; 179 CHECKREG r4, 0x040000BC; 180 CHECKREG r5, 0x050000BC; 181 CHECKREG r6, 0x060009BC; 182 CHECKREG r7, 0xE7000006; 183 184 imm32 r0, 0xd23100e0; 185 imm32 r1, 0xd04500e0; 186 imm32 r2, 0xde32f0e0; 187 imm32 r3, 0xd90300e0; 188 imm32 r4, 0xd07400e0; 189 imm32 r5, 0xdef500e0; 190 imm32 r6, 0xd06600e0; 191 imm32 r7, 0xd0080023; 192 R1 = ALIGN24 ( R0 , R7 ); 193 R2 = ALIGN24 ( R1 , R7 ); 194 R3 = ALIGN24 ( R2 , R7 ); 195 R4 = ALIGN24 ( R3 , R7 ); 196 R5 = ALIGN24 ( R4 , R7 ); 197 R6 = ALIGN24 ( R5 , R7 ); 198 R7 = ALIGN24 ( R6 , R7 ); 199 R0 = ALIGN24 ( R7 , R7 ); 200 CHECKREG r0, 0xD0D0D0D0; 201 CHECKREG r1, 0x3100E0D0; 202 CHECKREG r2, 0x00E0D0D0; 203 CHECKREG r3, 0xE0D0D0D0; 204 CHECKREG r4, 0xD0D0D0D0; 205 CHECKREG r5, 0xD0D0D0D0; 206 CHECKREG r6, 0xD0D0D0D0; 207 CHECKREG r7, 0xD0D0D0D0; 208 209 210 pass 211
Indexes created Wed Aug 12 00:25:48 UTC 2026