1 //Original:/testcases/core/c_dsp32shiftim_ahalf_ln_s/c_dsp32shiftim_ahalf_ln_s.dsp 2 // Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated 3 # mach: bfin 4 5 .include "testutils.inc" 6 start 7 8 9 10 // Ashift : neg data, count (+)=left (half reg) 11 // d_lo = ashft (d_lo BY d_lo) 12 // RLx by RLx 13 imm32 r0, 0x1000c000; 14 imm32 r1, 0x1000c001; 15 imm32 r2, 0x1000c002; 16 imm32 r3, 0x1000c003; 17 imm32 r4, 0x1000c004; 18 imm32 r5, 0x1000c005; 19 imm32 r6, 0x1000c006; 20 imm32 r7, 0x1000c007; 21 R0.L = R0.L << 1 (S); 22 R1.L = R1.L << 1 (S); 23 R2.L = R2.L << 1 (S); 24 R3.L = R3.L << 1 (S); 25 R4.L = R4.L << 1 (S); 26 R5.L = R5.L << 1 (S); 27 R6.L = R6.L << 1 (S); 28 R7.L = R7.L << 1 (S); 29 CHECKREG r0, 0x10008000; 30 CHECKREG r1, 0x10008002; 31 CHECKREG r2, 0x10008004; 32 CHECKREG r3, 0x10008006; 33 CHECKREG r4, 0x10008008; 34 CHECKREG r5, 0x1000800A; 35 CHECKREG r6, 0x1000800C; 36 CHECKREG r7, 0x1000800E; 37 38 imm32 r0, 0x20008001; 39 imm32 r1, 0x20000001; 40 imm32 r2, 0x2000d002; 41 imm32 r3, 0x2000e003; 42 imm32 r4, 0x2000f004; 43 imm32 r5, 0x2000c005; 44 imm32 r6, 0x2000d006; 45 imm32 r7, 0x2000e007; 46 R7.L = R0.L << 1 (S); 47 R6.L = R1.L << 1 (S); 48 R5.L = R2.L << 1 (S); 49 R4.L = R3.L << 1 (S); 50 R3.L = R4.L << 1 (S); 51 R2.L = R5.L << 1 (S); 52 R1.L = R6.L << 1 (S); 53 R0.L = R7.L << 1 (S); 54 55 imm32 r0, 0x3000c001; 56 imm32 r1, 0x3000d001; 57 imm32 r2, 0x3000000f; 58 imm32 r3, 0x3000e003; 59 imm32 r4, 0x3000f004; 60 imm32 r5, 0x3000f005; 61 imm32 r6, 0x3000f006; 62 imm32 r7, 0x3000f007; 63 R6.L = R0.L << 12 (S); 64 R7.L = R1.L << 12 (S); 65 R5.L = R2.L << 12 (S); 66 R4.L = R3.L << 12 (S); 67 R3.L = R4.L << 12 (S); 68 R2.L = R5.L << 12 (S); 69 R1.L = R6.L << 12 (S); 70 R0.L = R7.L << 12 (S); 71 CHECKREG r1, 0x30008000; 72 CHECKREG r0, 0x30008000; 73 CHECKREG r2, 0x30007FFF; 74 CHECKREG r3, 0x30008000; 75 CHECKREG r4, 0x30008000; 76 CHECKREG r5, 0x30007FFF; 77 CHECKREG r6, 0x30008000; 78 CHECKREG r7, 0x30008000; 79 80 imm32 r0, 0x40009001; 81 imm32 r1, 0x4000a001; 82 imm32 r2, 0x4000b002; 83 imm32 r3, 0x40000010; 84 imm32 r4, 0x4000c004; 85 imm32 r5, 0x4000d005; 86 imm32 r6, 0x4000e006; 87 imm32 r7, 0x4000f007; 88 R5.L = R0.L << 13 (S); 89 R6.L = R1.L << 13 (S); 90 R7.L = R2.L << 13 (S); 91 R0.L = R3.L << 13 (S); 92 R1.L = R4.L << 13 (S); 93 R2.L = R5.L << 13 (S); 94 R3.L = R6.L << 13 (S); 95 R4.L = R7.L << 13 (S); 96 CHECKREG r0, 0x40007FFF; 97 CHECKREG r1, 0x40008000; 98 CHECKREG r2, 0x40008000; 99 CHECKREG r3, 0x40008000; 100 CHECKREG r4, 0x40008000; 101 CHECKREG r5, 0x40008000; 102 CHECKREG r6, 0x40008000; 103 CHECKREG r7, 0x40008000; 104 105 imm32 r0, 0x00005000; 106 imm32 r1, 0x00015000; 107 imm32 r2, 0x00025000; 108 imm32 r3, 0x00035000; 109 imm32 r4, 0x00045000; 110 imm32 r5, 0x00055000; 111 imm32 r6, 0x00065000; 112 imm32 r7, 0x00075500; 113 R0.L = R0.H << 10 (S); 114 R1.L = R1.H << 10 (S); 115 R2.L = R2.H << 10 (S); 116 R3.L = R3.H << 10 (S); 117 R4.L = R4.H << 10 (S); 118 R5.L = R5.H << 10 (S); 119 R6.L = R6.H << 10 (S); 120 R7.L = R7.H << 10 (S); 121 CHECKREG r0, 0x00000000; 122 CHECKREG r1, 0x00010400; 123 CHECKREG r2, 0x00020800; 124 CHECKREG r3, 0x00030C00; 125 CHECKREG r4, 0x00041000; 126 CHECKREG r5, 0x00051400; 127 CHECKREG r6, 0x00061800; 128 CHECKREG r7, 0x00071C00; 129 130 imm32 r0, 0x90010000; 131 imm32 r1, 0x90010001; 132 imm32 r2, 0x90020000; 133 imm32 r3, 0x90030000; 134 imm32 r4, 0x90040000; 135 imm32 r5, 0x90050000; 136 imm32 r6, 0x90060000; 137 imm32 r7, 0x90070000; 138 R2.L = R0.H << 11 (S); 139 R3.L = R1.H << 11 (S); 140 R4.L = R2.H << 11 (S); 141 R5.L = R3.H << 11 (S); 142 R6.L = R4.H << 11 (S); 143 R7.L = R5.H << 11 (S); 144 R0.L = R6.H << 11 (S); 145 R1.L = R7.H << 11 (S); 146 CHECKREG r0, 0x90018000; 147 CHECKREG r1, 0x90018000; 148 CHECKREG r2, 0x90028000; 149 CHECKREG r3, 0x90038000; 150 CHECKREG r4, 0x90048000; 151 CHECKREG r5, 0x90058000; 152 CHECKREG r6, 0x90068000; 153 CHECKREG r7, 0x90078000; 154 155 156 imm32 r0, 0xa0010600; 157 imm32 r1, 0xa0010600; 158 imm32 r2, 0xa002060f; 159 imm32 r3, 0xa0030600; 160 imm32 r4, 0xa0040600; 161 imm32 r5, 0xa0050600; 162 imm32 r6, 0xa0060600; 163 imm32 r7, 0xa0070600; 164 R0.L = R0.H << 12 (S); 165 R1.L = R1.H << 12 (S); 166 R2.L = R2.H << 12 (S); 167 R3.L = R3.H << 12 (S); 168 R4.L = R4.H << 12 (S); 169 R5.L = R5.H << 12 (S); 170 R6.L = R6.H << 12 (S); 171 R7.L = R7.H << 12 (S); 172 CHECKREG r0, 0xA0018000; 173 CHECKREG r1, 0xA0018000; 174 CHECKREG r2, 0xA0028000; 175 CHECKREG r3, 0xA0038000; 176 CHECKREG r4, 0xA0048000; 177 CHECKREG r5, 0xA0058000; 178 CHECKREG r6, 0xA0068000; 179 CHECKREG r7, 0xA0078000; 180 181 imm32 r0, 0xc0010701; 182 imm32 r1, 0xc0010701; 183 imm32 r2, 0xc0020702; 184 imm32 r3, 0xc0030710; 185 imm32 r4, 0xc0040704; 186 imm32 r5, 0xc0050705; 187 imm32 r6, 0xc0060706; 188 imm32 r7, 0xc0070707; 189 R0.L = R0.H << 13 (S); 190 R1.L = R1.H << 13 (S); 191 R2.L = R2.H << 13 (S); 192 R3.L = R3.H << 13 (S); 193 R4.L = R4.H << 13 (S); 194 R5.L = R5.H << 13 (S); 195 R6.L = R6.H << 13 (S); 196 R7.L = R7.H << 13 (S); 197 CHECKREG r0, 0xC0018000; 198 CHECKREG r1, 0xC0018000; 199 CHECKREG r2, 0xC0028000; 200 CHECKREG r3, 0xC0038000; 201 CHECKREG r4, 0xC0048000; 202 CHECKREG r5, 0xC0058000; 203 CHECKREG r6, 0xC0068000; 204 CHECKREG r7, 0xC0078000; 205 206 imm32 r0, 0x00008000; 207 imm32 r1, 0x00008001; 208 imm32 r2, 0x00008002; 209 imm32 r3, 0x00008003; 210 imm32 r4, 0x00008004; 211 imm32 r5, 0x00008005; 212 imm32 r6, 0x00008006; 213 imm32 r7, 0x00008007; 214 R0.H = R0.L << 0 (S); 215 R1.H = R1.L << 1 (S); 216 R2.H = R2.L << 2 (S); 217 R3.H = R3.L << 3 (S); 218 R4.H = R4.L << 4 (S); 219 R5.H = R5.L << 5 (S); 220 R6.H = R6.L << 6 (S); 221 R7.H = R7.L << 7 (S); 222 CHECKREG r0, 0x80008000; 223 CHECKREG r1, 0x80008001; 224 CHECKREG r2, 0x80008002; 225 CHECKREG r3, 0x80008003; 226 CHECKREG r4, 0x80008004; 227 CHECKREG r5, 0x80008005; 228 CHECKREG r6, 0x80008006; 229 CHECKREG r7, 0x80008007; 230 231 imm32 r0, 0x0000d001; 232 imm32 r1, 0x00000001; 233 imm32 r2, 0x0000d002; 234 imm32 r3, 0x0000d003; 235 imm32 r4, 0x0000d004; 236 imm32 r5, 0x0000d005; 237 imm32 r6, 0x0000d006; 238 imm32 r7, 0x0000d007; 239 R2.H = R0.L << 8 (S); 240 R3.H = R1.L << 9 (S); 241 R4.H = R2.L << 10 (S); 242 R5.H = R3.L << 11 (S); 243 R6.H = R4.L << 12 (S); 244 R7.H = R5.L << 13 (S); 245 R0.H = R6.L << 14 (S); 246 R1.H = R7.L << 15 (S); 247 CHECKREG r0, 0x8000D001; 248 CHECKREG r1, 0x80000001; 249 CHECKREG r2, 0x8000D002; 250 CHECKREG r3, 0x0200D003; 251 CHECKREG r4, 0x8000D004; 252 CHECKREG r5, 0x8000D005; 253 CHECKREG r6, 0x8000D006; 254 CHECKREG r7, 0x8000D007; 255 256 imm32 r0, 0x0000e001; 257 imm32 r1, 0x0000e001; 258 imm32 r2, 0x0000000f; 259 imm32 r3, 0x0000e003; 260 imm32 r4, 0x0000e004; 261 imm32 r5, 0x0000e005; 262 imm32 r6, 0x0000e006; 263 imm32 r7, 0x0000e007; 264 R0.H = R0.L << 12 (S); 265 R1.H = R1.L << 12 (S); 266 R2.H = R2.L << 12 (S); 267 R3.H = R3.L << 12 (S); 268 R4.H = R4.L << 12 (S); 269 R5.H = R5.L << 12 (S); 270 R6.H = R6.L << 12 (S); 271 R7.H = R7.L << 12 (S); 272 CHECKREG r0, 0x8000E001; 273 CHECKREG r1, 0x8000E001; 274 CHECKREG r2, 0x7FFF000F; 275 CHECKREG r3, 0x8000E003; 276 CHECKREG r4, 0x8000E004; 277 CHECKREG r5, 0x8000E005; 278 CHECKREG r6, 0x8000E006; 279 CHECKREG r7, 0x8000E007; 280 281 imm32 r0, 0x0000f001; 282 imm32 r1, 0x0000f001; 283 imm32 r2, 0x0000f002; 284 imm32 r3, 0x00000010; 285 imm32 r4, 0x0000f004; 286 imm32 r5, 0x0000f005; 287 imm32 r6, 0x0000f006; 288 imm32 r7, 0x0000f007; 289 R5.H = R0.L << 13 (S); 290 R6.H = R1.L << 13 (S); 291 R7.H = R2.L << 13 (S); 292 R0.H = R3.L << 13 (S); 293 R1.H = R4.L << 13 (S); 294 R2.H = R5.L << 13 (S); 295 R3.H = R6.L << 13 (S); 296 R4.H = R7.L << 13 (S); 297 CHECKREG r0, 0x7FFFF001; 298 CHECKREG r1, 0x8000F001; 299 CHECKREG r2, 0x8000F002; 300 CHECKREG r3, 0x80000010; 301 CHECKREG r4, 0x8000F004; 302 CHECKREG r5, 0x8000F005; 303 CHECKREG r6, 0x8000F006; 304 CHECKREG r7, 0x8000F007; 305 306 // d_lo = ashift (d_hi BY d_lo) 307 // RHx by RLx 308 imm32 r0, 0x90000000; 309 imm32 r1, 0x90010000; 310 imm32 r2, 0x90020000; 311 imm32 r3, 0x90030000; 312 imm32 r4, 0x90040000; 313 imm32 r5, 0x90050000; 314 imm32 r6, 0x90060000; 315 imm32 r7, 0x90070000; 316 R4.H = R0.H << 10 (S); 317 R5.H = R1.H << 10 (S); 318 R6.H = R2.H << 10 (S); 319 R7.H = R3.H << 10 (S); 320 R0.H = R4.H << 10 (S); 321 R1.H = R5.H << 10 (S); 322 R2.H = R6.H << 10 (S); 323 R3.H = R7.H << 10 (S); 324 CHECKREG r0, 0x80000000; 325 CHECKREG r1, 0x80000000; 326 CHECKREG r2, 0x80000000; 327 CHECKREG r3, 0x80000000; 328 CHECKREG r4, 0x80000000; 329 CHECKREG r5, 0x80000000; 330 CHECKREG r6, 0x80000000; 331 CHECKREG r7, 0x80000000; 332 333 imm32 r0, 0xa0010000; 334 imm32 r1, 0x00010001; 335 imm32 r2, 0xa0020000; 336 imm32 r3, 0xa0030000; 337 imm32 r4, 0xa0040000; 338 imm32 r5, 0xa0050000; 339 imm32 r6, 0xa0060000; 340 imm32 r7, 0xa0070000; 341 R7.H = R0.H << 11 (S); 342 R0.H = R1.H << 11 (S); 343 R1.H = R2.H << 11 (S); 344 R2.H = R3.H << 11 (S); 345 R3.H = R4.H << 11 (S); 346 R4.H = R5.H << 11 (S); 347 R5.H = R6.H << 11 (S); 348 R6.H = R7.H << 11 (S); 349 CHECKREG r0, 0x08000000; 350 CHECKREG r1, 0x80000001; 351 CHECKREG r2, 0x80000000; 352 CHECKREG r3, 0x80000000; 353 CHECKREG r4, 0x80000000; 354 CHECKREG r5, 0x80000000; 355 CHECKREG r6, 0x80000000; 356 CHECKREG r7, 0x80000000; 357 358 359 imm32 r0, 0xb0010000; 360 imm32 r1, 0xb0010000; 361 imm32 r2, 0xb002000f; 362 imm32 r3, 0xb0030000; 363 imm32 r4, 0xb0040000; 364 imm32 r5, 0xb0050000; 365 imm32 r6, 0xb0060000; 366 imm32 r7, 0xb0070000; 367 R6.H = R0.H << 12 (S); 368 R7.H = R1.H << 12 (S); 369 R0.H = R2.H << 12 (S); 370 R1.H = R3.H << 12 (S); 371 R2.H = R4.H << 12 (S); 372 R3.H = R5.H << 12 (S); 373 R4.H = R6.H << 12 (S); 374 R5.H = R7.H << 12 (S); 375 CHECKREG r0, 0x80000000; 376 CHECKREG r1, 0x80000000; 377 CHECKREG r2, 0x8000000F; 378 CHECKREG r3, 0x80000000; 379 CHECKREG r4, 0x80000000; 380 CHECKREG r5, 0x80000000; 381 CHECKREG r6, 0x80000000; 382 CHECKREG r7, 0x80000000; 383 384 imm32 r0, 0xd0010000; 385 imm32 r1, 0xd0010000; 386 imm32 r2, 0xd0020000; 387 imm32 r3, 0xd0030010; 388 imm32 r4, 0xd0040000; 389 imm32 r5, 0xd0050000; 390 imm32 r6, 0xd0060000; 391 imm32 r7, 0xd0070000; 392 R5.H = R0.H << 3 (S); 393 R6.H = R1.H << 3 (S); 394 R7.H = R2.H << 3 (S); 395 R0.H = R3.H << 3 (S); 396 R1.H = R4.H << 3 (S); 397 R2.H = R5.H << 3 (S); 398 R3.H = R6.H << 3 (S); 399 R4.H = R7.H << 3 (S); 400 CHECKREG r0, 0x80000000; 401 CHECKREG r1, 0x80000000; 402 CHECKREG r2, 0x80000000; 403 CHECKREG r3, 0x80000010; 404 CHECKREG r4, 0x80000000; 405 CHECKREG r5, 0x80000000; 406 CHECKREG r6, 0x80000000; 407 CHECKREG r7, 0x80000000; 408 pass 409
Indexes created Tue Aug 11 00:25:38 UTC 2026