1 //Original:/testcases/core/c_dsp32shiftim_ahalf_lp_s/c_dsp32shiftim_ahalf_lp_s.dsp 2 // Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated 3 # mach: bfin 4 5 .include "testutils.inc" 6 start 7 8 9 10 imm32 r0, 0x00100a00; 11 imm32 r1, 0x00100a01; 12 imm32 r2, 0x00100a02; 13 imm32 r3, 0x00100a03; 14 imm32 r4, 0x00100a04; 15 imm32 r5, 0x00100a05; 16 imm32 r6, 0x00100a06; 17 imm32 r7, 0x00100a07; 18 R7.L = R0.L << 0 (S); 19 R0.L = R1.L << 1 (S); 20 R1.L = R2.L << 2 (S); 21 R2.L = R3.L << 3 (S); 22 R3.L = R4.L << 4 (S); 23 R4.L = R5.L << 5 (S); 24 R5.L = R6.L << 6 (S); 25 R6.L = R7.L << 7 (S); 26 CHECKREG r1, 0x00102808; 27 CHECKREG r0, 0x00101402; 28 CHECKREG r2, 0x00105018; 29 CHECKREG r3, 0x00107FFF; 30 CHECKREG r4, 0x00107FFF; 31 CHECKREG r5, 0x00107FFF; 32 CHECKREG r6, 0x00107FFF; 33 CHECKREG r7, 0x00100A00; 34 35 imm32 r0, 0x00200018; 36 imm32 r1, 0x00200019; 37 imm32 r2, 0x0020001a; 38 imm32 r3, 0x0020001b; 39 imm32 r4, 0x0020001c; 40 imm32 r5, 0x0020001d; 41 imm32 r6, 0x0020001e; 42 imm32 r7, 0x0020001f; 43 R2.L = R0.L << 8 (S); 44 R3.L = R1.L << 9 (S); 45 R4.L = R2.L << 10 (S); 46 R5.L = R3.L << 11 (S); 47 R6.L = R4.L << 12 (S); 48 R7.L = R5.L << 13 (S); 49 R0.L = R6.L << 14 (S); 50 R1.L = R7.L << 15 (S); 51 CHECKREG r0, 0x00207FFF; 52 CHECKREG r1, 0x00207FFF; 53 CHECKREG r2, 0x00201800; 54 CHECKREG r3, 0x00203200; 55 CHECKREG r4, 0x00207FFF; 56 CHECKREG r5, 0x00207FFF; 57 CHECKREG r6, 0x00207FFF; 58 CHECKREG r7, 0x00207FFF; 59 60 imm32 r0, 0x05002001; 61 imm32 r1, 0x05002001; 62 imm32 r2, 0x0500000f; 63 imm32 r3, 0x05002003; 64 imm32 r4, 0x05002004; 65 imm32 r5, 0x05002005; 66 imm32 r6, 0x05002006; 67 imm32 r7, 0x05002007; 68 R3.L = R0.L << 0 (S); 69 R4.L = R1.L << 1 (S); 70 R5.L = R2.L << 2 (S); 71 R6.L = R3.L << 3 (S); 72 R7.L = R4.L << 4 (S); 73 R0.L = R5.L << 5 (S); 74 R1.L = R6.L << 6 (S); 75 R2.L = R7.L << 7 (S); 76 CHECKREG r0, 0x05000780; 77 CHECKREG r1, 0x05007FFF; 78 CHECKREG r2, 0x05007FFF; 79 CHECKREG r3, 0x05002001; 80 CHECKREG r4, 0x05004002; 81 CHECKREG r5, 0x0500003C; 82 CHECKREG r6, 0x05007FFF; 83 CHECKREG r7, 0x05007FFF; 84 85 imm32 r0, 0x03000031; 86 imm32 r1, 0x03000031; 87 imm32 r2, 0x03000032; 88 imm32 r3, 0x03000030; 89 imm32 r4, 0x03000034; 90 imm32 r5, 0x03000035; 91 imm32 r6, 0x03000036; 92 imm32 r7, 0x03000037; 93 R4.L = R0.L << 8 (S); 94 R5.L = R1.L << 9 (S); 95 R6.L = R2.L << 10 (S); 96 R7.L = R3.L << 11 (S); 97 R0.L = R4.L << 12 (S); 98 R1.L = R5.L << 13 (S); 99 R2.L = R6.L << 14 (S); 100 R3.L = R7.L << 15 (S); 101 CHECKREG r0, 0x03007FFF; 102 CHECKREG r1, 0x03007FFF; 103 CHECKREG r2, 0x03007FFF; 104 CHECKREG r3, 0x03007FFF; 105 CHECKREG r4, 0x03003100; 106 CHECKREG r5, 0x03006200; 107 CHECKREG r6, 0x03007FFF; 108 CHECKREG r7, 0x03007FFF; 109 // RHx by RLx 110 imm32 r0, 0x03000000; 111 imm32 r1, 0x03000000; 112 imm32 r2, 0x03000000; 113 imm32 r3, 0x03000000; 114 imm32 r4, 0x03003100; 115 imm32 r5, 0x03006200; 116 imm32 r6, 0x0300C800; 117 imm32 r7, 0x03008000; 118 R5.L = R0.H << 0 (S); 119 R6.L = R1.H << 1 (S); 120 R7.L = R2.H << 2 (S); 121 R0.L = R3.H << 3 (S); 122 R1.L = R4.H << 4 (S); 123 R2.L = R5.H << 5 (S); 124 R3.L = R6.H << 6 (S); 125 R4.L = R7.H << 7 (S); 126 CHECKREG r0, 0x03001800; 127 CHECKREG r1, 0x03003000; 128 CHECKREG r2, 0x03006000; 129 CHECKREG r3, 0x03007FFF; 130 CHECKREG r4, 0x03007FFF; 131 CHECKREG r5, 0x03000300; 132 CHECKREG r6, 0x03000600; 133 CHECKREG r7, 0x03000C00; 134 135 imm32 r0, 0x05018000; 136 imm32 r1, 0x05018001; 137 imm32 r2, 0x05028000; 138 imm32 r3, 0x05038000; 139 imm32 r4, 0x05048000; 140 imm32 r5, 0x05058000; 141 imm32 r6, 0x05068000; 142 imm32 r7, 0x05078000; 143 R6.L = R0.H << 8 (S); 144 R7.L = R1.H << 9 (S); 145 R0.L = R2.H << 10 (S); 146 R1.L = R3.H << 11 (S); 147 R2.L = R4.H << 12 (S); 148 R3.L = R5.H << 13 (S); 149 R4.L = R6.H << 14 (S); 150 R5.L = R7.H << 15 (S); 151 CHECKREG r0, 0x05017FFF; 152 CHECKREG r1, 0x05017FFF; 153 CHECKREG r2, 0x05027FFF; 154 CHECKREG r3, 0x05037FFF; 155 CHECKREG r4, 0x05047FFF; 156 CHECKREG r5, 0x05057FFF; 157 CHECKREG r6, 0x05067FFF; 158 CHECKREG r7, 0x05077FFF; 159 160 161 imm32 r0, 0x60019000; 162 imm32 r1, 0x60019000; 163 imm32 r2, 0x6002900f; 164 imm32 r3, 0x60039000; 165 imm32 r4, 0x60049000; 166 imm32 r5, 0x60059000; 167 imm32 r6, 0x60069000; 168 imm32 r7, 0x60079000; 169 R7.L = R0.H << 0 (S); 170 R0.L = R1.H << 1 (S); 171 R1.L = R2.H << 2 (S); 172 R2.L = R3.H << 3 (S); 173 R3.L = R4.H << 4 (S); 174 R4.L = R5.H << 5 (S); 175 R5.L = R6.H << 6 (S); 176 R6.L = R7.H << 7 (S); 177 CHECKREG r0, 0x60017FFF; 178 CHECKREG r1, 0x60017FFF; 179 CHECKREG r2, 0x60027FFF; 180 CHECKREG r3, 0x60037FFF; 181 CHECKREG r4, 0x60047FFF; 182 CHECKREG r5, 0x60057FFF; 183 CHECKREG r6, 0x60067FFF; 184 CHECKREG r7, 0x60076001; 185 186 imm32 r0, 0x70010001; 187 imm32 r1, 0x70010001; 188 imm32 r2, 0x70020002; 189 imm32 r3, 0x77030010; 190 imm32 r4, 0x70040004; 191 imm32 r5, 0x70050005; 192 imm32 r6, 0x70060006; 193 imm32 r7, 0x70070007; 194 R0.L = R0.H << 8 (S); 195 R1.L = R1.H << 9 (S); 196 R2.L = R2.H << 10 (S); 197 R3.L = R3.H << 11 (S); 198 R4.L = R4.H << 12 (S); 199 R5.L = R5.H << 13 (S); 200 R6.L = R6.H << 14 (S); 201 R7.L = R7.H << 15 (S); 202 CHECKREG r0, 0x70017FFF; 203 CHECKREG r1, 0x70017FFF; 204 CHECKREG r2, 0x70027FFF; 205 CHECKREG r3, 0x77037FFF; 206 CHECKREG r4, 0x70047FFF; 207 CHECKREG r5, 0x70057FFF; 208 CHECKREG r6, 0x70067FFF; 209 CHECKREG r7, 0x70077FFF; 210 211 // d_hi = lshft (d_lo BY d_lo) 212 // RLx by RLx 213 imm32 r0, 0xa8000000; 214 imm32 r1, 0xa8000001; 215 imm32 r2, 0xa8000002; 216 imm32 r3, 0xa8000003; 217 imm32 r4, 0xa8000004; 218 imm32 r5, 0xa8000005; 219 imm32 r6, 0xa8000006; 220 imm32 r7, 0xa8000007; 221 R0.H = R0.L << 0 (S); 222 R1.H = R1.L << 1 (S); 223 R2.H = R2.L << 2 (S); 224 R3.H = R3.L << 3 (S); 225 R4.H = R4.L << 4 (S); 226 R5.H = R5.L << 5 (S); 227 R6.H = R6.L << 6 (S); 228 R7.H = R7.L << 7 (S); 229 CHECKREG r0, 0x00000000; 230 CHECKREG r1, 0x00020001; 231 CHECKREG r2, 0x00080002; 232 CHECKREG r3, 0x00180003; 233 CHECKREG r4, 0x00400004; 234 CHECKREG r5, 0x00A00005; 235 CHECKREG r6, 0x01800006; 236 CHECKREG r7, 0x03800007; 237 238 imm32 r0, 0xf0090001; 239 imm32 r1, 0xf0090001; 240 imm32 r2, 0xf0090002; 241 imm32 r3, 0xf0090003; 242 imm32 r4, 0xf0090004; 243 imm32 r5, 0xf0090005; 244 imm32 r6, 0xf0000006; 245 imm32 r7, 0xf0000007; 246 R1.H = R0.L << 8 (S); 247 R2.H = R1.L << 9 (S); 248 R3.H = R2.L << 10 (S); 249 R4.H = R3.L << 11 (S); 250 R5.H = R4.L << 12 (S); 251 R6.H = R5.L << 13 (S); 252 R7.H = R6.L << 14 (S); 253 R0.H = R7.L << 15 (S); 254 CHECKREG r1, 0x01000001; 255 CHECKREG r2, 0x02000002; 256 CHECKREG r3, 0x08000003; 257 CHECKREG r4, 0x18000004; 258 CHECKREG r5, 0x40000005; 259 CHECKREG r6, 0x7FFF0006; 260 CHECKREG r7, 0x7FFF0007; 261 CHECKREG r0, 0x7FFF0001; 262 263 264 imm32 r0, 0x07000001; 265 imm32 r1, 0x07000001; 266 imm32 r2, 0x0700000f; 267 imm32 r3, 0x07000003; 268 imm32 r4, 0x07000004; 269 imm32 r5, 0x07000005; 270 imm32 r6, 0x07000006; 271 imm32 r7, 0x07000007; 272 R3.H = R0.L << 0 (S); 273 R4.H = R1.L << 1 (S); 274 R5.H = R2.L << 2 (S); 275 R6.H = R3.L << 3 (S); 276 R7.H = R4.L << 4 (S); 277 R0.H = R5.L << 5 (S); 278 R1.H = R6.L << 6 (S); 279 R2.H = R7.L << 7 (S); 280 CHECKREG r0, 0x00A00001; 281 CHECKREG r1, 0x01800001; 282 CHECKREG r2, 0x0380000F; 283 CHECKREG r3, 0x00010003; 284 CHECKREG r4, 0x00020004; 285 CHECKREG r5, 0x003C0005; 286 CHECKREG r6, 0x00180006; 287 CHECKREG r7, 0x00400007; 288 289 imm32 r0, 0x00000501; 290 imm32 r1, 0x00000501; 291 imm32 r2, 0x00000502; 292 imm32 r3, 0x00000510; 293 imm32 r4, 0x00000504; 294 imm32 r5, 0x00000505; 295 imm32 r6, 0x00000506; 296 imm32 r7, 0x00000507; 297 R4.H = R0.L << 8 (S); 298 R5.H = R1.L << 9 (S); 299 R6.H = R2.L << 10 (S); 300 R7.H = R3.L << 11 (S); 301 R0.H = R4.L << 12 (S); 302 R1.H = R5.L << 13 (S); 303 R2.H = R6.L << 14 (S); 304 R3.H = R7.L << 15 (S); 305 CHECKREG r0, 0x7FFF0501; 306 CHECKREG r1, 0x7FFF0501; 307 CHECKREG r2, 0x7FFF0502; 308 CHECKREG r3, 0x7FFF0510; 309 CHECKREG r4, 0x7FFF0504; 310 CHECKREG r5, 0x7FFF0505; 311 CHECKREG r6, 0x7FFF0506; 312 CHECKREG r7, 0x7FFF0507; 313 314 imm32 r0, 0x00a00800; 315 imm32 r1, 0x00a10800; 316 imm32 r2, 0x00a20800; 317 imm32 r3, 0x00a30800; 318 imm32 r4, 0x00a40800; 319 imm32 r5, 0x00a50800; 320 imm32 r6, 0x00a60800; 321 imm32 r7, 0x00a70800; 322 R5.H = R0.H << 0 (S); 323 R6.H = R1.H << 1 (S); 324 R7.H = R2.H << 2 (S); 325 R0.H = R3.H << 3 (S); 326 R1.H = R4.H << 4 (S); 327 R2.H = R5.H << 5 (S); 328 R3.H = R6.H << 6 (S); 329 R4.H = R7.H << 7 (S); 330 CHECKREG r0, 0x05180800; 331 CHECKREG r1, 0x0A400800; 332 CHECKREG r2, 0x14000800; 333 CHECKREG r3, 0x50800800; 334 CHECKREG r4, 0x7FFF0800; 335 CHECKREG r5, 0x00A00800; 336 CHECKREG r6, 0x01420800; 337 CHECKREG r7, 0x02880800; 338 339 imm32 r0, 0x0c010000; 340 imm32 r1, 0x0c010001; 341 imm32 r2, 0x0c020000; 342 imm32 r3, 0x0c030000; 343 imm32 r4, 0x0c040000; 344 imm32 r5, 0x0c050000; 345 imm32 r6, 0x0c060000; 346 imm32 r7, 0x0c070000; 347 R6.H = R0.H << 8 (S); 348 R7.H = R1.H << 9 (S); 349 R0.H = R2.H << 10 (S); 350 R1.H = R3.H << 11 (S); 351 R2.H = R4.H << 12 (S); 352 R3.H = R5.H << 13 (S); 353 R4.H = R6.H << 14 (S); 354 R5.H = R7.H << 15 (S); 355 CHECKREG r0, 0x7FFF0000; 356 CHECKREG r1, 0x7FFF0001; 357 CHECKREG r2, 0x7FFF0000; 358 CHECKREG r3, 0x7FFF0000; 359 CHECKREG r4, 0x7FFF0000; 360 CHECKREG r5, 0x7FFF0000; 361 CHECKREG r6, 0x7FFF0000; 362 CHECKREG r7, 0x7FFF0000; 363 364 365 imm32 r0, 0x00b10000; 366 imm32 r1, 0x00b10000; 367 imm32 r2, 0x00b2000f; 368 imm32 r3, 0x00b30000; 369 imm32 r4, 0x00b40000; 370 imm32 r5, 0x00b50000; 371 imm32 r6, 0x00b60000; 372 imm32 r7, 0x00b70000; 373 R7.L = R0.H << 0 (S); 374 R0.L = R1.H << 1 (S); 375 R1.L = R2.H << 2 (S); 376 R2.L = R3.H << 3 (S); 377 R3.L = R4.H << 4 (S); 378 R4.L = R5.H << 5 (S); 379 R5.L = R6.H << 6 (S); 380 R6.L = R7.H << 7 (S); 381 CHECKREG r0, 0x00B10162; 382 CHECKREG r1, 0x00B102C8; 383 CHECKREG r2, 0x00B20598; 384 CHECKREG r3, 0x00B30B40; 385 CHECKREG r4, 0x00B416A0; 386 CHECKREG r5, 0x00B52D80; 387 CHECKREG r6, 0x00B65B80; 388 CHECKREG r7, 0x00B700B1; 389 390 imm32 r0, 0x0a010700; 391 imm32 r1, 0x0a010700; 392 imm32 r2, 0x0a020700; 393 imm32 r3, 0x0a030710; 394 imm32 r4, 0x0a040700; 395 imm32 r5, 0x0a050700; 396 imm32 r6, 0x0a060700; 397 imm32 r7, 0x0a070700; 398 R0.H = R0.H << 8 (S); 399 R1.H = R1.H << 9 (S); 400 R2.H = R2.H << 10 (S); 401 R3.H = R3.H << 11 (S); 402 R4.H = R4.H << 12 (S); 403 R5.H = R5.H << 13 (S); 404 R6.H = R6.H << 14 (S); 405 R7.H = R7.H << 15 (S); 406 CHECKREG r0, 0x7FFF0700; 407 CHECKREG r1, 0x7FFF0700; 408 CHECKREG r2, 0x7FFF0700; 409 CHECKREG r3, 0x7FFF0710; 410 CHECKREG r4, 0x7FFF0700; 411 CHECKREG r5, 0x7FFF0700; 412 CHECKREG r6, 0x7FFF0700; 413 CHECKREG r7, 0x7FFF0700; 414 415 pass 416
Indexes created Tue Aug 11 00:25:38 UTC 2026