1 //Original:/testcases/core/c_dsp32shiftim_ahalf_rp_s/c_dsp32shiftim_ahalf_rp_s.dsp 2 // Spec Reference: dspshiftimm dreg_lo(hi) = ashift (dreg_lo(hi) by imm5) saturated 3 # mach: bfin 4 5 .include "testutils.inc" 6 start 7 8 9 10 // Ashift : positive data, count (+)=right (half reg) 11 // d_lo = ashft (d_lo BY d_lo) 12 // RLx by RLx 13 imm32 r0, 0x00000000; 14 R0.L = -1; 15 imm32 r1, 0x00010001; 16 imm32 r2, 0x00010002; 17 imm32 r3, 0x00010003; 18 imm32 r4, 0x00010004; 19 imm32 r5, 0x00010005; 20 imm32 r6, 0x00010006; 21 imm32 r7, 0x00010007; 22 R0.L = R0.L >>> 1; 23 R1.L = R1.L >>> 1; 24 R2.L = R2.L >>> 1; 25 R3.L = R3.L >>> 1; 26 R4.L = R4.L >>> 1; 27 R5.L = R5.L >>> 1; 28 R6.L = R6.L >>> 1; 29 R7.L = R7.L >>> 1; 30 CHECKREG r0, 0x0000FFFF; 31 CHECKREG r1, 0x00010000; 32 CHECKREG r2, 0x00010001; 33 CHECKREG r3, 0x00010001; 34 CHECKREG r4, 0x00010002; 35 CHECKREG r5, 0x00010002; 36 CHECKREG r6, 0x00010003; 37 CHECKREG r7, 0x00010003; 38 39 imm32 r0, 0x00201001; 40 R1.L = -1; 41 imm32 r2, 0x00202002; 42 imm32 r3, 0x00203003; 43 imm32 r4, 0x00204004; 44 imm32 r5, 0x00205005; 45 imm32 r6, 0x00206006; 46 imm32 r7, 0x00207007; 47 R7.L = R0.L >>> 5; 48 R0.L = R1.L >>> 5; 49 R1.L = R2.L >>> 5; 50 R2.L = R3.L >>> 5; 51 R3.L = R4.L >>> 5; 52 R4.L = R5.L >>> 5; 53 R5.L = R6.L >>> 5; 54 R6.L = R7.L >>> 5; 55 CHECKREG r0, 0x0020FFFF; 56 CHECKREG r1, 0x00010100; 57 CHECKREG r2, 0x00200180; 58 CHECKREG r3, 0x00200200; 59 CHECKREG r4, 0x00200280; 60 CHECKREG r5, 0x00200300; 61 CHECKREG r6, 0x00200004; 62 CHECKREG r7, 0x00200080; 63 64 65 imm32 r0, 0x03001001; 66 imm32 r1, 0x03001001; 67 R2.L = -15; 68 imm32 r3, 0x03003003; 69 imm32 r4, 0x03004004; 70 imm32 r5, 0x03005005; 71 imm32 r6, 0x03006006; 72 imm32 r7, 0x03007007; 73 R6.L = R0.L >>> 2; 74 R7.L = R1.L >>> 2; 75 R0.L = R2.L >>> 2; 76 R1.L = R3.L >>> 2; 77 R2.L = R4.L >>> 2; 78 R3.L = R5.L >>> 2; 79 R4.L = R6.L >>> 2; 80 R5.L = R7.L >>> 2; 81 CHECKREG r0, 0x0300FFFC; 82 CHECKREG r1, 0x03000C00; 83 CHECKREG r2, 0x00201001; 84 CHECKREG r3, 0x03001401; 85 CHECKREG r4, 0x03000100; 86 CHECKREG r5, 0x03000100; 87 CHECKREG r6, 0x03000400; 88 CHECKREG r7, 0x03000400; 89 90 imm32 r0, 0x40001001; 91 imm32 r1, 0x40001001; 92 imm32 r2, 0x40002002; 93 R3.L = -16; 94 imm32 r4, 0x40004004; 95 imm32 r5, 0x40005005; 96 imm32 r6, 0x40006006; 97 imm32 r7, 0x40007007; 98 R5.L = R0.L >>> 13; 99 R6.L = R1.L >>> 13; 100 R7.L = R2.L >>> 13; 101 R0.L = R3.L >>> 13; 102 R1.L = R4.L >>> 13; 103 R2.L = R5.L >>> 13; 104 R3.L = R6.L >>> 13; 105 R4.L = R7.L >>> 13; 106 CHECKREG r0, 0x4000FFFF; 107 CHECKREG r1, 0x40000002; 108 CHECKREG r2, 0x40000000; 109 CHECKREG r3, 0x03000000; 110 CHECKREG r4, 0x40000000; 111 CHECKREG r5, 0x40000000; 112 CHECKREG r6, 0x40000000; 113 CHECKREG r7, 0x40000001; 114 115 // d_lo = ashift (d_hi BY d_lo) 116 // RHx by RLx 117 imm32 r0, 0x50000000; 118 imm32 r1, 0x50010000; 119 imm32 r2, 0x50020000; 120 imm32 r3, 0x50030000; 121 imm32 r4, 0x50040000; 122 imm32 r5, 0x50050000; 123 imm32 r6, 0x50060000; 124 imm32 r7, 0x50070000; 125 R3.L = R0.H >>> 10; 126 R4.L = R1.H >>> 10; 127 R5.L = R2.H >>> 10; 128 R6.L = R3.H >>> 10; 129 R7.L = R4.H >>> 10; 130 R0.L = R5.H >>> 10; 131 R1.L = R6.H >>> 10; 132 R2.L = R7.H >>> 10; 133 CHECKREG r0, 0x50000014; 134 CHECKREG r1, 0x50010014; 135 CHECKREG r2, 0x50020014; 136 CHECKREG r3, 0x50030014; 137 CHECKREG r4, 0x50040014; 138 CHECKREG r5, 0x50050014; 139 CHECKREG r6, 0x50060014; 140 CHECKREG r7, 0x50070014; 141 142 imm32 r0, 0x10016000; 143 R1.L = -1; 144 imm32 r2, 0x20026000; 145 imm32 r3, 0x30036000; 146 imm32 r4, 0x40046000; 147 imm32 r5, 0x50056000; 148 imm32 r6, 0x60060000; 149 imm32 r7, 0x70076000; 150 R0.L = R0.H >>> 11; 151 R1.L = R1.H >>> 11; 152 R2.L = R2.H >>> 11; 153 R3.L = R3.H >>> 11; 154 R4.L = R4.H >>> 11; 155 R5.L = R5.H >>> 11; 156 R6.L = R6.H >>> 11; 157 R7.L = R7.H >>> 11; 158 CHECKREG r0, 0x10010002; 159 CHECKREG r1, 0x5001000A; 160 CHECKREG r2, 0x20020004; 161 CHECKREG r3, 0x30030006; 162 CHECKREG r4, 0x40040008; 163 CHECKREG r5, 0x5005000A; 164 CHECKREG r6, 0x6006000C; 165 CHECKREG r7, 0x7007000E; 166 167 168 imm32 r0, 0x10010700; 169 imm32 r1, 0x10010700; 170 R2.L = -15; 171 imm32 r3, 0x30030700; 172 imm32 r4, 0x40040000; 173 imm32 r5, 0x50050700; 174 imm32 r6, 0x60060000; 175 imm32 r7, 0x70070700; 176 R0.L = R0.H >>> 15; 177 R1.L = R1.H >>> 15; 178 R2.L = R2.H >>> 15; 179 R3.L = R3.H >>> 15; 180 R4.L = R4.H >>> 15; 181 R5.L = R5.H >>> 15; 182 R6.L = R6.H >>> 15; 183 R7.L = R7.H >>> 15; 184 CHECKREG r0, 0x10010000; 185 CHECKREG r1, 0x10010000; 186 CHECKREG r2, 0x20020000; 187 CHECKREG r3, 0x30030000; 188 CHECKREG r4, 0x40040000; 189 CHECKREG r5, 0x50050000; 190 CHECKREG r6, 0x60060000; 191 CHECKREG r7, 0x70070000; 192 193 imm32 r0, 0x18010001; 194 imm32 r1, 0x18010001; 195 imm32 r2, 0x28020002; 196 R3.L = -16; 197 imm32 r4, 0x48040004; 198 imm32 r5, 0x58050005; 199 imm32 r6, 0x68060006; 200 imm32 r7, 0x78070007; 201 R0.L = R0.H >>> 13; 202 R1.L = R1.H >>> 13; 203 R2.L = R2.H >>> 13; 204 R3.L = R3.H >>> 13; 205 R4.L = R4.H >>> 13; 206 R5.L = R5.H >>> 13; 207 R6.L = R6.H >>> 13; 208 R7.L = R7.H >>> 13; 209 CHECKREG r0, 0x18010000; 210 CHECKREG r1, 0x18010000; 211 CHECKREG r2, 0x28020001; 212 CHECKREG r3, 0x30030001; 213 CHECKREG r4, 0x48040002; 214 CHECKREG r5, 0x58050002; 215 CHECKREG r6, 0x68060003; 216 CHECKREG r7, 0x78070003; 217 218 // d_hi = ashft (d_lo BY d_lo) 219 // RLx by RLx 220 imm32 r0, 0x09000091; 221 imm32 r1, 0x09000091; 222 imm32 r2, 0x09000092; 223 imm32 r3, 0x09000093; 224 imm32 r4, 0x09000090; 225 imm32 r5, 0x09000095; 226 imm32 r6, 0x09000096; 227 imm32 r7, 0x09000097; 228 R0.H = R0.L >>> 14; 229 R1.H = R1.L >>> 14; 230 R2.H = R2.L >>> 14; 231 R3.H = R3.L >>> 14; 232 R4.H = R4.L >>> 14; 233 R5.H = R5.L >>> 14; 234 R6.H = R6.L >>> 14; 235 R7.H = R7.L >>> 14; 236 CHECKREG r0, 0x00000091; 237 CHECKREG r1, 0x00000091; 238 CHECKREG r2, 0x00000092; 239 CHECKREG r3, 0x00000093; 240 CHECKREG r4, 0x00000090; 241 CHECKREG r5, 0x00000095; 242 CHECKREG r6, 0x00000096; 243 CHECKREG r7, 0x00000097; 244 245 imm32 r0, 0xa0000001; 246 imm32 r1, 0xa0000001; 247 imm32 r2, 0xa0000002; 248 imm32 r3, 0xa0000003; 249 imm32 r4, 0xa0000004; 250 R5.L = -1; 251 imm32 r6, 0xa0000006; 252 imm32 r7, 0xa0000007; 253 R0.H = R0.L >>> 15; 254 R1.H = R1.L >>> 15; 255 R2.H = R2.L >>> 15; 256 R3.H = R3.L >>> 15; 257 R4.H = R4.L >>> 15; 258 R5.H = R5.L >>> 15; 259 R6.H = R6.L >>> 15; 260 R7.H = R7.L >>> 15; 261 CHECKREG r0, 0x00000001; 262 CHECKREG r1, 0x00000001; 263 CHECKREG r2, 0x00000002; 264 CHECKREG r3, 0x00000003; 265 CHECKREG r4, 0x00000004; 266 CHECKREG r5, 0xFFFFFFFF; 267 CHECKREG r6, 0x00000006; 268 CHECKREG r7, 0x00000007; 269 270 271 imm32 r0, 0xb0001001; 272 imm32 r1, 0xb0001001; 273 imm32 r1, 0xb0002002; 274 imm32 r3, 0xb0003003; 275 imm32 r4, 0xb0004004; 276 imm32 r5, 0xb0005005; 277 R6.L = -15; 278 imm32 r7, 0xb0007007; 279 R0.H = R0.L >>> 6; 280 R1.H = R1.L >>> 6; 281 R2.H = R2.L >>> 6; 282 R3.H = R3.L >>> 6; 283 R4.H = R4.L >>> 6; 284 R5.H = R5.L >>> 6; 285 R6.H = R6.L >>> 6; 286 R7.H = R7.L >>> 6; 287 CHECKREG r0, 0x00401001; 288 CHECKREG r1, 0x00802002; 289 CHECKREG r2, 0x00000002; 290 CHECKREG r3, 0x00C03003; 291 CHECKREG r4, 0x01004004; 292 CHECKREG r5, 0x01405005; 293 CHECKREG r6, 0xFFFFFFF1; 294 CHECKREG r7, 0x01C07007; 295 296 imm32 r0, 0x0c001c01; 297 imm32 r1, 0x0c002c01; 298 imm32 r2, 0x0c002c02; 299 imm32 r3, 0x0c003c03; 300 imm32 r4, 0x0c004c04; 301 imm32 r5, 0x0c005c05; 302 imm32 r6, 0x0c006c06; 303 R7.L = -16; 304 R0.H = R0.L >>> 7; 305 R1.H = R1.L >>> 7; 306 R2.H = R2.L >>> 7; 307 R3.H = R3.L >>> 7; 308 R4.H = R4.L >>> 7; 309 R5.H = R5.L >>> 7; 310 R6.H = R6.L >>> 7; 311 R7.H = R7.L >>> 7; 312 CHECKREG r0, 0x00381C01; 313 CHECKREG r1, 0x00582C01; 314 CHECKREG r2, 0x00582C02; 315 CHECKREG r3, 0x00783C03; 316 CHECKREG r4, 0x00984C04; 317 CHECKREG r5, 0x00B85C05; 318 CHECKREG r6, 0x00D86C06; 319 CHECKREG r7, 0xFFFFFFF0; 320 321 // d_lo = ashft (d_hi BY d_lo) 322 // RHx by RLx 323 imm32 r0, 0x0d01d000; 324 imm32 r1, 0x0d01d000; 325 imm32 r2, 0x0d02d000; 326 imm32 r3, 0x0d03d000; 327 R4.L = -1; 328 imm32 r5, 0x0d05d000; 329 imm32 r6, 0x0d06d000; 330 imm32 r7, 0x0d07d000; 331 R0.H = R0.H >>> 4; 332 R1.H = R1.H >>> 4; 333 R2.H = R2.H >>> 4; 334 R3.H = R3.H >>> 4; 335 R4.H = R4.H >>> 4; 336 R5.H = R5.H >>> 4; 337 R6.H = R6.H >>> 4; 338 R7.H = R6.H >>> 4; 339 CHECKREG r0, 0x00D0D000; 340 CHECKREG r1, 0x00D0D000; 341 CHECKREG r2, 0x00D0D000; 342 CHECKREG r3, 0x00D0D000; 343 CHECKREG r4, 0x0009FFFF; 344 CHECKREG r5, 0x00D0D000; 345 CHECKREG r6, 0x00D0D000; 346 CHECKREG r7, 0x000DD000; 347 348 imm32 r0, 0x1e010000; 349 imm32 r1, 0x1e010000; 350 imm32 r2, 0x2e020000; 351 imm32 r3, 0x3e030000; 352 imm32 r4, 0x4e040000; 353 R5.L = -1; 354 imm32 r6, 0x6e060000; 355 imm32 r7, 0x7e070000; 356 R7.H = R0.H >>> 15; 357 R6.H = R1.H >>> 15; 358 R0.H = R2.H >>> 15; 359 R1.H = R3.H >>> 15; 360 R2.H = R4.H >>> 15; 361 R3.H = R5.H >>> 15; 362 R4.H = R6.H >>> 15; 363 R5.H = R7.H >>> 15; 364 CHECKREG r0, 0x00000000; 365 CHECKREG r1, 0x00000000; 366 CHECKREG r2, 0x00000000; 367 CHECKREG r3, 0x00000000; 368 CHECKREG r4, 0x00000000; 369 CHECKREG r5, 0x0000FFFF; 370 CHECKREG r6, 0x00000000; 371 CHECKREG r7, 0x00000000; 372 373 imm32 r0, 0x1f010000; 374 imm32 r1, 0x1f010000; 375 imm32 r2, 0x2f020000; 376 imm32 r3, 0x3f030000; 377 imm32 r4, 0x4f040000; 378 imm32 r5, 0x5f050000; 379 R6.L = -15; 380 imm32 r7, 0x70070000; 381 R6.H = R0.H >>> 6; 382 R7.H = R1.H >>> 6; 383 R5.H = R2.H >>> 6; 384 R0.H = R3.H >>> 6; 385 R1.H = R4.H >>> 6; 386 R2.H = R5.H >>> 6; 387 R3.H = R6.H >>> 6; 388 R4.H = R7.H >>> 6; 389 CHECKREG r0, 0x00FC0000; 390 CHECKREG r1, 0x013C0000; 391 CHECKREG r2, 0x00020000; 392 CHECKREG r3, 0x00010000; 393 CHECKREG r4, 0x00010000; 394 CHECKREG r5, 0x00BC0000; 395 CHECKREG r6, 0x007CFFF1; 396 CHECKREG r7, 0x007C0000; 397 398 imm32 r0, 0x11010a00; 399 imm32 r1, 0x11010b00; 400 imm32 r2, 0x21020d00; 401 imm32 r2, 0x31030c00; 402 imm32 r4, 0x41040d00; 403 imm32 r5, 0x51050e00; 404 imm32 r6, 0x610600f0; 405 R7.L = -16; 406 R5.H = R0.H >>> 7; 407 R6.H = R1.H >>> 7; 408 R7.H = R2.H >>> 7; 409 R2.H = R3.H >>> 7; 410 R3.H = R4.H >>> 7; 411 R4.H = R5.H >>> 7; 412 R0.H = R6.H >>> 7; 413 R1.H = R7.H >>> 7; 414 CHECKREG r0, 0x00000A00; 415 CHECKREG r1, 0x00000B00; 416 CHECKREG r2, 0x00000C00; 417 CHECKREG r3, 0x00820000; 418 CHECKREG r4, 0x00000D00; 419 CHECKREG r5, 0x00220E00; 420 CHECKREG r6, 0x002200F0; 421 CHECKREG r7, 0x0062FFF0; 422 pass 423
Indexes created Tue Aug 11 00:25:38 UTC 2026