1 //Original:/proj/frio/dv/testcases/seq/se_excpt_dagprotviol/se_excpt_dagprotviol.dsp 2 // Description: EXCPT instruction combined with DAG Misaligned Access 3 # mach: bfin 4 # sim: --environment operating 5 6 #include "test.h" 7 .include "testutils.inc" 8 start 9 10 include(gen_int.inc) 11 include(selfcheck.inc) 12 include(std.inc) 13 include(mmrs.inc) 14 include(symtable.inc) 15 16 #ifndef STACKSIZE 17 #define STACKSIZE 0x100 // change for how much stack you need 18 #endif 19 #ifndef ITABLE 20 #define ITABLE 0xF0000000 21 #endif 22 23 GEN_INT_INIT(ITABLE) // set location for interrupt table 24 25 // 26 // Reset/Bootstrap Code 27 // (Here we should set the processor operating modes, initialize registers, 28 // etc.) 29 // 30 31 BOOT: 32 INIT_R_REGS(0); // initialize general purpose regs 33 34 INIT_P_REGS(0); // initialize the pointers 35 36 INIT_I_REGS(0); // initialize the dsp address regs 37 INIT_M_REGS(0); 38 INIT_L_REGS(0); 39 INIT_B_REGS(0); 40 41 CLI R1; // inhibit events during MMR writes 42 43 LD32_LABEL(sp, USTACK); // setup the user stack pointer 44 USP = SP; 45 46 LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer 47 FP = SP; // and frame pointer 48 49 LD32(p0, EVT0); // Setup Event Vectors and Handlers 50 51 P0 += 4; // EVT0 not used (Emulation) 52 53 P0 += 4; // EVT1 not used (Reset) 54 55 LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) 56 [ P0 ++ ] = R0; 57 58 LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) 59 [ P0 ++ ] = R0; 60 61 P0 += 4; // EVT4 not used (Global Interrupt Enable) 62 63 LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) 64 [ P0 ++ ] = R0; 65 66 LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) 67 [ P0 ++ ] = R0; 68 69 LD32_LABEL(r0, I7HANDLE); // IVG7 Handler 70 [ P0 ++ ] = R0; 71 72 LD32_LABEL(r0, I8HANDLE); // IVG8 Handler 73 [ P0 ++ ] = R0; 74 75 LD32_LABEL(r0, I9HANDLE); // IVG9 Handler 76 [ P0 ++ ] = R0; 77 78 LD32_LABEL(r0, I10HANDLE);// IVG10 Handler 79 [ P0 ++ ] = R0; 80 81 LD32_LABEL(r0, I11HANDLE);// IVG11 Handler 82 [ P0 ++ ] = R0; 83 84 LD32_LABEL(r0, I12HANDLE);// IVG12 Handler 85 [ P0 ++ ] = R0; 86 87 LD32_LABEL(r0, I13HANDLE);// IVG13 Handler 88 [ P0 ++ ] = R0; 89 90 LD32_LABEL(r0, I14HANDLE);// IVG14 Handler 91 [ P0 ++ ] = R0; 92 93 LD32_LABEL(r0, I15HANDLE);// IVG15 Handler 94 [ P0 ++ ] = R0; 95 96 LD32(p0, EVT_OVERRIDE); 97 R0 = 0; 98 [ P0 ++ ] = R0; 99 100 R1 = -1; // Change this to mask interrupts (*) 101 CSYNC; // wait for MMR writes to finish 102 STI R1; // sync and reenable events (implicit write to IMASK) 103 104 DUMMY: 105 106 R0 = 0 (Z); 107 108 LT0 = r0; // set loop counters to something deterministic 109 LB0 = r0; 110 LC0 = r0; 111 LT1 = r0; 112 LB1 = r0; 113 LC1 = r0; 114 115 ASTAT = r0; // reset other internal regs 116 SYSCFG = r0; 117 RETS = r0; // prevent X's breaking LINK instruction 118 119 RETI = r0; // prevent Xs later on 120 RETX = r0; 121 RETN = r0; 122 RETE = r0; 123 124 125 // The following code sets up the test for running in USER mode 126 127 LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a 128 // ReturnFromInterrupt (RTI) 129 RETI = r0; // We need to load the return address 130 131 // Comment the following line for a USER Mode test 132 133 // JUMP STARTSUP; // jump to code start for SUPERVISOR mode 134 135 RTI; 136 137 STARTSUP: 138 LD32_LABEL(p1, BEGIN); 139 140 LD32(p0, EVT15); 141 142 CLI R1; // inhibit events during write to MMR 143 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start 144 CSYNC; // wait for it 145 STI R1; // reenable events with proper imask 146 147 RAISE 15; // after we RTI, INT 15 should be taken 148 149 RTI; 150 151 // 152 // The Main Program 153 // 154 155 STARTUSER: 156 157 LD32_LABEL(sp, USTACK); // setup the user stack pointer 158 FP = SP; 159 LINK 0; // change for how much stack frame space you need. 160 161 JUMP BEGIN; 162 163 //********************************************************************* 164 165 BEGIN: 166 167 // COMMENT the following line for USER MODE tests 168 // [--sp] = RETI; // enable interrupts in supervisor mode 169 170 R0 = 0; 171 R1 = -1; 172 LD32_LABEL(p1, USTACK); 173 P1 += 1; // misalign it 174 175 EXCPT 2; // the RAISE should not prevent the EXCPT from being taken 176 R2 = [ P1 ]; 177 178 CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); 179 180 CHECKREG(r5, 2); // check the flag 181 182 END: 183 dbg_pass; // End the test 184 185 //********************************************************************* 186 187 // 188 // Handlers for Events 189 // 190 191 NHANDLE: // NMI Handler 2 192 RTN; 193 194 XHANDLE: // Exception Handler 3 195 196 [ -- SP ] = ASTAT; // save what we damage 197 [ -- SP ] = ( R7:6 ); 198 R7 = SEQSTAT; 199 R7 <<= 26; 200 R7 >>= 26; // only want EXCAUSE 201 R6 = 0x02; // EXCAUSE 0x02 means EXCPT 2 instruction 202 CC = r7 == r6; 203 IF CC JUMP EXCPT2; 204 205 R6 = 0x24; // EXCAUSE 0x24 means DAG misalign 206 CC = r7 == r6; 207 IF CC JUMP DGPROTVIOL; 208 209 JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop 210 211 EXCPT2: 212 R5 = 1; // Set a Flag 213 JUMP.S OUT; 214 215 DGPROTVIOL: 216 R7 = RETX; // Fix up return address 217 218 R7 += 2; // skip offending 16 bit instruction 219 220 RETX = r7; // and put back in RETX 221 222 R5 <<= 1; // Alter Global Flag 223 224 OUT: 225 ( R7:6 ) = [ SP ++ ]; 226 ASTAT = [sp++]; 227 RTX; 228 229 HWHANDLE: // HW Error Handler 5 230 RTI; 231 232 THANDLE: // Timer Handler 6 233 RTI; 234 235 I7HANDLE: // IVG 7 Handler 236 RTI; 237 238 I8HANDLE: // IVG 8 Handler 239 RTI; 240 241 I9HANDLE: // IVG 9 Handler 242 RTI; 243 244 I10HANDLE: // IVG 10 Handler 245 RTI; 246 247 I11HANDLE: // IVG 11 Handler 248 RTI; 249 250 I12HANDLE: // IVG 12 Handler 251 RTI; 252 253 I13HANDLE: // IVG 13 Handler 254 RTI; 255 256 I14HANDLE: // IVG 14 Handler 257 RTI; 258 259 I15HANDLE: // IVG 15 Handler 260 RTI; 261 262 263 // padding for the icache 264 265 EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; 266 267 // 268 // Data Segment 269 // 270 271 .data 272 DATA: 273 .space (0x10); 274 275 // Stack Segments (Both Kernel and User) 276 277 .space (STACKSIZE); 278 KSTACK: 279 280 .space (STACKSIZE); 281 USTACK: 282
Indexes created Sat Feb 28 05:31:39 UTC 2026