1 # frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond 2 # mach: all 3 4 .include "../testutils.inc" 5 6 start 7 8 .global cmqaddhus 9 cmqaddhus: 10 set_spr_immed 0x1b1b,cccr 11 12 set_fr_iimmed 0x0000,0x0000,fr10 13 set_fr_iimmed 0xdead,0x0000,fr11 14 set_fr_iimmed 0x0000,0x0000,fr12 15 set_fr_iimmed 0x0000,0xbeef,fr13 16 cmqaddhus fr10,fr12,fr14,cc0,1 17 test_fr_limmed 0x0000,0x0000,fr14 18 test_fr_limmed 0xdead,0xbeef,fr15 19 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 20 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 21 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 22 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 23 24 set_fr_iimmed 0x0000,0xdead,fr10 25 set_fr_iimmed 0x1234,0x5678,fr11 26 set_fr_iimmed 0xbeef,0x0000,fr12 27 set_fr_iimmed 0x1111,0x1111,fr13 28 cmqaddhus fr10,fr12,fr14,cc0,1 29 test_fr_limmed 0xbeef,0xdead,fr14 30 test_fr_limmed 0x2345,0x6789,fr15 31 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 32 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 33 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 34 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 35 36 set_fr_iimmed 0x7ffe,0x7ffe,fr10 37 set_fr_iimmed 0xfffe,0xfffe,fr11 38 set_fr_iimmed 0x0002,0x0001,fr12 39 set_fr_iimmed 0x0001,0x0002,fr13 40 cmqaddhus fr10,fr12,fr14,cc4,1 41 test_fr_limmed 0x8000,0x7fff,fr14 42 test_fr_limmed 0xffff,0xffff,fr15 43 test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set 44 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 45 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 46 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 47 48 set_spr_immed 0,msr0 49 set_fr_iimmed 0x0002,0x0001,fr10 50 set_fr_iimmed 0x0001,0x0001,fr11 51 set_fr_iimmed 0xfffe,0xfffe,fr12 52 set_fr_iimmed 0x8000,0x8000,fr13 53 cmqaddhus.p fr10,fr10,fr14,cc4,1 54 cmqaddhus fr12,fr12,fr16,cc4,1 55 test_fr_limmed 0x0004,0x0002,fr14 56 test_fr_limmed 0x0002,0x0002,fr15 57 test_fr_limmed 0xffff,0xffff,fr16 58 test_fr_limmed 0xffff,0xffff,fr17 59 test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set 60 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 61 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 62 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 63 64 set_spr_immed 0,msr0 65 set_fr_iimmed 0x0000,0x0000,fr10 66 set_fr_iimmed 0xdead,0x0000,fr11 67 set_fr_iimmed 0x0000,0x0000,fr12 68 set_fr_iimmed 0x0000,0xbeef,fr13 69 cmqaddhus fr10,fr12,fr14,cc1,0 70 test_fr_limmed 0x0000,0x0000,fr14 71 test_fr_limmed 0xdead,0xbeef,fr15 72 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 73 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 74 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 75 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 76 77 set_fr_iimmed 0x0000,0xdead,fr10 78 set_fr_iimmed 0x1234,0x5678,fr11 79 set_fr_iimmed 0xbeef,0x0000,fr12 80 set_fr_iimmed 0x1111,0x1111,fr13 81 cmqaddhus fr10,fr12,fr14,cc1,0 82 test_fr_limmed 0xbeef,0xdead,fr14 83 test_fr_limmed 0x2345,0x6789,fr15 84 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 85 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 86 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 87 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 88 89 set_fr_iimmed 0x7ffe,0x7ffe,fr10 90 set_fr_iimmed 0xfffe,0xfffe,fr11 91 set_fr_iimmed 0x0002,0x0001,fr12 92 set_fr_iimmed 0x0001,0x0002,fr13 93 cmqaddhus fr10,fr12,fr14,cc5,0 94 test_fr_limmed 0x8000,0x7fff,fr14 95 test_fr_limmed 0xffff,0xffff,fr15 96 test_spr_bits 0x3c,2,1,msr0 ; msr0.sie is set 97 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 98 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 99 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 100 101 set_spr_immed 0,msr0 102 set_fr_iimmed 0x0002,0x0001,fr10 103 set_fr_iimmed 0x0001,0x0001,fr11 104 set_fr_iimmed 0xfffe,0xfffe,fr12 105 set_fr_iimmed 0x8000,0x8000,fr13 106 cmqaddhus.p fr10,fr10,fr14,cc5,0 107 cmqaddhus fr12,fr12,fr16,cc5,0 108 test_fr_limmed 0x0004,0x0002,fr14 109 test_fr_limmed 0x0002,0x0002,fr15 110 test_fr_limmed 0xffff,0xffff,fr16 111 test_fr_limmed 0xffff,0xffff,fr17 112 test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set 113 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 114 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 115 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 116 117 set_fr_iimmed 0x1111,0x1111,fr14 118 set_fr_iimmed 0x2222,0x2222,fr15 119 set_spr_immed 0,msr0 120 set_fr_iimmed 0x0000,0x0000,fr10 121 set_fr_iimmed 0xdead,0x0000,fr11 122 set_fr_iimmed 0x0000,0x0000,fr12 123 set_fr_iimmed 0x0000,0xbeef,fr13 124 cmqaddhus fr10,fr12,fr14,cc0,0 125 test_fr_limmed 0x1111,0x1111,fr14 126 test_fr_limmed 0x2222,0x2222,fr15 127 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 128 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 129 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 130 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 131 132 set_fr_iimmed 0x0000,0xdead,fr10 133 set_fr_iimmed 0x1234,0x5678,fr11 134 set_fr_iimmed 0xbeef,0x0000,fr12 135 set_fr_iimmed 0x1111,0x1111,fr13 136 cmqaddhus fr10,fr12,fr14,cc0,0 137 test_fr_limmed 0x1111,0x1111,fr14 138 test_fr_limmed 0x2222,0x2222,fr15 139 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 140 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 141 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 142 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 143 144 set_fr_iimmed 0x7ffe,0x7ffe,fr10 145 set_fr_iimmed 0xfffe,0xfffe,fr11 146 set_fr_iimmed 0x0002,0x0001,fr12 147 set_fr_iimmed 0x0001,0x0002,fr13 148 cmqaddhus fr10,fr12,fr14,cc4,0 149 test_fr_limmed 0x1111,0x1111,fr14 150 test_fr_limmed 0x2222,0x2222,fr15 151 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 152 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 153 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 154 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 155 156 set_fr_iimmed 0x3333,0x3333,fr16 157 set_fr_iimmed 0x4444,0x4444,fr17 158 set_spr_immed 0,msr0 159 set_fr_iimmed 0x0002,0x0001,fr10 160 set_fr_iimmed 0x0001,0x0001,fr11 161 set_fr_iimmed 0xfffe,0xfffe,fr12 162 set_fr_iimmed 0x8000,0x8000,fr13 163 cmqaddhus.p fr10,fr10,fr14,cc4,0 164 cmqaddhus fr12,fr12,fr16,cc4,0 165 test_fr_limmed 0x1111,0x1111,fr14 166 test_fr_limmed 0x2222,0x2222,fr15 167 test_fr_limmed 0x3333,0x3333,fr16 168 test_fr_limmed 0x4444,0x4444,fr17 169 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 170 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 171 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 172 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 173 174 set_fr_iimmed 0x1111,0x1111,fr14 175 set_fr_iimmed 0x2222,0x2222,fr15 176 set_spr_immed 0,msr0 177 set_fr_iimmed 0x0000,0x0000,fr10 178 set_fr_iimmed 0xdead,0x0000,fr11 179 set_fr_iimmed 0x0000,0x0000,fr12 180 set_fr_iimmed 0x0000,0xbeef,fr13 181 cmqaddhus fr10,fr12,fr14,cc1,1 182 test_fr_limmed 0x1111,0x1111,fr14 183 test_fr_limmed 0x2222,0x2222,fr15 184 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 185 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 186 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 187 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 188 189 set_fr_iimmed 0x0000,0xdead,fr10 190 set_fr_iimmed 0x1234,0x5678,fr11 191 set_fr_iimmed 0xbeef,0x0000,fr12 192 set_fr_iimmed 0x1111,0x1111,fr13 193 cmqaddhus fr10,fr12,fr14,cc1,1 194 test_fr_limmed 0x1111,0x1111,fr14 195 test_fr_limmed 0x2222,0x2222,fr15 196 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 197 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 198 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 199 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 200 201 set_fr_iimmed 0x7ffe,0x7ffe,fr10 202 set_fr_iimmed 0xfffe,0xfffe,fr11 203 set_fr_iimmed 0x0002,0x0001,fr12 204 set_fr_iimmed 0x0001,0x0002,fr13 205 cmqaddhus fr10,fr12,fr14,cc5,1 206 test_fr_limmed 0x1111,0x1111,fr14 207 test_fr_limmed 0x2222,0x2222,fr15 208 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 209 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 210 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 211 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 212 213 set_fr_iimmed 0x3333,0x3333,fr16 214 set_fr_iimmed 0x4444,0x4444,fr17 215 set_spr_immed 0,msr0 216 set_fr_iimmed 0x0002,0x0001,fr10 217 set_fr_iimmed 0x0001,0x0001,fr11 218 set_fr_iimmed 0xfffe,0xfffe,fr12 219 set_fr_iimmed 0x8000,0x8000,fr13 220 cmqaddhus.p fr10,fr10,fr14,cc5,1 221 cmqaddhus fr12,fr12,fr16,cc5,1 222 test_fr_limmed 0x1111,0x1111,fr14 223 test_fr_limmed 0x2222,0x2222,fr15 224 test_fr_limmed 0x3333,0x3333,fr16 225 test_fr_limmed 0x4444,0x4444,fr17 226 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 227 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 228 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 229 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 230 231 set_fr_iimmed 0x1111,0x1111,fr14 232 set_fr_iimmed 0x2222,0x2222,fr15 233 set_spr_immed 0,msr0 234 set_fr_iimmed 0x0000,0x0000,fr10 235 set_fr_iimmed 0xdead,0x0000,fr11 236 set_fr_iimmed 0x0000,0x0000,fr12 237 set_fr_iimmed 0x0000,0xbeef,fr13 238 cmqaddhus fr10,fr12,fr14,cc2,1 239 test_fr_limmed 0x1111,0x1111,fr14 240 test_fr_limmed 0x2222,0x2222,fr15 241 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 242 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 243 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 244 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 245 246 set_fr_iimmed 0x0000,0xdead,fr10 247 set_fr_iimmed 0x1234,0x5678,fr11 248 set_fr_iimmed 0xbeef,0x0000,fr12 249 set_fr_iimmed 0x1111,0x1111,fr13 250 cmqaddhus fr10,fr12,fr14,cc2,0 251 test_fr_limmed 0x1111,0x1111,fr14 252 test_fr_limmed 0x2222,0x2222,fr15 253 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 254 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 255 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 256 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 257 258 set_fr_iimmed 0x7ffe,0x7ffe,fr10 259 set_fr_iimmed 0xfffe,0xfffe,fr11 260 set_fr_iimmed 0x0002,0x0001,fr12 261 set_fr_iimmed 0x0001,0x0002,fr13 262 cmqaddhus fr10,fr12,fr14,cc6,1 263 test_fr_limmed 0x1111,0x1111,fr14 264 test_fr_limmed 0x2222,0x2222,fr15 265 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 266 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 267 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 268 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 269 270 set_fr_iimmed 0x3333,0x3333,fr16 271 set_fr_iimmed 0x4444,0x4444,fr17 272 set_spr_immed 0,msr0 273 set_fr_iimmed 0x0002,0x0001,fr10 274 set_fr_iimmed 0x0001,0x0001,fr11 275 set_fr_iimmed 0xfffe,0xfffe,fr12 276 set_fr_iimmed 0x8000,0x8000,fr13 277 cmqaddhus.p fr10,fr10,fr14,cc6,0 278 cmqaddhus fr12,fr12,fr16,cc6,1 279 test_fr_limmed 0x1111,0x1111,fr14 280 test_fr_limmed 0x2222,0x2222,fr15 281 test_fr_limmed 0x3333,0x3333,fr16 282 test_fr_limmed 0x4444,0x4444,fr17 283 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 284 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 285 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 286 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 287 288 set_fr_iimmed 0x1111,0x1111,fr14 289 set_fr_iimmed 0x2222,0x2222,fr15 290 set_spr_immed 0,msr0 291 set_fr_iimmed 0x0000,0x0000,fr10 292 set_fr_iimmed 0xdead,0x0000,fr11 293 set_fr_iimmed 0x0000,0x0000,fr12 294 set_fr_iimmed 0x0000,0xbeef,fr13 295 cmqaddhus fr10,fr12,fr14,cc3,1 296 test_fr_limmed 0x1111,0x1111,fr14 297 test_fr_limmed 0x2222,0x2222,fr15 298 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 299 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 300 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 301 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 302 303 set_fr_iimmed 0x0000,0xdead,fr10 304 set_fr_iimmed 0x1234,0x5678,fr11 305 set_fr_iimmed 0xbeef,0x0000,fr12 306 set_fr_iimmed 0x1111,0x1111,fr13 307 cmqaddhus fr10,fr12,fr14,cc3,0 308 test_fr_limmed 0x1111,0x1111,fr14 309 test_fr_limmed 0x2222,0x2222,fr15 310 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 311 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 312 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 313 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 314 315 set_fr_iimmed 0x7ffe,0x7ffe,fr10 316 set_fr_iimmed 0xfffe,0xfffe,fr11 317 set_fr_iimmed 0x0002,0x0001,fr12 318 set_fr_iimmed 0x0001,0x0002,fr13 319 cmqaddhus fr10,fr12,fr14,cc7,1 320 test_fr_limmed 0x1111,0x1111,fr14 321 test_fr_limmed 0x2222,0x2222,fr15 322 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 323 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 324 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 325 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 326 327 set_fr_iimmed 0x3333,0x3333,fr16 328 set_fr_iimmed 0x4444,0x4444,fr17 329 set_spr_immed 0,msr0 330 set_fr_iimmed 0x0002,0x0001,fr10 331 set_fr_iimmed 0x0001,0x0001,fr11 332 set_fr_iimmed 0xfffe,0xfffe,fr12 333 set_fr_iimmed 0x8000,0x8000,fr13 334 cmqaddhus.p fr10,fr10,fr14,cc7,0 335 cmqaddhus fr12,fr12,fr16,cc7,1 336 test_fr_limmed 0x1111,0x1111,fr14 337 test_fr_limmed 0x2222,0x2222,fr15 338 test_fr_limmed 0x3333,0x3333,fr16 339 test_fr_limmed 0x4444,0x4444,fr17 340 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 341 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 342 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 343 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt always set 344 345 pass 346
Indexes created Sat Oct 03 00:25:10 UTC 2026