1 # Hitachi H8 testcase 'xor.b' 2 # mach(): all 3 # as(h8300): --defsym sim_cpu=0 4 # as(h8300h): --defsym sim_cpu=1 5 # as(h8300s): --defsym sim_cpu=2 6 # as(h8sx): --defsym sim_cpu=3 7 # ld(h8300h): -m h8300helf 8 # ld(h8300s): -m h8300self 9 # ld(h8sx): -m h8300sxelf 10 11 .include "testutils.inc" 12 13 # Instructions tested: 14 # xor.b #xx:8, rd ; d rd xxxxxxxx 15 # xor.b #xx:8, @erd ; 7 d rd ???? d ???? xxxxxxxx 16 # xor.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? d ???? xxxxxxxx 17 # xor.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? d ???? xxxxxxxx 18 # xor.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? d ???? xxxxxxxx 19 # xor.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? d ???? xxxxxxxx 20 # xor.b rs, rd ; 1 5 rs rd 21 # xor.b reg8, @erd ; 7 d rd ???? 1 5 rs ???? 22 # xor.b reg8, @erd+ ; 0 1 7 9 8 rd 5 rs 23 # xor.b reg8, @erd- ; 0 1 7 9 a rd 5 rs 24 # xor.b reg8, @+erd ; 0 1 7 9 9 rd 5 rs 25 # xor.b reg8, @-erd ; 0 1 7 9 b rd 5 rs 26 # 27 # xorc #xx:8, ccr ; 28 # xorc #xx:8, exr ; 29 30 # Coming soon: 31 # ... 32 33 .data 34 pre_byte: .byte 0 35 byte_dest: .byte 0xa5 36 post_byte: .byte 0 37 38 start 39 40 xor_b_imm8_reg: 41 set_grs_a5a5 ; Fill all general regs with a fixed pattern 42 ;; fixme set ccr 43 44 ;; xor.b #xx:8,Rd 45 xor.b #0xff, r0l ; Immediate 8-bit operand 46 47 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 48 test_h_gr16 0xa55a r0 ; xor result: a5 ^ ff 49 .if (sim_cpu) ; non-zero means h8300h, s, or sx 50 test_h_gr32 0xa5a5a55a er0 ; xor result: a5 ^ ff 51 .endif 52 test_gr_a5a5 1 ; Make sure other general regs not disturbed 53 test_gr_a5a5 2 54 test_gr_a5a5 3 55 test_gr_a5a5 4 56 test_gr_a5a5 5 57 test_gr_a5a5 6 58 test_gr_a5a5 7 59 60 .if (sim_cpu == h8sx) 61 xor_b_imm8_rdind: 62 set_grs_a5a5 ; Fill all general regs with a fixed pattern 63 set_ccr_zero 64 65 ;; xor.b #xx:8,@eRd 66 mov #byte_dest, er0 67 xor.b #0xff:8, @er0 ; Immediate 8-bit src, reg indirect dst 68 ;;; .word 0x7d00 69 ;;; .word 0xd0ff 70 71 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 72 test_ovf_clear 73 test_zero_clear 74 test_neg_clear 75 76 test_h_gr32 byte_dest, er0 ; er0 still contains address 77 test_gr_a5a5 1 ; Make sure other general regs not disturbed 78 test_gr_a5a5 2 79 test_gr_a5a5 3 80 test_gr_a5a5 4 81 test_gr_a5a5 5 82 test_gr_a5a5 6 83 test_gr_a5a5 7 84 85 ;; Now check the result of the xor to memory. 86 sub.b r0l, r0l 87 mov.b @byte_dest, r0l 88 cmp.b #0x5a, r0l 89 beq .L1 90 fail 91 .L1: 92 93 xor_b_imm8_postinc: 94 set_grs_a5a5 ; Fill all general regs with a fixed pattern 95 set_ccr_zero 96 97 ;; xor.b #xx:8,@eRd+ 98 mov #byte_dest, er0 99 xor.b #0xff:8, @er0+ ; Immediate 8-bit src, reg indirect dst 100 ;;; .word 0x0174 101 ;;; .word 0x6c08 102 ;;; .word 0xd0ff 103 104 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 105 test_ovf_clear 106 test_zero_clear 107 test_neg_set 108 109 test_h_gr32 post_byte, er0 ; er0 contains address plus one 110 test_gr_a5a5 1 ; Make sure other general regs not disturbed 111 test_gr_a5a5 2 112 test_gr_a5a5 3 113 test_gr_a5a5 4 114 test_gr_a5a5 5 115 test_gr_a5a5 6 116 test_gr_a5a5 7 117 118 ;; Now check the result of the xor to memory. 119 sub.b r0l, r0l 120 mov.b @byte_dest, r0l 121 cmp.b #0xa5, r0l 122 beq .L2 123 fail 124 .L2: 125 126 xor_b_imm8_rdpostdec: 127 set_grs_a5a5 ; Fill all general regs with a fixed pattern 128 set_ccr_zero 129 130 ;; xor.b #xx:8,@eRd- 131 mov #byte_dest, er0 132 xor.b #0xff:8, @er0- ; Immediate 8-bit src, reg indirect dst 133 ;;; .word 0x0176 134 ;;; .word 0x6c08 135 ;;; .word 0xd0ff 136 137 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 138 test_ovf_clear 139 test_zero_clear 140 test_neg_clear 141 142 test_h_gr32 pre_byte, er0 ; er0 contains address minus one 143 test_gr_a5a5 1 ; Make sure other general regs not disturbed 144 test_gr_a5a5 2 145 test_gr_a5a5 3 146 test_gr_a5a5 4 147 test_gr_a5a5 5 148 test_gr_a5a5 6 149 test_gr_a5a5 7 150 151 ;; Now check the result of the xor to memory. 152 sub.b r0l, r0l 153 mov.b @byte_dest, r0l 154 cmp.b #0x5a, r0l 155 beq .L3 156 fail 157 .L3: 158 .endif 159 160 xor_b_reg8_reg8: 161 set_grs_a5a5 ; Fill all general regs with a fixed pattern 162 ;; fixme set ccr 163 164 ;; xor.b Rs,Rd 165 mov.b #0xff, r0h 166 xor.b r0h, r0l ; Register operand 167 168 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0 169 test_h_gr16 0xff5a r0 ; xor result: a5 ^ ff 170 .if (sim_cpu) ; non-zero means h8300h, s, or sx 171 test_h_gr32 0xa5a5ff5a er0 ; xor result: a5 ^ ff 172 .endif 173 test_gr_a5a5 1 ; Make sure other general regs not disturbed 174 test_gr_a5a5 2 175 test_gr_a5a5 3 176 test_gr_a5a5 4 177 test_gr_a5a5 5 178 test_gr_a5a5 6 179 test_gr_a5a5 7 180 181 .if (sim_cpu == h8sx) 182 xor_b_reg8_rdind: 183 set_grs_a5a5 ; Fill all general regs with a fixed pattern 184 set_ccr_zero 185 186 ;; xor.b rs8,@eRd ; xor reg8 to register indirect 187 mov #byte_dest, er0 188 mov #0xff, r1l 189 xor.b r1l, @er0 ; reg8 src, reg indirect dest 190 ;;; .word 0x7d00 191 ;;; .word 0x1590 192 193 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 194 test_ovf_clear 195 test_zero_clear 196 test_neg_set 197 198 test_h_gr32 byte_dest er0 ; er0 still contains address 199 test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load 200 201 test_gr_a5a5 2 ; Make sure other general regs not disturbed 202 test_gr_a5a5 3 203 test_gr_a5a5 4 204 test_gr_a5a5 5 205 test_gr_a5a5 6 206 test_gr_a5a5 7 207 208 ;; Now check the result of the or to memory. 209 sub.b r0l, r0l 210 mov.b @byte_dest, r0l 211 cmp.b #0xa5, r0l 212 beq .L4 213 fail 214 .L4: 215 216 xor_b_reg8_rdpostinc: 217 set_grs_a5a5 ; Fill all general regs with a fixed pattern 218 set_ccr_zero 219 220 ;; xor.b rs8,@eRd+ ; xor reg8 to register post-increment 221 mov #byte_dest, er0 222 mov #0xff, r1l 223 xor.b r1l, @er0+ ; reg8 src, reg post-increment dest 224 ;;; .word 0x0179 225 ;;; .word 0x8059 226 227 test_carry_clear ; H=0 N=0 Z=0 V=0 C=0 228 test_ovf_clear 229 test_zero_clear 230 test_neg_clear 231 232 test_h_gr32 post_byte er0 ; er0 contains address plus one 233 test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load 234 235 test_gr_a5a5 2 ; Make sure other general regs not disturbed 236 test_gr_a5a5 3 237 test_gr_a5a5 4 238 test_gr_a5a5 5 239 test_gr_a5a5 6 240 test_gr_a5a5 7 241 242 ;; Now check the result of the or to memory. 243 sub.b r0l, r0l 244 mov.b @byte_dest, r0l 245 cmp.b #0x5a, r0l 246 beq .L5 247 fail 248 .L5: 249 ;; special case same register 250 mov.l #byte_dest, er0 251 mov.b r0l, r1l 252 mov.b @er0, r1h 253 xor.b r0l, @er0+ 254 inc.b r1l 255 xor.b r1h, r1l 256 mov.b @byte_dest, r0l 257 cmp.b r1l, r0l 258 beq .L25 259 fail 260 .L25: 261 mov.b r1h, @byte_dest 262 263 xor_b_reg8_rdpostdec: 264 set_grs_a5a5 ; Fill all general regs with a fixed pattern 265 set_ccr_zero 266 267 ;; xor.b rs8,@eRd- ; xor reg8 to register post-decrement 268 mov #byte_dest, er0 269 mov #0xff, r1l 270 xor.b r1l, @er0- ; reg8 src, reg indirect dest 271 ;;; .word 0x0179 272 ;;; .word 0xa059 273 274 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0 275 test_ovf_clear 276 test_zero_clear 277 test_neg_set 278 279 test_h_gr32 pre_byte er0 ; er0 contains address minus one 280 test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load 281 282 test_gr_a5a5 2 ; Make sure other general regs not disturbed 283 test_gr_a5a5 3 284 test_gr_a5a5 4 285 test_gr_a5a5 5 286 test_gr_a5a5 6 287 test_gr_a5a5 7 288 289 ;; Now check the result of the or to memory. 290 sub.b r0l, r0l 291 mov.b @byte_dest, r0l 292 cmp.b #0xa5, r0l 293 beq .L6 294 fail 295 .L6: 296 ;; special case same register 297 mov.l #byte_dest, er0 298 mov.b r0l, r1l 299 mov.b @er0, r1h 300 xor.b r0l, @er0- 301 dec.b r1l 302 xor.b r1h, r1l 303 mov.b @byte_dest, r0l 304 cmp.b r1l, r0l 305 beq .L26 306 fail 307 .L26: 308 309 .endif ; h8sx 310 311 xorc_imm8_ccr: 312 set_grs_a5a5 ; Fill all general regs with a fixed pattern 313 set_ccr_zero 314 315 ;; xorc #xx:8,ccr 316 317 test_neg_clear 318 xorc #0x8, ccr ; Immediate 8-bit operand (neg flag) 319 test_neg_set 320 xorc #0x8, ccr 321 test_neg_clear 322 323 test_zero_clear 324 xorc #0x4, ccr ; Immediate 8-bit operand (zero flag) 325 test_zero_set 326 xorc #0x4, ccr 327 test_zero_clear 328 329 test_ovf_clear 330 xorc #0x2, ccr ; Immediate 8-bit operand (overflow flag) 331 test_ovf_set 332 xorc #0x2, ccr 333 test_ovf_clear 334 335 test_carry_clear 336 xorc #0x1, ccr ; Immediate 8-bit operand (carry flag) 337 test_carry_set 338 xorc #0x1, ccr 339 test_carry_clear 340 341 test_gr_a5a5 0 ; Make sure other general regs not disturbed 342 test_gr_a5a5 1 343 test_gr_a5a5 2 344 test_gr_a5a5 3 345 test_gr_a5a5 4 346 test_gr_a5a5 5 347 test_gr_a5a5 6 348 test_gr_a5a5 7 349 350 .if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr 351 xorc_imm8_exr: 352 set_grs_a5a5 ; Fill all general regs with a fixed pattern 353 ldc #0, exr 354 stc exr, r0l 355 test_h_gr8 0, r0l 356 357 set_ccr_zero 358 ;; xorc #xx:8,exr 359 360 xorc #0x80, exr 361 test_cc_clear 362 stc exr, r0l 363 test_h_gr8 0x80, r0l 364 xorc #0x80, exr 365 stc exr, r0l 366 test_h_gr8 0, r0l 367 368 xorc #0x4, exr 369 stc exr, r0l 370 test_h_gr8 4, r0l 371 xorc #0x4, exr 372 stc exr, r0l 373 test_h_gr8 0, r0l 374 375 xorc #0x2, exr ; Immediate 8-bit operand (overflow flag) 376 stc exr, r0l 377 test_h_gr8 2, r0l 378 xorc #0x2, exr 379 stc exr, r0l 380 test_h_gr8 0, r0l 381 382 xorc #0x1, exr ; Immediate 8-bit operand (carry flag) 383 stc exr, r0l 384 test_h_gr8 1, r0l 385 xorc #0x1, exr 386 stc exr, r0l 387 test_h_gr8 0, r0l 388 389 test_h_gr32 0xa5a5a500 er0 390 test_gr_a5a5 1 ; Make sure other general regs not disturbed 391 test_gr_a5a5 2 392 test_gr_a5a5 3 393 test_gr_a5a5 4 394 test_gr_a5a5 5 395 test_gr_a5a5 6 396 test_gr_a5a5 7 397 .endif ; not h8300 or h8300h 398 399 pass 400 401 exit 0 402
Indexes created Mon Mar 02 05:31:46 UTC 2026