1 1.1 mrg Copyright 1996, 2001 Free Software Foundation, Inc. 2 1.1 mrg 3 1.1 mrg This file is part of the GNU MP Library. 4 1.1 mrg 5 1.1 mrg The GNU MP Library is free software; you can redistribute it and/or modify 6 1.1.1.2 mrg it under the terms of either: 7 1.1.1.2 mrg 8 1.1.1.2 mrg * the GNU Lesser General Public License as published by the Free 9 1.1.1.2 mrg Software Foundation; either version 3 of the License, or (at your 10 1.1.1.2 mrg option) any later version. 11 1.1.1.2 mrg 12 1.1.1.2 mrg or 13 1.1.1.2 mrg 14 1.1.1.2 mrg * the GNU General Public License as published by the Free Software 15 1.1.1.2 mrg Foundation; either version 2 of the License, or (at your option) any 16 1.1.1.2 mrg later version. 17 1.1.1.2 mrg 18 1.1.1.2 mrg or both in parallel, as here. 19 1.1 mrg 20 1.1 mrg The GNU MP Library is distributed in the hope that it will be useful, but 21 1.1 mrg WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 22 1.1.1.2 mrg or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 23 1.1.1.2 mrg for more details. 24 1.1 mrg 25 1.1.1.2 mrg You should have received copies of the GNU General Public License and the 26 1.1.1.2 mrg GNU Lesser General Public License along with the GNU MP Library. If not, 27 1.1.1.2 mrg see https://www.gnu.org/licenses/. 28 1.1 mrg 29 1.1 mrg 30 1.1 mrg 31 1.1 mrg 32 1.1 mrg 33 1.1 mrg This directory contains mpn functions for various SPARC chips. Code that 34 1.1 mrg runs only on version 8 SPARC implementations, is in the v8 subdirectory. 35 1.1 mrg 36 1.1 mrg RELEVANT OPTIMIZATION ISSUES 37 1.1 mrg 38 1.1 mrg Load and Store timing 39 1.1 mrg 40 1.1 mrg On most early SPARC implementations, the ST instructions takes multiple 41 1.1 mrg cycles, while a STD takes just a single cycle more than an ST. For the CPUs 42 1.1 mrg in SPARCstation I and II, the times are 3 and 4 cycles, respectively. 43 1.1 mrg Therefore, combining two ST instructions into a STD when possible is a 44 1.1 mrg significant optimization. 45 1.1 mrg 46 1.1 mrg Later SPARC implementations have single cycle ST. 47 1.1 mrg 48 1.1 mrg For SuperSPARC, we can perform just one memory instruction per cycle, even 49 1.1 mrg if up to two integer instructions can be executed in its pipeline. For 50 1.1 mrg programs that perform so many memory operations that there are not enough 51 1.1 mrg non-memory operations to issue in parallel with all memory operations, using 52 1.1 mrg LDD and STD when possible helps. 53 1.1 mrg 54 1.1 mrg UltraSPARC-1/2 has very slow integer multiplication. In the v9 subdirectory, 55 1.1 mrg we therefore use floating-point multiplication. 56 1.1 mrg 57 1.1 mrg STATUS 58 1.1 mrg 59 1.1 mrg 1. On a SuperSPARC, mpn_lshift and mpn_rshift run at 3 cycles/limb, or 2.5 60 1.1 mrg cycles/limb asymptotically. We could optimize speed for special counts 61 1.1 mrg by using ADDXCC. 62 1.1 mrg 63 1.1 mrg 2. On a SuperSPARC, mpn_add_n and mpn_sub_n runs at 2.5 cycles/limb, or 2 64 1.1 mrg cycles/limb asymptotically. 65 1.1 mrg 66 1.1 mrg 3. mpn_mul_1 runs at what is believed to be optimal speed. 67 1.1 mrg 68 1.1 mrg 4. On SuperSPARC, mpn_addmul_1 and mpn_submul_1 could both be improved by a 69 1.1 mrg cycle by avoiding one of the add instructions. See a29k/addmul_1. 70 1.1 mrg 71 1.1 mrg The speed of the code for other SPARC implementations is uncertain. 72
Indexes created Sun Jun 07 00:24:08 UTC 2026