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README revision 1.1 
      1  1.1  mrg Copyright 1996, 2001 Free Software Foundation, Inc.
      2  1.1  mrg 
      3  1.1  mrg This file is part of the GNU MP Library.
      4  1.1  mrg 
      5  1.1  mrg The GNU MP Library is free software; you can redistribute it and/or modify
      6  1.1  mrg it under the terms of the GNU Lesser General Public License as published by
      7  1.1  mrg the Free Software Foundation; either version 3 of the License, or (at your
      8  1.1  mrg option) any later version.
      9  1.1  mrg 
     10  1.1  mrg The GNU MP Library is distributed in the hope that it will be useful, but
     11  1.1  mrg WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
     12  1.1  mrg or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
     13  1.1  mrg License for more details.
     14  1.1  mrg 
     15  1.1  mrg You should have received a copy of the GNU Lesser General Public License
     16  1.1  mrg along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.
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     22  1.1  mrg This directory contains mpn functions for various SPARC chips.  Code that
     23  1.1  mrg runs only on version 8 SPARC implementations, is in the v8 subdirectory.
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     25  1.1  mrg RELEVANT OPTIMIZATION ISSUES
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     27  1.1  mrg   Load and Store timing
     28  1.1  mrg 
     29  1.1  mrg On most early SPARC implementations, the ST instructions takes multiple
     30  1.1  mrg cycles, while a STD takes just a single cycle more than an ST.  For the CPUs
     31  1.1  mrg in SPARCstation I and II, the times are 3 and 4 cycles, respectively.
     32  1.1  mrg Therefore, combining two ST instructions into a STD when possible is a
     33  1.1  mrg significant optimization.
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     35  1.1  mrg Later SPARC implementations have single cycle ST.
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     37  1.1  mrg For SuperSPARC, we can perform just one memory instruction per cycle, even
     38  1.1  mrg if up to two integer instructions can be executed in its pipeline.  For
     39  1.1  mrg programs that perform so many memory operations that there are not enough
     40  1.1  mrg non-memory operations to issue in parallel with all memory operations, using
     41  1.1  mrg LDD and STD when possible helps.
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     43  1.1  mrg UltraSPARC-1/2 has very slow integer multiplication.  In the v9 subdirectory,
     44  1.1  mrg we therefore use floating-point multiplication.
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     46  1.1  mrg STATUS
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     48  1.1  mrg 1. On a SuperSPARC, mpn_lshift and mpn_rshift run at 3 cycles/limb, or 2.5
     49  1.1  mrg    cycles/limb asymptotically.  We could optimize speed for special counts
     50  1.1  mrg    by using ADDXCC.
     51  1.1  mrg 
     52  1.1  mrg 2. On a SuperSPARC, mpn_add_n and mpn_sub_n runs at 2.5 cycles/limb, or 2
     53  1.1  mrg    cycles/limb asymptotically.
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     55  1.1  mrg 3. mpn_mul_1 runs at what is believed to be optimal speed.
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     57  1.1  mrg 4. On SuperSPARC, mpn_addmul_1 and mpn_submul_1 could both be improved by a
     58  1.1  mrg    cycle by avoiding one of the add instructions.  See a29k/addmul_1.
     59  1.1  mrg 
     60  1.1  mrg The speed of the code for other SPARC implementations is uncertain.
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