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      1 Copyright 2001 Free Software Foundation, Inc.
      2 
      3 This file is part of the GNU MP Library.
      4 
      5 The GNU MP Library is free software; you can redistribute it and/or modify
      6 it under the terms of either:
      7 
      8   * the GNU Lesser General Public License as published by the Free
      9     Software Foundation; either version 3 of the License, or (at your
     10     option) any later version.
     11 
     12 or
     13 
     14   * the GNU General Public License as published by the Free Software
     15     Foundation; either version 2 of the License, or (at your option) any
     16     later version.
     17 
     18 or both in parallel, as here.
     19 
     20 The GNU MP Library is distributed in the hope that it will be useful, but
     21 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
     22 or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
     23 for more details.
     24 
     25 You should have received copies of the GNU General Public License and the
     26 GNU Lesser General Public License along with the GNU MP Library.  If not,
     27 see https://www.gnu.org/licenses/.
     28 
     29 
     30 
     31 
     32                    INTEL PENTIUM-4 MPN SUBROUTINES
     33 
     34 
     35 This directory contains mpn functions optimized for Intel Pentium-4.
     36 
     37 The mmx subdirectory has routines using MMX instructions, the sse2
     38 subdirectory has routines using SSE2 instructions.  All P4s have these, the
     39 separate directories are just so configure can omit that code if the
     40 assembler doesn't support it.
     41 
     42 
     43 STATUS
     44 
     45                                 cycles/limb
     46 
     47 	mpn_add_n/sub_n            4 normal, 6 in-place
     48 
     49 	mpn_mul_1                  4 normal, 6 in-place
     50 	mpn_addmul_1               6
     51 	mpn_submul_1               7
     52 
     53 	mpn_mul_basecase           6 cycles/crossproduct (approx)
     54 
     55 	mpn_sqr_basecase           3.5 cycles/crossproduct (approx)
     56                                    or 7.0 cycles/triangleproduct (approx)
     57 
     58 	mpn_l/rshift               1.75
     59 
     60 
     61 
     62 The shifts ought to be able to go at 1.5 c/l, but not much effort has been
     63 applied to them yet.
     64 
     65 In-place operations, and all addmul, submul, mul_basecase and sqr_basecase
     66 calls, suffer from pipeline anomalies associated with write combining and
     67 movd reads and writes to the same or nearby locations.  The movq
     68 instructions do not trigger the same hardware problems.  Unfortunately,
     69 using movq and splitting/combining seems to require too many extra
     70 instructions to help.  Perhaps future chip steppings will be better.
     71 
     72 
     73 
     74 NOTES
     75 
     76 The Pentium-4 pipeline "Netburst", provides for quite a number of surprises.
     77 Many traditional x86 instructions run very slowly, requiring use of
     78 alterative instructions for acceptable performance.
     79 
     80 adcl and sbbl are quite slow at 8 cycles for reg->reg.  paddq of 32-bits
     81 within a 64-bit mmx register seems better, though the combination
     82 paddq/psrlq when propagating a carry is still a 4 cycle latency.
     83 
     84 incl and decl should be avoided, instead use add $1 and sub $1.  Apparently
     85 the carry flag is not separately renamed, so incl and decl depend on all
     86 previous flags-setting instructions.
     87 
     88 shll and shrl have a 4 cycle latency, or 8 times the latency of the fastest
     89 integer instructions (addl, subl, orl, andl, and some more).  shldl and
     90 shrdl seem to have 13 and 15 cycles latency, respectively.  Bizarre.
     91 
     92 movq mmx -> mmx does have 6 cycle latency, as noted in the documentation.
     93 pxor/por or similar combination at 2 cycles latency can be used instead.
     94 The movq however executes in the float unit, thereby saving MMX execution
     95 resources.  With the right juggling, data moves shouldn't be on a dependent
     96 chain.
     97 
     98 L1 is write-through, but the write-combining sounds like it does enough to
     99 not require explicit destination prefetching.
    100 
    101 xmm registers so far haven't found a use, but not much effort has been
    102 expended.  A configure test for whether the operating system knows
    103 fxsave/fxrestor will be needed if they're used.
    104 
    105 
    106 
    107 REFERENCES
    108 
    109 Intel Pentium-4 processor manuals,
    110 
    111 	http://developer.intel.com/design/pentium4/manuals
    112 
    113 "Intel Pentium 4 Processor Optimization Reference Manual", Intel, 2001,
    114 order number 248966.  Available on-line:
    115 
    116 	http://developer.intel.com/design/pentium4/manuals/248966.htm
    117 
    118 
    119 
    120 ----------------
    121 Local variables:
    122 mode: text
    123 fill-column: 76
    124 End:
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