Copyright (c) 2009 Ken Hornstein.
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.Dd February 22, 2009 .Dt EPGPIO 4 .Os .Sh NAME .Nm epgpio .Nd General Purpose I/O support for Cirrus EP93xx ARM processors .Sh SYNOPSIS .Cd "epgpio0 at epsoc? addr 0x80840000 size 0xcc intr 59" .Cd "gpio* at epgpio?"
p .Cd options EPGPIO_PORT_A_MASK=0xXX .Cd options EPGPIO_PORT_B_MASK=0xXX .Cd options EPGPIO_PORT_C_MASK=0xXX .Cd options EPGPIO_PORT_D_MASK=0xXX .Cd options EPGPIO_PORT_E_MASK=0xXX .Cd options EPGPIO_PORT_F_MASK=0xXX .Cd options EPGPIO_PORT_G_MASK=0xXX .Cd options EPGPIO_PORT_H_MASK=0xXX .Sh DESCRIPTION The .Nm driver provides support for the on-board General Purpose I/O (GPIO) pins on the Cirrus Logic EP93xx series of processors. There are 8 GPIO ports (Ports A though H) each having 8 GPIO pins available (note: early revisions of some EP9301 processors have some ports with less than eight pins available on each port; check the documentation for your specific processor).
p The .Nm driver provides a .Xr gpio 4 controller interface and will attach each port as a separate .Xr gpio 4 device with 8 pins available. All pins are bidirectional; when used as inputs they should not be driven beyond TTL voltage levels, but for exact details on the electrical interface the documentation for the specific evbarm board should be consulted. .Ss Kernel options The following kernel options are available to configure the behavior of the .Nm driver.
p l -tag -width "options" -compact t Cd options EPGPIO_PORT_A_MASK=0xXX t Cd options EPGPIO_PORT_B_MASK=0xXX t Cd options EPGPIO_PORT_C_MASK=0xXX t Cd options EPGPIO_PORT_D_MASK=0xXX t Cd options EPGPIO_PORT_E_MASK=0xXX t Cd options EPGPIO_PORT_F_MASK=0xXX t Cd options EPGPIO_PORT_G_MASK=0xXX t Cd options EPGPIO_PORT_H_MASK=0xXX .El
p Each of these options is a bitmask specifying the pins available to the .Xr gpio 4 controller for the corresponding port. Pins should be disabled if they are not available or are being used by the hardware for other purposes. The default mask is .Dq 0xff for all ports. .Sh IMPLEMENTATION NOTES When a port bitmask configures less than 8 pins available, the remaining pins will appear as sequentially numbered pins to the .Xr gpio 4 interface. For example, if .Dv EPGPIO_PORT_A_MASK is set to .Dq 0x2c , Port A pins 1, 3, and 5 will appear as .Xr gpio 4 pins 0, 1, and 2 respectively. .Sh SEE ALSO .Xr gpio 4
Indexes created Wed Sep 24 15:09:51 GMT 2025