armreg.h revision 1.11
1 /* $NetBSD: armreg.h,v 1.11 2018/07/15 16:08:30 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _AARCH64_ARMREG_H_ 33 #define _AARCH64_ARMREG_H_ 34 35 #include <arm/cputypes.h> 36 #include <sys/types.h> 37 38 #define AARCH64REG_READ_INLINE2(regname, regdesc) \ 39 static uint64_t inline \ 40 reg_##regname##_read(void) \ 41 { \ 42 uint64_t __rv; \ 43 __asm __volatile("mrs %0, " #regdesc : "=r"(__rv)); \ 44 return __rv; \ 45 } 46 47 #define AARCH64REG_WRITE_INLINE2(regname, regdesc) \ 48 static void inline \ 49 reg_##regname##_write(uint64_t __val) \ 50 { \ 51 __asm __volatile("msr " #regdesc ", %0" :: "r"(__val)); \ 52 } 53 54 #define AARCH64REG_WRITEIMM_INLINE2(regname, regdesc) \ 55 static void inline \ 56 reg_##regname##_write(uint64_t __val) \ 57 { \ 58 __asm __volatile("msr " #regdesc ", %0" :: "n"(__val)); \ 59 } 60 61 #define AARCH64REG_READ_INLINE(regname) \ 62 AARCH64REG_READ_INLINE2(regname, regname) 63 64 #define AARCH64REG_WRITE_INLINE(regname) \ 65 AARCH64REG_WRITE_INLINE2(regname, regname) 66 67 #define AARCH64REG_WRITEIMM_INLINE(regname) \ 68 AARCH64REG_WRITEIMM_INLINE2(regname, regname) 69 /* 70 * System registers available at EL0 (user) 71 */ 72 AARCH64REG_READ_INLINE(ctr_el0) // Cache Type Register 73 74 static const uintmax_t 75 CTR_EL0_CWG_LINE = __BITS(27,24), // Cacheback Writeback Granule 76 CTR_EL0_ERG_LINE = __BITS(23,20), // Exclusives Reservation Granule 77 CTR_EL0_DMIN_LINE = __BITS(19,16), // Dcache MIN LINE size (log2 - 2) 78 CTR_EL0_L1IP_MASK = __BITS(15,14), 79 CTR_EL0_L1IP_AIVIVT = 1, // ASID-tagged Virtual Index, Virtual Tag 80 CTR_EL0_L1IP_VIPT = 2, // Virtual Index, Physical Tag 81 CTR_EL0_L1IP_PIPT = 3, // Physical Index, Physical Tag 82 CTR_EL0_IMIN_LINE = __BITS(3,0); // Icache MIN LINE size (log2 - 2) 83 84 AARCH64REG_READ_INLINE(dczid_el0) // Data Cache Zero ID Register 85 86 static const uintmax_t 87 DCZID_DZP = __BIT(4), // Data Zero Prohibited 88 DCZID_BS = __BITS(3,0); // Block Size (log2 - 2) 89 90 AARCH64REG_READ_INLINE(fpcr) // Floating Point Control Register 91 AARCH64REG_WRITE_INLINE(fpcr) 92 93 static const uintmax_t 94 FPCR_AHP = __BIT(26), // Alternative Half Precision 95 FPCR_DN = __BIT(25), // Default Nan Control 96 FPCR_FZ = __BIT(24), // Flush-To-Zero 97 FPCR_RMODE = __BITS(23,22),// Rounding Mode 98 FPCR_RN = 0, // Round Nearest 99 FPCR_RP = 1, // Round towards Plus infinity 100 FPCR_RM = 2, // Round towards Minus infinity 101 FPCR_RZ = 3, // Round towards Zero 102 FPCR_STRIDE = __BITS(21,20), 103 FPCR_LEN = __BITS(18,16), 104 FPCR_IDE = __BIT(15), // Input Denormal Exception enable 105 FPCR_IXE = __BIT(12), // IneXact Exception enable 106 FPCR_UFE = __BIT(11), // UnderFlow Exception enable 107 FPCR_OFE = __BIT(10), // OverFlow Exception enable 108 FPCR_DZE = __BIT(9), // Divide by Zero Exception enable 109 FPCR_IOE = __BIT(8), // Invalid Operation Exception enable 110 FPCR_ESUM = 0x1F00; 111 112 AARCH64REG_READ_INLINE(fpsr) // Floating Point Status Register 113 AARCH64REG_WRITE_INLINE(fpsr) 114 115 static const uintmax_t 116 FPSR_N32 = __BIT(31), // AARCH32 Negative 117 FPSR_Z32 = __BIT(30), // AARCH32 Zero 118 FPSR_C32 = __BIT(29), // AARCH32 Carry 119 FPSR_V32 = __BIT(28), // AARCH32 Overflow 120 FPSR_QC = __BIT(27), // SIMD Saturation 121 FPSR_IDC = __BIT(7), // Input Denormal Cumulative status 122 FPSR_IXC = __BIT(4), // IneXact Cumulative status 123 FPSR_UFC = __BIT(3), // UnderFlow Cumulative status 124 FPSR_OFC = __BIT(2), // OverFlow Cumulative status 125 FPSR_DZC = __BIT(1), // Divide by Zero Cumulative status 126 FPSR_IOC = __BIT(0), // Invalid Operation Cumulative status 127 FPSR_CSUM = 0x1F; 128 129 AARCH64REG_READ_INLINE(nzcv) // condition codes 130 AARCH64REG_WRITE_INLINE(nzcv) 131 132 static const uintmax_t 133 NZCV_N = __BIT(31), // Negative 134 NZCV_Z = __BIT(30), // Zero 135 NZCV_C = __BIT(29), // Carry 136 NZCV_V = __BIT(28); // Overflow 137 138 AARCH64REG_READ_INLINE(tpidr_el0) // Thread Pointer ID Register (RW) 139 AARCH64REG_WRITE_INLINE(tpidr_el0) 140 141 AARCH64REG_READ_INLINE(tpidrro_el0) // Thread Pointer ID Register (RO) 142 143 /* 144 * From here on, these can only be accessed at EL1 (kernel) 145 */ 146 147 /* 148 * These are readonly registers 149 */ 150 AARCH64REG_READ_INLINE(aidr_el1) 151 152 AARCH64REG_READ_INLINE2(cbar_el1, s3_1_c15_c3_0) // Cortex-A57 153 154 static const uintmax_t CBAR_PA = __BITS(47,18); 155 156 AARCH64REG_READ_INLINE(ccsidr_el1) 157 158 static const uintmax_t 159 CCSIDR_WT = __BIT(31), // Write-through supported 160 CCSIDR_WB = __BIT(30), // Write-back supported 161 CCSIDR_RA = __BIT(29), // Read-allocation supported 162 CCSIDR_WA = __BIT(28), // Write-allocation supported 163 CCSIDR_NUMSET = __BITS(27,13),// (Number of sets in cache) - 1 164 CCSIDR_ASSOC = __BITS(12,3), // (Associativity of cache) - 1 165 CCSIDR_LINESIZE = __BITS(2,0); // Number of bytes in cache line 166 167 AARCH64REG_READ_INLINE(clidr_el1) 168 169 static const uintmax_t 170 CLIDR_LOUU = __BITS(29,27), // Level of Unification Uniprocessor 171 CLIDR_LOC = __BITS(26,24), // Level of Coherency 172 CLIDR_LOUIS = __BITS(23,21), // Level of Unification InnerShareable*/ 173 CLIDR_CTYPE7 = __BITS(20,18), // Cache Type field for level7 174 CLIDR_CTYPE6 = __BITS(17,15), // Cache Type field for level6 175 CLIDR_CTYPE5 = __BITS(14,12), // Cache Type field for level5 176 CLIDR_CTYPE4 = __BITS(11,9), // Cache Type field for level4 177 CLIDR_CTYPE3 = __BITS(8,6), // Cache Type field for level3 178 CLIDR_CTYPE2 = __BITS(5,3), // Cache Type field for level2 179 CLIDR_CTYPE1 = __BITS(2,0), // Cache Type field for level1 180 CLIDR_TYPE_NOCACHE = 0, // No cache 181 CLIDR_TYPE_ICACHE = 1, // Instruction cache only 182 CLIDR_TYPE_DCACHE = 2, // Data cache only 183 CLIDR_TYPE_IDCACHE = 3, // Separate inst and data caches 184 CLIDR_TYPE_UNIFIEDCACHE = 4; // Unified cache 185 186 AARCH64REG_READ_INLINE(currentel) 187 AARCH64REG_READ_INLINE(id_aa64afr0_el1) 188 AARCH64REG_READ_INLINE(id_aa64afr1_el1) 189 AARCH64REG_READ_INLINE(id_aa64dfr0_el1) 190 191 static const uintmax_t 192 ID_AA64DFR0_EL1_CTX_CMPS = __BITS(31,28), 193 ID_AA64DFR0_EL1_WRPS = __BITS(20,23), 194 ID_AA64DFR0_EL1_BRPS = __BITS(12,15), 195 ID_AA64DFR0_EL1_PMUVER = __BITS(8,11), 196 ID_AA64DFR0_EL1_PMUVER_NONE = 0, 197 ID_AA64DFR0_EL1_PMUVER_V3 = 1, 198 ID_AA64DFR0_EL1_PMUVER_NOV3 = 2, 199 ID_AA64DFR0_EL1_TRACEVER = __BITS(4,7), 200 ID_AA64DFR0_EL1_TRACEVER_NONE = 0, 201 ID_AA64DFR0_EL1_TRACEVER_IMPL = 1, 202 ID_AA64DFR0_EL1_DEBUGVER = __BITS(0,3), 203 ID_AA64DFR0_EL1_DEBUGVER_V8A = 6; 204 205 AARCH64REG_READ_INLINE(id_aa64dfr1_el1) 206 207 AARCH64REG_READ_INLINE(id_aa64isar0_el1) 208 209 static const uintmax_t 210 ID_AA64ISAR0_EL1_CRC32 = __BITS(19,16), 211 ID_AA64ISAR0_EL1_CRC32_NONE = 0, 212 ID_AA64ISAR0_EL1_CRC32_CRC32X = 1, 213 ID_AA64ISAR0_EL1_SHA2 = __BITS(15,12), 214 ID_AA64ISAR0_EL1_SHA2_NONE = 0, 215 ID_AA64ISAR0_EL1_SHA2_SHA256HSU = 1, 216 ID_AA64ISAR0_EL1_SHA1 = __BITS(11,8), 217 ID_AA64ISAR0_EL1_SHA1_NONE = 0, 218 ID_AA64ISAR0_EL1_SHA1_SHA1CPMHSU = 1, 219 ID_AA64ISAR0_EL1_AES = __BITS(7,4), 220 ID_AA64ISAR0_EL1_AES_NONE = 0, 221 ID_AA64ISAR0_EL1_AES_AES = 1, 222 ID_AA64ISAR0_EL1_AES_PMUL = 2; 223 224 AARCH64REG_READ_INLINE(id_aa64isar1_el1) 225 AARCH64REG_READ_INLINE(id_aa64mmfr0_el1) 226 227 static const uintmax_t 228 ID_AA64MMFR0_EL1_TGRAN4 = __BITS(31,28), 229 ID_AA64MMFR0_EL1_TGRAN4_4KB = 0, 230 ID_AA64MMFR0_EL1_TGRAN4_NONE = 15, 231 ID_AA64MMFR0_EL1_TGRAN64 = __BITS(24,27), 232 ID_AA64MMFR0_EL1_TGRAN64_64KB = 0, 233 ID_AA64MMFR0_EL1_TGRAN64_NONE = 15, 234 ID_AA64MMFR0_EL1_TGRAN16 = __BITS(20,23), 235 ID_AA64MMFR0_EL1_TGRAN16_NONE = 0, 236 ID_AA64MMFR0_EL1_TGRAN16_16KB = 1, 237 ID_AA64MMFR0_EL1_BIGENDEL0 = __BITS(16,19), 238 ID_AA64MMFR0_EL1_BIGENDEL0_NONE = 0, 239 ID_AA64MMFR0_EL1_BIGENDEL0_MIX = 1, 240 ID_AA64MMFR0_EL1_SNSMEM = __BITS(12,15), 241 ID_AA64MMFR0_EL1_SNSMEM_NONE = 0, 242 ID_AA64MMFR0_EL1_SNSMEM_SNSMEM = 1, 243 ID_AA64MMFR0_EL1_BIGEND = __BITS(8,11), 244 ID_AA64MMFR0_EL1_BIGEND_NONE = 0, 245 ID_AA64MMFR0_EL1_BIGEND_MIX = 1, 246 ID_AA64MMFR0_EL1_ASIDBITS = __BITS(4,7), 247 ID_AA64MMFR0_EL1_ASIDBITS_8BIT = 0, 248 ID_AA64MMFR0_EL1_ASIDBITS_16BIT = 2, 249 ID_AA64MMFR0_EL1_PARANGE = __BITS(0,3), 250 ID_AA64MMFR0_EL1_PARANGE_4G = 0, 251 ID_AA64MMFR0_EL1_PARANGE_64G = 1, 252 ID_AA64MMFR0_EL1_PARANGE_1T = 2, 253 ID_AA64MMFR0_EL1_PARANGE_4T = 3, 254 ID_AA64MMFR0_EL1_PARANGE_16T = 4, 255 ID_AA64MMFR0_EL1_PARANGE_256T = 5; 256 257 AARCH64REG_READ_INLINE(id_aa64mmfr1_el1) 258 AARCH64REG_READ_INLINE(id_aa64pfr0_el1) 259 AARCH64REG_READ_INLINE(id_aa64pfr1_el1) 260 AARCH64REG_READ_INLINE(id_pfr1_el1) 261 AARCH64REG_READ_INLINE(isr_el1) 262 AARCH64REG_READ_INLINE(midr_el1) 263 AARCH64REG_READ_INLINE(mpidr_el1) 264 265 static const uintmax_t 266 MPIDR_AFF3 = __BITS(32,39), 267 MPIDR_U = __BIT(30), // 1 = Uni-Processor System 268 MPIDR_MT = __BIT(24), // 1 = SMT(AFF0 is logical) 269 MPIDR_AFF2 = __BITS(16,23), 270 MPIDR_AFF1 = __BITS(8,15), 271 MPIDR_AFF0 = __BITS(0,7); 272 273 AARCH64REG_READ_INLINE(mvfr0_el1) 274 275 static const uintmax_t 276 MVFR0_FPROUND = __BITS(31,28), 277 MVFR0_FPROUND_NEAREST = 0, 278 MVFR0_FPROUND_ALL = 1, 279 MVFR0_FPSHVEC = __BITS(27,24), 280 MVFR0_FPSHVEC_NONE = 0, 281 MVFR0_FPSHVEC_SHVEC = 1, 282 MVFR0_FPSQRT = __BITS(23,20), 283 MVFR0_FPSQRT_NONE = 0, 284 MVFR0_FPSQRT_VSQRT = 1, 285 MVFR0_FPDIVIDE = __BITS(19,16), 286 MVFR0_FPDIVIDE_NONE = 0, 287 MVFR0_FPDIVIDE_VDIV = 1, 288 MVFR0_FPTRAP = __BITS(15,12), 289 MVFR0_FPTRAP_NONE = 0, 290 MVFR0_FPTRAP_TRAP = 1, 291 MVFR0_FPDP = __BITS(11,8), 292 MVFR0_FPDP_NONE = 0, 293 MVFR0_FPDP_VFPV2 = 1, 294 MVFR0_FPDP_VFPV3 = 2, 295 MVFR0_FPSP = __BITS(7,4), 296 MVFR0_FPSP_NONE = 0, 297 MVFR0_FPSP_VFPV2 = 1, 298 MVFR0_FPSP_VFPV3 = 2, 299 MVFR0_SIMDREG = __BITS(3,0), 300 MVFR0_SIMDREG_NONE = 0, 301 MVFR0_SIMDREG_16x64 = 1, 302 MVFR0_SIMDREG_32x64 = 2; 303 304 AARCH64REG_READ_INLINE(mvfr1_el1) 305 306 static const uintmax_t 307 MVFR1_SIMDFMAC = __BITS(31,28), 308 MVFR1_SIMDFMAC_NONE = 0, 309 MVFR1_SIMDFMAC_FMAC = 1, 310 MVFR1_FPHP = __BITS(27,24), 311 MVFR1_FPHP_NONE = 0, 312 MVFR1_FPHP_HALF_SINGLE = 1, 313 MVFR1_FPHP_HALF_DOUBLE = 2, 314 MVFR1_SIMDHP = __BITS(23,20), 315 MVFR1_SIMDHP_NONE = 0, 316 MVFR1_SIMDHP_HALF = 1, 317 MVFR1_SIMDSP = __BITS(19,16), 318 MVFR1_SIMDSP_NONE = 0, 319 MVFR1_SIMDSP_SINGLE = 1, 320 MVFR1_SIMDINT = __BITS(15,12), 321 MVFR1_SIMDINT_NONE = 0, 322 MVFR1_SIMDINT_INTEGER = 1, 323 MVFR1_SIMDLS = __BITS(11,8), 324 MVFR1_SIMDLS_NONE = 0, 325 MVFR1_SIMDLS_LOADSTORE = 1, 326 MVFR1_FPDNAN = __BITS(7,4), 327 MVFR1_FPDNAN_NONE = 0, 328 MVFR1_FPDNAN_NAN = 1, 329 MVFR1_FPFTZ = __BITS(3,0), 330 MVFR1_FPFTZ_NONE = 0, 331 MVFR1_FPFTZ_DENORMAL = 1; 332 333 AARCH64REG_READ_INLINE(mvfr2_el1) 334 335 static const uintmax_t 336 MVFR2_FPMISC = __BITS(7,4), 337 MVFR2_FPMISC_NONE = 0, 338 MVFR2_FPMISC_SEL = 1, 339 MVFR2_FPMISC_DROUND = 2, 340 MVFR2_FPMISC_ROUNDINT = 3, 341 MVFR2_FPMISC_MAXMIN = 4, 342 MVFR2_SIMDMISC = __BITS(3,0), 343 MVFR2_SIMDMISC_NONE = 0, 344 MVFR2_SIMDMISC_DROUND = 1, 345 MVFR2_SIMDMISC_ROUNDINT = 2, 346 MVFR2_SIMDMISC_MAXMIN = 3; 347 348 AARCH64REG_READ_INLINE(revidr_el1) 349 350 /* 351 * These are read/write registers 352 */ 353 AARCH64REG_READ_INLINE(cpacr_el1) // Coprocessor Access Control Regiser 354 AARCH64REG_WRITE_INLINE(cpacr_el1) 355 356 static const uintmax_t 357 CPACR_TTA = __BIT(28), // System Register Access Traps 358 CPACR_FPEN = __BITS(21,20), 359 CPACR_FPEN_NONE = __SHIFTIN(0, CPACR_FPEN), 360 CPACR_FPEN_EL1 = __SHIFTIN(1, CPACR_FPEN), 361 CPACR_FPEN_NONE_2 = __SHIFTIN(2, CPACR_FPEN), 362 CPACR_FPEN_ALL = __SHIFTIN(3, CPACR_FPEN); 363 364 AARCH64REG_READ_INLINE(csselr_el1) // Cache Size Selection Register 365 AARCH64REG_WRITE_INLINE(csselr_el1) 366 367 static const uintmax_t 368 CSSELR_LEVEL = __BITS(3,1), // Cache level of required cache 369 CSSELR_IND = __BIT(0); // Instruction not Data bit 370 371 AARCH64REG_READ_INLINE(daif) // Debug Async Irq Fiq mask register 372 AARCH64REG_WRITE_INLINE(daif) 373 AARCH64REG_WRITEIMM_INLINE(daifclr) 374 AARCH64REG_WRITEIMM_INLINE(daifset) 375 376 static const uintmax_t 377 DAIF_D = __BIT(9), // Debug Exception Mask 378 DAIF_A = __BIT(8), // SError Abort Mask 379 DAIF_I = __BIT(7), // IRQ Mask 380 DAIF_F = __BIT(6), // FIQ Mask 381 DAIF_SETCLR_SHIFT = 6; // for daifset/daifclr #imm shift 382 383 AARCH64REG_READ_INLINE(elr_el1) // Exception Link Register 384 AARCH64REG_WRITE_INLINE(elr_el1) 385 386 AARCH64REG_READ_INLINE(esr_el1) // Exception Symdrone Register 387 AARCH64REG_WRITE_INLINE(esr_el1) 388 389 static const uintmax_t 390 ESR_EC = __BITS(31,26), // Exception Cause 391 ESR_EC_UNKNOWN = 0x00, // AXX: Unknown Reason 392 ESR_EC_WFX = 0x01, // AXX: WFI or WFE instruction execution 393 ESR_EC_CP15_RT = 0x03, // A32: MCR/MRC access to CP15 !EC=0 394 ESR_EC_CP15_RRT = 0x04, // A32: MCRR/MRRC access to CP15 !EC=0 395 ESR_EC_CP14_RT = 0x05, // A32: MCR/MRC access to CP14 396 ESR_EC_CP14_DT = 0x06, // A32: LDC/STC access to CP14 397 ESR_EC_FP_ACCESS = 0x07, // AXX: Access to SIMD/FP Registers 398 ESR_EC_FPID = 0x08, // A32: MCR/MRC access to CP10 !EC=7 399 ESR_EC_CP14_RRT = 0x0c, // A32: MRRC access to CP14 400 ESR_EC_ILL_STATE = 0x0e, // AXX: Illegal Execution State 401 ESR_EC_SVC_A32 = 0x11, // A32: SVC Instruction Execution 402 ESR_EC_HVC_A32 = 0x12, // A32: HVC Instruction Execution 403 ESR_EC_SMC_A32 = 0x13, // A32: SMC Instruction Execution 404 ESR_EC_SVC_A64 = 0x15, // A64: SVC Instruction Execution 405 ESR_EC_HVC_A64 = 0x16, // A64: HVC Instruction Execution 406 ESR_EC_SMC_A64 = 0x17, // A64: SMC Instruction Execution 407 ESR_EC_SYS_REG = 0x18, // A64: MSR/MRS/SYS instruction (!EC0/1/7) 408 ESR_EC_INSN_ABT_EL0 = 0x20, // AXX: Instruction Abort (EL0) 409 ESR_EC_INSN_ABT_EL1 = 0x21, // AXX: Instruction Abort (EL1) 410 ESR_EC_PC_ALIGNMENT = 0x22, // AXX: Misaligned PC 411 ESR_EC_DATA_ABT_EL0 = 0x24, // AXX: Data Abort (EL0) 412 ESR_EC_DATA_ABT_EL1 = 0x25, // AXX: Data Abort (EL1) 413 ESR_EC_SP_ALIGNMENT = 0x26, // AXX: Misaligned SP 414 ESR_EC_FP_TRAP_A32 = 0x28, // A32: FP Exception 415 ESR_EC_FP_TRAP_A64 = 0x2c, // A64: FP Exception 416 ESR_EC_SERROR = 0x2f, // AXX: SError Interrupt 417 ESR_EC_BRKPNT_EL0 = 0x30, // AXX: Breakpoint Exception (EL0) 418 ESR_EC_BRKPNT_EL1 = 0x31, // AXX: Breakpoint Exception (EL1) 419 ESR_EC_SW_STEP_EL0 = 0x32, // AXX: Software Step (EL0) 420 ESR_EC_SW_STEP_EL1 = 0x33, // AXX: Software Step (EL1) 421 ESR_EC_WTCHPNT_EL0 = 0x34, // AXX: Watchpoint (EL0) 422 ESR_EC_WTCHPNT_EL1 = 0x35, // AXX: Watchpoint (EL1) 423 ESR_EC_BKPT_INSN_A32 = 0x38, // A32: BKPT Instruction Execution 424 ESR_EC_VECTOR_CATCH = 0x3a, // A32: Vector Catch Exception 425 ESR_EC_BKPT_INSN_A64 = 0x3c, // A64: BKPT Instruction Execution 426 ESR_IL = __BIT(25), // Instruction Length (1=32-bit) 427 ESR_ISS = __BITS(24,0), // Instruction Specific Syndrome 428 ESR_ISS_CV = __BIT(24), // common 429 ESR_ISS_COND = __BITS(23,20), // common 430 ESR_ISS_WFX_TRAP_INSN = __BIT(0), // for ESR_EC_WFX 431 ESR_ISS_MRC_OPC2 = __BITS(19,17), // for ESR_EC_CP15_RT 432 ESR_ISS_MRC_OPC1 = __BITS(16,14), // for ESR_EC_CP15_RT 433 ESR_ISS_MRC_CRN = __BITS(13,10), // for ESR_EC_CP15_RT 434 ESR_ISS_MRC_RT = __BITS(9,5), // for ESR_EC_CP15_RT 435 ESR_ISS_MRC_CRM = __BITS(4,1), // for ESR_EC_CP15_RT 436 ESR_ISS_MRC_DIRECTION = __BIT(0), // for ESR_EC_CP15_RT 437 ESR_ISS_MCRR_OPC1 = __BITS(19,16), // for ESR_EC_CP15_RRT 438 ESR_ISS_MCRR_RT2 = __BITS(14,10), // for ESR_EC_CP15_RRT 439 ESR_ISS_MCRR_RT = __BITS(9,5), // for ESR_EC_CP15_RRT 440 ESR_ISS_MCRR_CRM = __BITS(4,1), // for ESR_EC_CP15_RRT 441 ESR_ISS_MCRR_DIRECTION = __BIT(0), // for ESR_EC_CP15_RRT 442 ESR_ISS_HVC_IMM16 = __BITS(15,0), // for ESR_EC_{SVC,HVC} 443 // ... 444 ESR_ISS_INSNABORT_EA = __BIT(9), // for ESC_RC_INSN_ABT_EL[01] 445 ESR_ISS_INSNABORT_S1PTW = __BIT(7), // for ESC_RC_INSN_ABT_EL[01] 446 ESR_ISS_INSNABORT_IFSC = __BITS(0,5), // for ESC_RC_INSN_ABT_EL[01] 447 ESR_ISS_DATAABORT_ISV = __BIT(24), // for ESC_RC_DATA_ABT_EL[01] 448 ESR_ISS_DATAABORT_SAS = __BITS(23,22), // for ESC_RC_DATA_ABT_EL[01] 449 ESR_ISS_DATAABORT_SSE = __BIT(21), // for ESC_RC_DATA_ABT_EL[01] 450 ESR_ISS_DATAABORT_SRT = __BITS(19,16), // for ESC_RC_DATA_ABT_EL[01] 451 ESR_ISS_DATAABORT_SF = __BIT(15), // for ESC_RC_DATA_ABT_EL[01] 452 ESR_ISS_DATAABORT_AR = __BIT(14), // for ESC_RC_DATA_ABT_EL[01] 453 ESR_ISS_DATAABORT_EA = __BIT(9), // for ESC_RC_DATA_ABT_EL[01] 454 ESR_ISS_DATAABORT_CM = __BIT(8), // for ESC_RC_DATA_ABT_EL[01] 455 ESR_ISS_DATAABORT_S1PTW = __BIT(7), // for ESC_RC_DATA_ABT_EL[01] 456 ESR_ISS_DATAABORT_WnR = __BIT(6), // for ESC_RC_DATA_ABT_EL[01] 457 ESR_ISS_DATAABORT_DFSC = __BITS(0,5); // for ESC_RC_DATA_ABT_EL[01] 458 459 static const uintmax_t // ESR_ISS_{INSN,DATA}ABORT_FSC 460 ESR_ISS_FSC_ADDRESS_SIZE_FAULT_0 = 0x00, 461 ESR_ISS_FSC_ADDRESS_SIZE_FAULT_1 = 0x01, 462 ESR_ISS_FSC_ADDRESS_SIZE_FAULT_2 = 0x02, 463 ESR_ISS_FSC_ADDRESS_SIZE_FAULT_3 = 0x03, 464 ESR_ISS_FSC_TRANSLATION_FAULT_0 = 0x04, 465 ESR_ISS_FSC_TRANSLATION_FAULT_1 = 0x05, 466 ESR_ISS_FSC_TRANSLATION_FAULT_2 = 0x06, 467 ESR_ISS_FSC_TRANSLATION_FAULT_3 = 0x07, 468 ESR_ISS_FSC_ACCESS_FAULT_0 = 0x08, 469 ESR_ISS_FSC_ACCESS_FAULT_1 = 0x09, 470 ESR_ISS_FSC_ACCESS_FAULT_2 = 0x0a, 471 ESR_ISS_FSC_ACCESS_FAULT_3 = 0x0b, 472 ESR_ISS_FSC_PERM_FAULT_0 = 0x0c, 473 ESR_ISS_FSC_PERM_FAULT_1 = 0x0d, 474 ESR_ISS_FSC_PERM_FAULT_2 = 0x0e, 475 ESR_ISS_FSC_PERM_FAULT_3 = 0x0f, 476 ESR_ISS_FSC_SYNC_EXTERNAL_ABORT = 0x10, 477 ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_0 = 0x14, 478 ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_1 = 0x15, 479 ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_2 = 0x16, 480 ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_3 = 0x17, 481 ESR_ISS_FSC_SYNC_PARITY_ERROR = 0x18, 482 ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_0 = 0x1c, 483 ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_1 = 0x1d, 484 ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_2 = 0x1e, 485 ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_3 = 0x1f, 486 ESR_ISS_FSC_ALIGNMENT_FAULT = 0x21, 487 ESR_ISS_FSC_TLB_CONFLICT_FAULT = 0x30, 488 ESR_ISS_FSC_LOCKDOWN_ABORT = 0x34, 489 ESR_ISS_FSC_UNSUPPORTED_EXCLUSIVE = 0x35, 490 ESR_ISS_FSC_FIRST_LEVEL_DOMAIN_FAULT = 0x3d, 491 ESR_ISS_FSC_SECOND_LEVEL_DOMAIN_FAULT = 0x3e; 492 493 494 AARCH64REG_READ_INLINE(far_el1) // Fault Address Register 495 AARCH64REG_WRITE_INLINE(far_el1) 496 497 AARCH64REG_READ_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73 498 AARCH64REG_WRITE_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73 499 500 static const uintmax_t 501 L2CTLR_NUMOFCORE = __BITS(25,24),// Number of cores 502 L2CTLR_CPUCACHEPROT = __BIT(22), // CPU Cache Protection 503 L2CTLR_SCUL2CACHEPROT = __BIT(21), // SCU-L2 Cache Protection 504 L2CTLR_L2_INPUT_LATENCY = __BIT(5), // L2 Data RAM input latency 505 L2CTLR_L2_OUTPUT_LATENCY = __BIT(0); // L2 Data RAM output latency 506 507 AARCH64REG_READ_INLINE(mair_el1) // Memory Attribute Indirection Register 508 AARCH64REG_WRITE_INLINE(mair_el1) 509 510 static const uintmax_t 511 MAIR_ATTR0 = __BITS(7,0), 512 MAIR_ATTR1 = __BITS(15,8), 513 MAIR_ATTR2 = __BITS(23,16), 514 MAIR_ATTR3 = __BITS(31,24), 515 MAIR_ATTR4 = __BITS(39,32), 516 MAIR_ATTR5 = __BITS(47,40), 517 MAIR_ATTR6 = __BITS(55,48), 518 MAIR_ATTR7 = __BITS(63,56), 519 MAIR_DEVICE_nGnRnE = 0x00, // NoGathering,NoReordering,NoEarlyWriteAck. 520 MAIR_NORMAL_NC = 0x44, 521 MAIR_NORMAL_WT = 0xbb, 522 MAIR_NORMAL_WB = 0xff; 523 524 AARCH64REG_READ_INLINE(par_el1) // Physical Address Register 525 AARCH64REG_WRITE_INLINE(par_el1) 526 527 static const uintmax_t 528 PAR_ATTR = __BITS(63,56),// F=0 memory attributes 529 PAR_PA = __BITS(47,12),// F=0 physical address 530 PAR_NS = __BIT(9), // F=0 non-secure 531 PAR_S = __BIT(9), // F=1 failure stage 532 PAR_SHA = __BITS(8,7), // F=0 shareability attribute 533 PAR_SHA_NONE = 0, 534 PAR_SHA_OUTER = 2, 535 PAR_SHA_INNER = 3, 536 PAR_PTW = __BIT(8), // F=1 partial table walk 537 PAR_FST = __BITS(6,1), // F=1 fault status code 538 PAR_F = __BIT(0); // translation failed 539 540 AARCH64REG_READ_INLINE(rmr_el1) // Reset Management Register 541 AARCH64REG_WRITE_INLINE(rmr_el1) 542 543 AARCH64REG_READ_INLINE(rvbar_el1) // Reset Vector Base Address Register 544 AARCH64REG_WRITE_INLINE(rvbar_el1) 545 546 AARCH64REG_READ_INLINE(sctlr_el1) // System Control Register 547 AARCH64REG_WRITE_INLINE(sctlr_el1) 548 549 static const uintmax_t 550 SCTLR_RES0 = 0xc8222400, // Reserved ARMv8.0, write 0 551 SCTLR_RES1 = 0x30d00800, // Reserved ARMv8.0, write 1 552 SCTLR_M = __BIT(0), 553 SCTLR_A = __BIT(1), 554 SCTLR_C = __BIT(2), 555 SCTLR_SA = __BIT(3), 556 SCTLR_SA0 = __BIT(4), 557 SCTLR_CP15BEN = __BIT(5), 558 SCTLR_THEE = __BIT(6), 559 SCTLR_ITD = __BIT(7), 560 SCTLR_SED = __BIT(8), 561 SCTLR_UMA = __BIT(9), 562 SCTLR_I = __BIT(12), 563 SCTLR_DZE = __BIT(14), 564 SCTLR_UCT = __BIT(15), 565 SCTLR_nTWI = __BIT(16), 566 SCTLR_nTWE = __BIT(18), 567 SCTLR_WXN = __BIT(19), 568 SCTLR_IESB = __BIT(21), 569 SCTLR_SPAN = __BIT(23), 570 SCTLR_EOE = __BIT(24), 571 SCTLR_EE = __BIT(25), 572 SCTLR_UCI = __BIT(26), 573 SCTLR_nTLSMD = __BIT(28), 574 SCTLR_LSMAOE = __BIT(29); 575 576 // current EL stack pointer 577 static uint64_t inline 578 reg_sp_read(void) 579 { 580 uint64_t __rv; 581 __asm __volatile ("mov %0, sp" : "=r"(__rv)); 582 return __rv; 583 } 584 585 AARCH64REG_READ_INLINE(sp_el0) // EL0 Stack Pointer 586 AARCH64REG_WRITE_INLINE(sp_el0) 587 588 AARCH64REG_READ_INLINE(spsel) // Stack Pointer Select 589 AARCH64REG_WRITE_INLINE(spsel) 590 591 static const uintmax_t 592 SPSEL_SP = __BIT(0); // use SP_EL0 at all exception levels 593 594 AARCH64REG_READ_INLINE(spsr_el1) // Saved Program Status Register 595 AARCH64REG_WRITE_INLINE(spsr_el1) 596 597 static const uintmax_t 598 SPSR_NZCV = __BITS(31,28), // mask of N Z C V 599 SPSR_N = __BIT(31), // Negative 600 SPSR_Z = __BIT(30), // Zero 601 SPSR_C = __BIT(29), // Carry 602 SPSR_V = __BIT(28), // oVerflow 603 SPSR_A32_Q = __BIT(27), // A32: Overflow 604 SPSR_A32_J = __BIT(24), // A32: Jazelle Mode 605 SPSR_A32_IT1 = __BIT(23), // A32: IT[1] 606 SPSR_A32_IT0 = __BIT(22), // A32: IT[0] 607 SPSR_SS = __BIT(21), // Software Step 608 SPSR_IL = __BIT(20), // Instruction Length 609 SPSR_GE = __BITS(19,16), // A32: SIMD GE 610 SPSR_IT7 = __BIT(15), // A32: IT[7] 611 SPSR_IT6 = __BIT(14), // A32: IT[6] 612 SPSR_IT5 = __BIT(13), // A32: IT[5] 613 SPSR_IT4 = __BIT(12), // A32: IT[4] 614 SPSR_IT3 = __BIT(11), // A32: IT[3] 615 SPSR_IT2 = __BIT(10), // A32: IT[2] 616 SPSR_A64_D = __BIT(9), // A64: Debug Exception Mask 617 SPSR_A32_E = __BIT(9), // A32: BE Endian Mode 618 SPSR_A = __BIT(8), // Async abort (SError) Mask 619 SPSR_I = __BIT(7), // IRQ Mask 620 SPSR_F = __BIT(6), // FIQ Mask 621 SPSR_A32_T = __BIT(5), // A32 Thumb Mode 622 SPSR_M = __BITS(4,0), // Execution State 623 SPSR_M_EL3H = 0x0d, 624 SPSR_M_EL3T = 0x0c, 625 SPSR_M_EL2H = 0x09, 626 SPSR_M_EL2T = 0x08, 627 SPSR_M_EL1H = 0x05, 628 SPSR_M_EL1T = 0x04, 629 SPSR_M_EL0T = 0x00, 630 SPSR_M_SYS32 = 0x1f, 631 SPSR_M_UND32 = 0x1b, 632 SPSR_M_ABT32 = 0x17, 633 SPSR_M_SVC32 = 0x13, 634 SPSR_M_IRQ32 = 0x12, 635 SPSR_M_FIQ32 = 0x11, 636 SPSR_M_USR32 = 0x10; 637 638 AARCH64REG_READ_INLINE(tcr_el1) // Translation Control Register 639 AARCH64REG_WRITE_INLINE(tcr_el1) 640 641 #define TCR_PAGE_SIZE1(tcr) (1L << ((1L << __SHIFTOUT(tcr, TCR_TG1)) + 8)) 642 643 AARCH64REG_READ_INLINE(tpidr_el1) // Thread ID Register (EL1) 644 AARCH64REG_WRITE_INLINE(tpidr_el1) 645 646 AARCH64REG_WRITE_INLINE(tpidrro_el0) // Thread ID Register (RO for EL0) 647 648 AARCH64REG_READ_INLINE(ttbr0_el1) // Translation Table Base Register 0 EL1 649 AARCH64REG_WRITE_INLINE(ttbr0_el1) 650 651 AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1 652 AARCH64REG_WRITE_INLINE(ttbr1_el1) 653 654 AARCH64REG_READ_INLINE(vbar_el1) // Vector Base Address Register 655 AARCH64REG_WRITE_INLINE(vbar_el1) 656 657 /* 658 * From here on, these are DEBUG registers 659 */ 660 AARCH64REG_READ_INLINE(dbgbcr0_el1) // Debug Breakpoint Control Register 0 661 AARCH64REG_WRITE_INLINE(dbgbcr0_el1) 662 AARCH64REG_READ_INLINE(dbgbcr1_el1) // Debug Breakpoint Control Register 1 663 AARCH64REG_WRITE_INLINE(dbgbcr1_el1) 664 AARCH64REG_READ_INLINE(dbgbcr2_el1) // Debug Breakpoint Control Register 2 665 AARCH64REG_WRITE_INLINE(dbgbcr2_el1) 666 AARCH64REG_READ_INLINE(dbgbcr3_el1) // Debug Breakpoint Control Register 3 667 AARCH64REG_WRITE_INLINE(dbgbcr3_el1) 668 AARCH64REG_READ_INLINE(dbgbcr4_el1) // Debug Breakpoint Control Register 4 669 AARCH64REG_WRITE_INLINE(dbgbcr4_el1) 670 AARCH64REG_READ_INLINE(dbgbcr5_el1) // Debug Breakpoint Control Register 5 671 AARCH64REG_WRITE_INLINE(dbgbcr5_el1) 672 AARCH64REG_READ_INLINE(dbgbcr6_el1) // Debug Breakpoint Control Register 6 673 AARCH64REG_WRITE_INLINE(dbgbcr6_el1) 674 AARCH64REG_READ_INLINE(dbgbcr7_el1) // Debug Breakpoint Control Register 7 675 AARCH64REG_WRITE_INLINE(dbgbcr7_el1) 676 AARCH64REG_READ_INLINE(dbgbcr8_el1) // Debug Breakpoint Control Register 8 677 AARCH64REG_WRITE_INLINE(dbgbcr8_el1) 678 AARCH64REG_READ_INLINE(dbgbcr9_el1) // Debug Breakpoint Control Register 9 679 AARCH64REG_WRITE_INLINE(dbgbcr9_el1) 680 AARCH64REG_READ_INLINE(dbgbcr10_el1) // Debug Breakpoint Control Register 10 681 AARCH64REG_WRITE_INLINE(dbgbcr10_el1) 682 AARCH64REG_READ_INLINE(dbgbcr11_el1) // Debug Breakpoint Control Register 11 683 AARCH64REG_WRITE_INLINE(dbgbcr11_el1) 684 AARCH64REG_READ_INLINE(dbgbcr12_el1) // Debug Breakpoint Control Register 12 685 AARCH64REG_WRITE_INLINE(dbgbcr12_el1) 686 AARCH64REG_READ_INLINE(dbgbcr13_el1) // Debug Breakpoint Control Register 13 687 AARCH64REG_WRITE_INLINE(dbgbcr13_el1) 688 AARCH64REG_READ_INLINE(dbgbcr14_el1) // Debug Breakpoint Control Register 14 689 AARCH64REG_WRITE_INLINE(dbgbcr14_el1) 690 AARCH64REG_READ_INLINE(dbgbcr15_el1) // Debug Breakpoint Control Register 15 691 AARCH64REG_WRITE_INLINE(dbgbcr15_el1) 692 693 static const uintmax_t 694 DBGBCR_BT = __BITS(23,20), 695 DBGBCR_LBN = __BITS(19,16), 696 DBGBCR_SSC = __BITS(15,14), 697 DBGBCR_HMC = __BIT(13), 698 DBGBCR_BAS = __BITS(8,5), 699 DBGBCR_PMC = __BITS(2,1), 700 DBGBCR_E = __BIT(0); 701 702 AARCH64REG_READ_INLINE(dbgbvr0_el1) // Debug Breakpoint Value Register 0 703 AARCH64REG_WRITE_INLINE(dbgbvr0_el1) 704 AARCH64REG_READ_INLINE(dbgbvr1_el1) // Debug Breakpoint Value Register 1 705 AARCH64REG_WRITE_INLINE(dbgbvr1_el1) 706 AARCH64REG_READ_INLINE(dbgbvr2_el1) // Debug Breakpoint Value Register 2 707 AARCH64REG_WRITE_INLINE(dbgbvr2_el1) 708 AARCH64REG_READ_INLINE(dbgbvr3_el1) // Debug Breakpoint Value Register 3 709 AARCH64REG_WRITE_INLINE(dbgbvr3_el1) 710 AARCH64REG_READ_INLINE(dbgbvr4_el1) // Debug Breakpoint Value Register 4 711 AARCH64REG_WRITE_INLINE(dbgbvr4_el1) 712 AARCH64REG_READ_INLINE(dbgbvr5_el1) // Debug Breakpoint Value Register 5 713 AARCH64REG_WRITE_INLINE(dbgbvr5_el1) 714 AARCH64REG_READ_INLINE(dbgbvr6_el1) // Debug Breakpoint Value Register 6 715 AARCH64REG_WRITE_INLINE(dbgbvr6_el1) 716 AARCH64REG_READ_INLINE(dbgbvr7_el1) // Debug Breakpoint Value Register 7 717 AARCH64REG_WRITE_INLINE(dbgbvr7_el1) 718 AARCH64REG_READ_INLINE(dbgbvr8_el1) // Debug Breakpoint Value Register 8 719 AARCH64REG_WRITE_INLINE(dbgbvr8_el1) 720 AARCH64REG_READ_INLINE(dbgbvr9_el1) // Debug Breakpoint Value Register 9 721 AARCH64REG_WRITE_INLINE(dbgbvr9_el1) 722 AARCH64REG_READ_INLINE(dbgbvr10_el1) // Debug Breakpoint Value Register 10 723 AARCH64REG_WRITE_INLINE(dbgbvr10_el1) 724 AARCH64REG_READ_INLINE(dbgbvr11_el1) // Debug Breakpoint Value Register 11 725 AARCH64REG_WRITE_INLINE(dbgbvr11_el1) 726 AARCH64REG_READ_INLINE(dbgbvr12_el1) // Debug Breakpoint Value Register 12 727 AARCH64REG_WRITE_INLINE(dbgbvr12_el1) 728 AARCH64REG_READ_INLINE(dbgbvr13_el1) // Debug Breakpoint Value Register 13 729 AARCH64REG_WRITE_INLINE(dbgbvr13_el1) 730 AARCH64REG_READ_INLINE(dbgbvr14_el1) // Debug Breakpoint Value Register 14 731 AARCH64REG_WRITE_INLINE(dbgbvr14_el1) 732 AARCH64REG_READ_INLINE(dbgbvr15_el1) // Debug Breakpoint Value Register 15 733 AARCH64REG_WRITE_INLINE(dbgbvr15_el1) 734 735 AARCH64REG_READ_INLINE(dbgwcr0_el1) // Debug Watchpoint Control Register 0 736 AARCH64REG_WRITE_INLINE(dbgwcr0_el1) 737 AARCH64REG_READ_INLINE(dbgwcr1_el1) // Debug Watchpoint Control Register 1 738 AARCH64REG_WRITE_INLINE(dbgwcr1_el1) 739 AARCH64REG_READ_INLINE(dbgwcr2_el1) // Debug Watchpoint Control Register 2 740 AARCH64REG_WRITE_INLINE(dbgwcr2_el1) 741 AARCH64REG_READ_INLINE(dbgwcr3_el1) // Debug Watchpoint Control Register 3 742 AARCH64REG_WRITE_INLINE(dbgwcr3_el1) 743 AARCH64REG_READ_INLINE(dbgwcr4_el1) // Debug Watchpoint Control Register 4 744 AARCH64REG_WRITE_INLINE(dbgwcr4_el1) 745 AARCH64REG_READ_INLINE(dbgwcr5_el1) // Debug Watchpoint Control Register 5 746 AARCH64REG_WRITE_INLINE(dbgwcr5_el1) 747 AARCH64REG_READ_INLINE(dbgwcr6_el1) // Debug Watchpoint Control Register 6 748 AARCH64REG_WRITE_INLINE(dbgwcr6_el1) 749 AARCH64REG_READ_INLINE(dbgwcr7_el1) // Debug Watchpoint Control Register 7 750 AARCH64REG_WRITE_INLINE(dbgwcr7_el1) 751 AARCH64REG_READ_INLINE(dbgwcr8_el1) // Debug Watchpoint Control Register 8 752 AARCH64REG_WRITE_INLINE(dbgwcr8_el1) 753 AARCH64REG_READ_INLINE(dbgwcr9_el1) // Debug Watchpoint Control Register 9 754 AARCH64REG_WRITE_INLINE(dbgwcr9_el1) 755 AARCH64REG_READ_INLINE(dbgwcr10_el1) // Debug Watchpoint Control Register 10 756 AARCH64REG_WRITE_INLINE(dbgwcr10_el1) 757 AARCH64REG_READ_INLINE(dbgwcr11_el1) // Debug Watchpoint Control Register 11 758 AARCH64REG_WRITE_INLINE(dbgwcr11_el1) 759 AARCH64REG_READ_INLINE(dbgwcr12_el1) // Debug Watchpoint Control Register 12 760 AARCH64REG_WRITE_INLINE(dbgwcr12_el1) 761 AARCH64REG_READ_INLINE(dbgwcr13_el1) // Debug Watchpoint Control Register 13 762 AARCH64REG_WRITE_INLINE(dbgwcr13_el1) 763 AARCH64REG_READ_INLINE(dbgwcr14_el1) // Debug Watchpoint Control Register 14 764 AARCH64REG_WRITE_INLINE(dbgwcr14_el1) 765 AARCH64REG_READ_INLINE(dbgwcr15_el1) // Debug Watchpoint Control Register 15 766 AARCH64REG_WRITE_INLINE(dbgwcr15_el1) 767 768 static const uintmax_t 769 DBGWCR_MASK = __BITS(28,24), 770 DBGWCR_WT = __BIT(20), 771 DBGWCR_LBN = __BITS(19,16), 772 DBGWCR_SSC = __BITS(15,14), 773 DBGWCR_HMC = __BIT(13), 774 DBGWCR_BAS = __BITS(12,5), 775 DBGWCR_LSC = __BITS(4,3), 776 DBGWCR_PAC = __BITS(2,1), 777 DBGWCR_E = __BIT(0); 778 779 AARCH64REG_READ_INLINE(dbgwvr0_el1) // Debug Watchpoint Value Register 0 780 AARCH64REG_WRITE_INLINE(dbgwvr0_el1) 781 AARCH64REG_READ_INLINE(dbgwvr1_el1) // Debug Watchpoint Value Register 1 782 AARCH64REG_WRITE_INLINE(dbgwvr1_el1) 783 AARCH64REG_READ_INLINE(dbgwvr2_el1) // Debug Watchpoint Value Register 2 784 AARCH64REG_WRITE_INLINE(dbgwvr2_el1) 785 AARCH64REG_READ_INLINE(dbgwvr3_el1) // Debug Watchpoint Value Register 3 786 AARCH64REG_WRITE_INLINE(dbgwvr3_el1) 787 AARCH64REG_READ_INLINE(dbgwvr4_el1) // Debug Watchpoint Value Register 4 788 AARCH64REG_WRITE_INLINE(dbgwvr4_el1) 789 AARCH64REG_READ_INLINE(dbgwvr5_el1) // Debug Watchpoint Value Register 5 790 AARCH64REG_WRITE_INLINE(dbgwvr5_el1) 791 AARCH64REG_READ_INLINE(dbgwvr6_el1) // Debug Watchpoint Value Register 6 792 AARCH64REG_WRITE_INLINE(dbgwvr6_el1) 793 AARCH64REG_READ_INLINE(dbgwvr7_el1) // Debug Watchpoint Value Register 7 794 AARCH64REG_WRITE_INLINE(dbgwvr7_el1) 795 AARCH64REG_READ_INLINE(dbgwvr8_el1) // Debug Watchpoint Value Register 8 796 AARCH64REG_WRITE_INLINE(dbgwvr8_el1) 797 AARCH64REG_READ_INLINE(dbgwvr9_el1) // Debug Watchpoint Value Register 9 798 AARCH64REG_WRITE_INLINE(dbgwvr9_el1) 799 AARCH64REG_READ_INLINE(dbgwvr10_el1) // Debug Watchpoint Value Register 10 800 AARCH64REG_WRITE_INLINE(dbgwvr10_el1) 801 AARCH64REG_READ_INLINE(dbgwvr11_el1) // Debug Watchpoint Value Register 11 802 AARCH64REG_WRITE_INLINE(dbgwvr11_el1) 803 AARCH64REG_READ_INLINE(dbgwvr12_el1) // Debug Watchpoint Value Register 12 804 AARCH64REG_WRITE_INLINE(dbgwvr12_el1) 805 AARCH64REG_READ_INLINE(dbgwvr13_el1) // Debug Watchpoint Value Register 13 806 AARCH64REG_WRITE_INLINE(dbgwvr13_el1) 807 AARCH64REG_READ_INLINE(dbgwvr14_el1) // Debug Watchpoint Value Register 14 808 AARCH64REG_WRITE_INLINE(dbgwvr14_el1) 809 AARCH64REG_READ_INLINE(dbgwvr15_el1) // Debug Watchpoint Value Register 15 810 AARCH64REG_WRITE_INLINE(dbgwvr15_el1) 811 812 static const uintmax_t 813 DBGWVR_MASK = __BITS(64,3); 814 815 816 AARCH64REG_READ_INLINE(mdscr_el1) // Monitor Debug System Control Register 817 AARCH64REG_WRITE_INLINE(mdscr_el1) 818 819 AARCH64REG_WRITE_INLINE(oslar_el1) // OS Lock Access Register 820 821 AARCH64REG_READ_INLINE(oslsr_el1) // OS Lock Status Register 822 823 /* 824 * From here on, these are PMC registers 825 */ 826 827 AARCH64REG_READ_INLINE(pmccfiltr_el0) 828 AARCH64REG_WRITE_INLINE(pmccfiltr_el0) 829 830 static const uintmax_t 831 PMCCFILTR_P = __BIT(31), // Don't count cycles in EL1 832 PMCCFILTR_U = __BIT(30), // Don't count cycles in EL0 833 PMCCFILTR_NSK = __BIT(29), // Don't count cycles in NS EL1 834 PMCCFILTR_NSU = __BIT(28), // Don't count cycles in NS EL0 835 PMCCFILTR_NSH = __BIT(27), // Don't count cycles in NS EL2 836 PMCCFILTR_M = __BIT(26); // Don't count cycles in EL3 837 838 AARCH64REG_READ_INLINE(pmccntr_el0) 839 840 AARCH64REG_READ_INLINE(pmceid0_el0); 841 AARCH64REG_READ_INLINE(pmceid1_el0); 842 843 AARCH64REG_WRITE_INLINE(pmcntenclr_el0); 844 AARCH64REG_WRITE_INLINE(pmcntenset_el0); 845 846 AARCH64REG_READ_INLINE(pmcr_el0) 847 AARCH64REG_WRITE_INLINE(pmcr_el0) 848 849 static const uintmax_t 850 PMCR_IMP = __BITS(31,24), // Implementor code 851 PMCR_IDCODE = __BITS(23,16), // Identification code 852 PMCR_N = __BITS(15,11), // Number of event counters 853 PMCR_LC = __BIT(6), // Long cycle counter enable 854 PMCR_DP = __BIT(5), // Disable cycle counter when event 855 // counting is prohibited 856 PMCR_X = __BIT(4), // Enable export of events 857 PMCR_D = __BIT(3), // Clock divider 858 PMCR_C = __BIT(2), // Cycle counter reset 859 PMCR_P = __BIT(1), // Event counter reset 860 PMCR_E = __BIT(0); // Enable 861 862 863 AARCH64REG_READ_INLINE(pmevcntr1_el0); 864 AARCH64REG_WRITE_INLINE(pmevcntr1_el0); 865 866 AARCH64REG_READ_INLINE(pmevtyper1_el0) 867 AARCH64REG_WRITE_INLINE(pmevtyper1_el0) 868 869 static uintmax_t 870 PMEVTYPER_P = __BIT(31), // Don't count events in EL1 871 PMEVTYPER_U = __BIT(30), // Don't count events in EL0 872 PMEVTYPER_NSK = __BIT(29), // Don't count events in NS EL1 873 PMEVTYPER_NSU = __BIT(28), // Don't count events in NS EL0 874 PMEVTYPER_NSH = __BIT(27), // Count events in NS EL2 875 PMEVTYPER_M = __BIT(26), // Don't count events in EL3 876 PMEVTYPER_MT = __BIT(25), // Count events on all CPUs with same 877 // aff1 level 878 PMEVTYPER_EVTCOUNT = __BITS(15,0); // Event to count 879 880 AARCH64REG_WRITE_INLINE(pmintenclr_el1); 881 AARCH64REG_WRITE_INLINE(pmintenset_el1); 882 883 AARCH64REG_WRITE_INLINE(pmovsclr_el0); 884 AARCH64REG_READ_INLINE(pmovsset_el0); 885 AARCH64REG_WRITE_INLINE(pmovsset_el0); 886 887 AARCH64REG_WRITE_INLINE(pmselr_el0); 888 889 AARCH64REG_WRITE_INLINE(pmswinc_el0); 890 891 AARCH64REG_READ_INLINE(pmuserenr_el0); 892 AARCH64REG_WRITE_INLINE(pmuserenr_el0); 893 894 AARCH64REG_READ_INLINE(pmxevcntr_el0); 895 AARCH64REG_WRITE_INLINE(pmxevcntr_el0); 896 897 AARCH64REG_READ_INLINE(pmxevtyper_el0); 898 AARCH64REG_WRITE_INLINE(pmxevtyper_el0); 899 900 /* 901 * Generic timer registers 902 */ 903 904 AARCH64REG_READ_INLINE(cntfrq_el0) 905 906 AARCH64REG_READ_INLINE(cnthctl_el2) 907 AARCH64REG_WRITE_INLINE(cnthctl_el2) 908 909 static const uintmax_t 910 CNTHCTL_EVNTDIR = __BIT(3), 911 CNTHCTL_EVNTEN = __BIT(2), 912 CNTHCTL_EL1PCEN = __BIT(1), 913 CNTHCTL_EL1PCTEN = __BIT(0); 914 915 AARCH64REG_READ_INLINE(cntkctl_el1) 916 AARCH64REG_WRITE_INLINE(cntkctl_el1) 917 918 static const uintmax_t 919 CNTKCTL_EL0PTEN = __BIT(9), // EL0 access for CNTP CVAL/TVAL/CTL 920 CNTKCTL_PL0PTEN = CNTKCTL_EL0PTEN, 921 CNTKCTL_EL0VTEN = __BIT(8), // EL0 access for CNTV CVAL/TVAL/CTL 922 CNTKCTL_PL0VTEN = CNTKCTL_EL0VTEN, 923 CNTKCTL_ELNTI = __BITS(7,4), 924 CNTKCTL_EVNTDIR = __BIT(3), 925 CNTKCTL_EVNTEN = __BIT(2), 926 CNTKCTL_EL0VCTEN = __BIT(1), // EL0 access for CNTVCT and CNTFRQ 927 CNTKCTL_PL0VCTEN = CNTKCTL_EL0VCTEN, 928 CNTKCTL_EL0PCTEN = __BIT(0), // EL0 access for CNTPCT and CNTFRQ 929 CNTKCTL_PL0PCTEN = CNTKCTL_EL0PCTEN; 930 931 AARCH64REG_READ_INLINE(cntp_ctl_el0) 932 AARCH64REG_WRITE_INLINE(cntp_ctl_el0) 933 AARCH64REG_READ_INLINE(cntp_cval_el0) 934 AARCH64REG_WRITE_INLINE(cntp_cval_el0) 935 AARCH64REG_READ_INLINE(cntp_tval_el0) 936 AARCH64REG_WRITE_INLINE(cntp_tval_el0) 937 AARCH64REG_READ_INLINE(cntpct_el0) 938 AARCH64REG_WRITE_INLINE(cntpct_el0) 939 940 AARCH64REG_READ_INLINE(cntps_ctl_el1) 941 AARCH64REG_WRITE_INLINE(cntps_ctl_el1) 942 AARCH64REG_READ_INLINE(cntps_cval_el1) 943 AARCH64REG_WRITE_INLINE(cntps_cval_el1) 944 AARCH64REG_READ_INLINE(cntps_tval_el1) 945 AARCH64REG_WRITE_INLINE(cntps_tval_el1) 946 947 AARCH64REG_READ_INLINE(cntv_ctl_el0) 948 AARCH64REG_WRITE_INLINE(cntv_ctl_el0) 949 AARCH64REG_READ_INLINE(cntv_cval_el0) 950 AARCH64REG_WRITE_INLINE(cntv_cval_el0) 951 AARCH64REG_READ_INLINE(cntv_tval_el0) 952 AARCH64REG_WRITE_INLINE(cntv_tval_el0) 953 AARCH64REG_READ_INLINE(cntvct_el0) 954 AARCH64REG_WRITE_INLINE(cntvct_el0) 955 956 static const uintmax_t 957 CNTCTL_ISTATUS = __BIT(2), // Interrupt Asserted 958 CNTCTL_IMASK = __BIT(1), // Timer Interrupt is Masked 959 CNTCTL_ENABLE = __BIT(0); // Timer Enabled 960 961 962 // ID_AA64PFR0_EL1: AArch64 Processor Feature Register 0 963 static const uintmax_t 964 ID_AA64PFR0_EL1_GIC = __BITS(24,27), // GIC CPU IF 965 ID_AA64PFR0_EL1_GIC_SHIFT = 24, 966 ID_AA64PFR0_EL1_GIC_CPUIF_EN = 1, 967 ID_AA64PFR0_EL1_GIC_CPUIF_NONE = 0, 968 ID_AA64PFR0_EL1_ADVSIMD = __BITS(23,20), // SIMD 969 ID_AA64PFR0_EL1_ADV_SIMD_IMPL = 0x0, 970 ID_AA64PFR0_EL1_ADV_SIMD_NONE = 0xf, 971 ID_AA64PFR0_EL1_FP = __BITS(19,16), // FP 972 ID_AA64PFR0_EL1_FP_IMPL = 0x0, 973 ID_AA64PFR0_EL1_FP_NONE = 0xf, 974 ID_AA64PFR0_EL1_EL3 = __BITS(15,12), // EL3 handling 975 ID_AA64PFR0_EL1_EL3_NONE = 0, 976 ID_AA64PFR0_EL1_EL3_64 = 1, 977 ID_AA64PFR0_EL1_EL3_64_32 = 2, 978 ID_AA64PFR0_EL1_EL2 = __BITS(11,8), // EL2 handling 979 ID_AA64PFR0_EL1_EL2_NONE = 0, 980 ID_AA64PFR0_EL1_EL2_64 = 1, 981 ID_AA64PFR0_EL1_EL2_64_32 = 2, 982 ID_AA64PFR0_EL1_EL1 = __BITS(7,4), // EL1 handling 983 ID_AA64PFR0_EL1_EL1_64 = 1, 984 ID_AA64PFR0_EL1_EL1_64_32 = 2, 985 ID_AA64PFR0_EL1_EL0 = __BITS(3,0), // EL0 handling 986 ID_AA64PFR0_EL1_EL0_64 = 1, 987 ID_AA64PFR0_EL1_EL0_64_32 = 2; 988 989 // ICC_SRE_EL1: Interrupt Controller System Register Enable register 990 static const uintmax_t 991 ICC_SRE_EL1_SRE = __BIT(0), 992 ICC_SRE_EL1_DFB = __BIT(1), 993 ICC_SRE_EL1_DIB = __BIT(2); 994 995 // ICC_SRE_EL2: Interrupt Controller System Register Enable register 996 static const uintmax_t 997 ICC_SRE_EL2_SRE = __BIT(0), 998 ICC_SRE_EL2_DFB = __BIT(1), 999 ICC_SRE_EL2_DIB = __BIT(2), 1000 ICC_SRE_EL2_EN = __BIT(3); 1001 1002 1003 /* 1004 * GENERIC TIMER REGISTER ACCESS 1005 */ 1006 static inline uint32_t 1007 gtmr_cntfrq_read(void) 1008 { 1009 1010 return reg_cntfrq_el0_read(); 1011 } 1012 1013 static inline uint32_t 1014 gtmr_cntk_ctl_read(void) 1015 { 1016 1017 return reg_cntkctl_el1_read(); 1018 } 1019 1020 static inline void 1021 gtmr_cntk_ctl_write(uint32_t val) 1022 { 1023 1024 reg_cntkctl_el1_write(val); 1025 } 1026 1027 /* 1028 * Counter-timer Virtual Count timer 1029 */ 1030 static inline uint64_t 1031 gtmr_cntpct_read(void) 1032 { 1033 1034 return reg_cntpct_el0_read(); 1035 } 1036 1037 static inline uint64_t 1038 gtmr_cntvct_read(void) 1039 { 1040 1041 return reg_cntvct_el0_read(); 1042 } 1043 1044 /* 1045 * Counter-timer Virtual Timer Control register 1046 */ 1047 static inline uint32_t 1048 gtmr_cntv_ctl_read(void) 1049 { 1050 1051 return reg_cntv_ctl_el0_read(); 1052 } 1053 1054 static inline void 1055 gtmr_cntv_ctl_write(uint32_t val) 1056 { 1057 1058 reg_cntv_ctl_el0_write(val); 1059 } 1060 1061 static inline void 1062 gtmr_cntp_ctl_write(uint32_t val) 1063 { 1064 1065 1066 reg_cntp_ctl_el0_write(val); 1067 } 1068 1069 /* 1070 * Counter-timer Virtual Timer TimerValue register 1071 */ 1072 static inline uint32_t 1073 gtmr_cntv_tval_read(void) 1074 { 1075 1076 return reg_cntv_tval_el0_read(); 1077 } 1078 1079 static inline void 1080 gtmr_cntv_tval_write(uint32_t val) 1081 { 1082 1083 reg_cntv_tval_el0_write(val); 1084 } 1085 1086 1087 /* 1088 * Counter-timer Virtual Timer CompareValue register 1089 */ 1090 static inline uint64_t 1091 gtmr_cntv_cval_read(void) 1092 { 1093 1094 return reg_cntv_cval_el0_read(); 1095 } 1096 1097 #endif /* _AARCH64_ARMREG_H_ */ 1098
Indexes created Thu Oct 02 14:10:14 GMT 2025