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History log of /src/sys/arch/aarch64/include/armreg.h
RevisionDateAuthorComments
 1.71  23-Aug-2025  skrll Add a #define for the RES1 bits (just bit 31) in MPIDR_EL1.
 1.70  12-Aug-2025  skrll Add MDCR_EL2 accessors and bit definitions.
 1.69  12-Aug-2025  skrll Add sp_el2 accessors.
 1.68  12-Aug-2025  skrll Remove the XXXNH I had against ESR_EC_LS64.

The FEAT_LS64 instructions are all A64.
 1.67  27-Feb-2025  andvar Fix various typos in comments.
 1.66  03-Jan-2024  andvar branches: 1.66.2;
ddress->address in comment.
 1.65  24-Sep-2023  skrll Add a bunch of system registers and their bit / bit field definitions.
Taken from ryo's nvmm branch with updates from me.
 1.64  06-May-2023  andvar s/Regiser/Register/ and s/regester/register/ in comments.
 1.63  01-Dec-2022  ryo Improve tprof(4)

- Multiple events can now be handled simultaneously.
- Counters should be configured with TPROF_IOC_CONFIGURE_EVENT in advance,
instead of being configured at TPROF_IOC_START.
- The configured counters can be started and stopped repeatedly by
PROF_IOC_START/TPROF_IOC_STOP.
- The value of the performance counter can be obtained at any timing as a 64bit
value with TPROF_IOC_GETCOUNTS.
- Backend common parts are handled in tprof.c as much as possible, and functions
on the tprof_backend side have been reimplemented to be more primitive.
- The reset value of counter overflows for profiling can now be adjusted.
It is calculated by default from the CPU clock (speed of cycle counter) and
TPROF_HZ, but for some events the value may be too large to be sufficient for
profiling. The event counter can be specified as a ratio to the default or as
an absolute value when configuring the event counter.
- Due to overall changes, API and ABI have been changed. TPROF_VERSION and
TPROF_BACKEND_VERSION were updated.
 1.62  01-Dec-2022  ryo PMCR.E should not be disabled from tprof.

PMCR.E controls not only performance event counters but also the cycle
counter operation, and the cycle counter may be used for cpu_counter.
Similarly, the 31st bit in PMINTENCLR and PMCNTENCLR controls the cycle
counter, not performance event counters, and should not be modified.
 1.61  02-May-2022  skrll Only print the appropriate PAR fields for PAR.F={0,1}

Group the fields in the header.
 1.60  05-Jan-2022  ryo fix ID_AA64ISAR0_EL1.ATOMIC field definition
 1.59  26-Oct-2021  ryo fix build with COPTS=-O0
 1.58  23-Oct-2021  skrll Typo in comment
 1.57  19-Jun-2021  jmcneill Do not try to initialize PMU if ID_AA64DFR0_EL1 reports a non-standard
PMU implementation.
 1.56  19-Jun-2021  jmcneill CNTV_CTL_EL0 is a 64-bit register
 1.55  09-Mar-2021  ryo branches: 1.55.4;
fixed mask width of DBGWVR_MASK, and added definition of DBGBVR_MASK
 1.54  30-Sep-2020  ryo branches: 1.54.2;
add some fields of ID_AA64ISAR1_EL1 definition (ARMv8.6)
 1.53  15-Sep-2020  ryo fix typo
 1.52  02-Aug-2020  maxv Add support for Privileged Access Never (ARMv8.1-PAN).

PAN provides the same functionality as SMAP on x86: it forbids kernel
access to userland pages when PSTATE.PAN=1, and allows such accesses when
PSTATE.PAN=0.

We clear SCTLR_SPAN, to guarantee that PAN=1 each time the kernel is
entered. We catch PAN faults and panic right away without further
processing. In copyin, copyout, etc, we temporarily authorize access to
userland pages.

PAN is a very useful exploit mitigation. Reviewed by ryo@, thanks. Tested
on Qemu. Enabled by default.
 1.51  01-Aug-2020  maxv The system registers we modify can have an impact on memory accesses, and
we don't want the compiler to randomly re-order the instructions, so add
barriers. Same as WRMSR on x86.
 1.50  01-Jul-2020  ryo - On some systems with a different cache line size (and DIC,IDC) per CPU, trap "mrs Xt,ctr_el0" instruction
to return the minimum cache line size of the system to userland.
- add CLIDR_EL1 and CTR_EL0 to struct aarch64_sysctl_cpu_id.

On most systems, cache line size is the same for all CPUs, so this mechanism won't be required.
Rather, this is primarily for errata support, which will be committed later.
 1.49  14-Jun-2020  riastradh Add some more id_aa64pfr0_el1 bits.
 1.48  28-May-2020  skrll Add some new CTR_EL0 bits
 1.47  25-May-2020  ryo add ARMv8.1-8.5 definitions of TCR_EL1
 1.46  25-May-2020  ryo cache information can be detected correctly on newer CPUs

- add VPIPT cache type
- adapt to 64-bit CCSIDR (ARMv8.3-CCIDX)
- CCSIDR:[WT,WB,PA,WA] are deprecated
- show number of cache lines when attaching cpu
 1.45  23-May-2020  ryo Not only the kernel thread, but also the userland PAC keys
(APIA,APIB,APDA,APDB,APGA) are now randomly initialized at exec, and switched
when context switch.
userland programs are able to perform pointer authentication on ARMv8.3+PAC cpu.

reviewd by maxv@, thanks.
 1.44  21-May-2020  ryo fix typo
 1.43  13-May-2020  ryo - move aarch64 addressspace macros from pmap.h to cpufunc.h
- rename ptr_strip_pac() to aarch64_strip_pac()
 1.42  11-May-2020  ryo "options ARMV83_PAC" is now supported for gcc as well.

- add "-msign-return-address=all" to CFLAGS for gcc when specified options ARMV83_PAC
- AARCH64REG_{READ,WRITE}_INLINE3 macro can now use the APIAKey registers in both gcc and llvm.
llvm requires asm(".arch armv8.3-a"), whereas gcc requires __attribute__((target("arch=armv8.3-a"))).
- use ".arch armv8.3-a" rather than ".arch armv8.3-a+pac" in *.S for llvm.
 1.41  10-May-2020  riastradh Fix ID_AA64ISAR0_EL1_RNDR field definition for RNDR support.

ARMv8.5 ARM, p. D13-3232
 1.40  12-Apr-2020  maxv Add support for Pointer Authentication (PAC).

We use the "pac-ret" option, to sign the return instruction pointer on
function entry, and authenticate it on function exit. This acts as a
mitigation against ROP.

The authentication uses a per-lwp (secret) I-A key stored in the 128bit
APIAKey register and part of the lwp context. During lwp creation, the
kernel generates a random key, and during context switches, it installs
the key of the target lwp on the CPU.

Userland cannot read the APIAKey register directly. However, it can sign
its pointers with it, because the register is architecturally shared
between userland and the kernel. Although part of the CPU design, it is
a bit of an undesired behavior, because it allows to forge valid kernel
pointers from userland. To avoid that, we don't share the key with
userland, and rather switch it in EL0<->EL1 transitions. This means that
when userland executes, a different key is loaded in APIAKey than the one
the kernel uses. For now the userland key is a fixed 128bit zero value.

The DDB stack unwinder is changed to strip the authentication code from
the pointers in lr.

Two problems are known:

* Currently the idlelwps' keys are not really secret. This is because
the RNG is not yet available when we spawn these lwps. Not overly
important, but would be nice to fix with UEFI RNG.
* The key switching in EL0<->EL1 transitions is not the most optimized
code on the planet. Instead of checking aarch64_pac_enabled, it would
be better to hot-patch the code at boot time, but there currently is
no hot-patch support on aarch64.

Tested on Qemu.
 1.39  30-Mar-2020  jmcneill branches: 1.39.2;
Enable the cycle counter when a CPU hatches and store an estimate of the
frequency in ci_data.cpu_cc_freq.
 1.38  06-Mar-2020  ryo fix missing paren
 1.37  06-Mar-2020  ryo add more definitions for ARMv8.1-ARMv8.4
 1.36  29-Feb-2020  ryo widen bit PAR_EL1.PAR_PA from [47:12] to [51:12] for ARMv8.2 (and later).

PAR_EL1:[51:48] is RES0 in ARMv8.1 and ARMv8.0.
 1.35  31-Jan-2020  maxv BTI definitions.
 1.34  28-Jan-2020  maxv More SCTLR.
 1.33  28-Jan-2020  maxv Fetch ID_AA64MMFR2_EL1. Okayed by Nick the other day.
 1.32  28-Jan-2020  maxv Jazelle and T32EE are not part of ARMv8, fix the bits to their real
meanings. No functional change.
 1.31  28-Jan-2020  maxv More definitions.
 1.30  28-Dec-2019  rjs branches: 1.30.2;
s/Memroy/Memory/ in comment.
 1.29  27-Dec-2019  jmcneill Enable early write acknowledge for device memory mappings.
 1.28  15-Sep-2019  tnn report A72 errata #859971 workaround status during boot
 1.27  11-Sep-2019  skrll Move the TCR and TTBR defines into armreg.h where they below. NFCI.
 1.26  12-Aug-2019  jmcneill Add support for physical timers and sprinkle isb where needed.
 1.25  16-Jun-2019  skrll branches: 1.25.2;
Provide icc_pmr_read
 1.24  20-Mar-2019  ryo - add reg_{s1e0r,s1e0w,s1e1r,s1e1w}_write() macro.
- show the result of AT insn at ddb "machine pte" command.
 1.23  30-Jan-2019  jmcneill add gtmr_cntv_cval_write
 1.22  13-Dec-2018  ryo add support PT_STEP
 1.21  20-Nov-2018  mrg rewrite the CPU identification on arm64:

- publish per-cpu data
- publish a whole bunch of info in struct aarch64_sysctl_cpu_id
instead of various individual nodes (there are 16 total.)
- add MIDR extractor bits
- define ARMv8.2-A id_aa64mmfr2_el1 and id_aa64zfr0_el1 regs,
but avoid using them until we make sure they exist. (these
members are added to aarch64_sysctl_cpu_id to avoid future
compat issues.)

the arm32 and aarch32 version of these need to be adjusted as
well (and aarch32 data published at all.) still trying to
work out how to make the same userland binary running on a
real arm32 or an aarch32 system can work sanely here.

ok ryo@.
 1.20  07-Nov-2018  riastradh When hardware subnormal support is available, disable flush-to-zero.

Similarly, when hardware NaN propagation is available, disable
default-NaN substitution.

This enables IEEE 754 semantics on any hardware that supports it by
default. Programs that want flush-to-zero or default-NaN substitution
can enable them explicitly.

ok ryo@
 1.19  12-Oct-2018  ryo add initial support of COMPAT_NETBSD32 on AArch64.
arm ELF32 EABI binaries could be execute in AArch32 state on AArch64. A32 THUMB mode is not supported yet.
 1.18  12-Aug-2018  skrll Provide and use cpu_mpidr_aff_read in psci_fdt_bootstrap
 1.17  12-Aug-2018  skrll Whitespace
 1.16  09-Aug-2018  jmcneill Restore ICC_SRE_EL2 registers lost in previous commit
 1.15  08-Aug-2018  jmcneill Add GICv3 system registers
 1.14  05-Aug-2018  skrll More whitespace
 1.13  01-Aug-2018  skrll Some whitespace improvements. NFC.
 1.12  17-Jul-2018  christos - use #define to define constants instead of static const variables so that
gcc can compile the code.
- fix position of inline, and use __inline
 1.11  15-Jul-2018  jmcneill Add more PMC registers
 1.10  14-May-2018  joerg branches: 1.10.2;
Workaround A-008585 errata in GTMR.

Register reads and writes may provide unstable results if the counter
hardware is active at the same time. This results in non-monotonic
counters seen by both the gtmr interrupt and time counter.

The loops are currently applied unconditionally, restricting them to
appropiate FDT markers can be applied later.
 1.9  01-Apr-2018  ryo Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)

- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)
 1.8  20-Mar-2018  ryo separate cputypes.h for CPU_ID_* from armreg.h,
and add some implementor IDs, CortexA55,73,75 IDs.

(preliminary changes for merging aarch64)
 1.7  06-Mar-2018  skrll Sprinkle __volatile on asm instructions
 1.6  06-Mar-2018  skrll Convert decimal to hex to make comparison to arm arm (slightly) easier.
 1.5  06-Mar-2018  skrll Another harmless typo
 1.4  06-Mar-2018  skrll Fix harmless typo
 1.3  20-Dec-2017  skrll branches: 1.3.2;
Trailing whitespace
 1.2  27-Apr-2015  skrll ARM spells the System Control Register SCTLR
 1.1  10-Aug-2014  matt branches: 1.1.4; 1.1.6;
Preliminary files for AARCH64 (64-bit ARM) support.
Enough for a distribution build.
 1.1.6.1  06-Jun-2015  skrll Sync with HEAD
 1.1.4.3  03-Dec-2017  jdolecek update from HEAD
 1.1.4.2  20-Aug-2014  tls Rebase to HEAD as of a few days ago.
 1.1.4.1  10-Aug-2014  tls file armreg.h was added on branch tls-maxphys on 2014-08-20 00:02:39 +0000
 1.3.2.9  26-Dec-2018  pgoyette Sync with HEAD, resolve a few conflicts
 1.3.2.8  26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.3.2.7  20-Oct-2018  pgoyette Sync with head
 1.3.2.6  06-Sep-2018  pgoyette Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)
 1.3.2.5  28-Jul-2018  pgoyette Sync with HEAD
 1.3.2.4  21-May-2018  pgoyette Sync with HEAD
 1.3.2.3  07-Apr-2018  pgoyette Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
 1.3.2.2  22-Mar-2018  pgoyette Synch with HEAD, resolve conflicts
 1.3.2.1  15-Mar-2018  pgoyette Synch with HEAD
 1.10.2.3  21-Apr-2020  martin Sync with HEAD
 1.10.2.2  13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.10.2.1  10-Jun-2019  christos Sync with HEAD
 1.25.2.2  29-Dec-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #586):

sys/arch/arm/nvidia/tegra_pcie.c: revision 1.27
sys/arch/aarch64/aarch64/pmap.c: revision 1.57
sys/arch/aarch64/aarch64/locore.S: revision 1.48
sys/arch/aarch64/include/armreg.h: revision 1.29
sys/arch/aarch64/aarch64/pmap.c: revision 1.58
sys/arch/aarch64/aarch64/locore.S: revision 1.49
sys/arch/arm/acpi/acpipchb.c: revision 1.14
sys/arch/aarch64/aarch64/genassym.cf: revision 1.16
sys/arch/arm/acpi/acpi_machdep.c: revision 1.13
sys/arch/aarch64/include/pmap.h: revision 1.27
sys/arch/aarch64/aarch64/genassym.cf: revision 1.17
sys/arch/aarch64/include/pmap.h: revision 1.28
sys/arch/arm/fdt/pcihost_fdtvar.h: revision 1.3
sys/arch/arm/include/bus_defs.h: revision 1.14
sys/arch/aarch64/aarch64/bus_space.c: revision 1.9
sys/arch/arm/fdt/pcihost_fdt.c: revision 1.12
sys/arch/aarch64/conf/files.aarch64: revision 1.15
sys/arch/aarch64/conf/files.aarch64: revision 1.16
sys/arch/arm/rockchip/rk3399_pcie.c: revision 1.9

Enable early write acknowledge for device memory mappings.

Do not use Early Write Acknowledge for PCIe I/O and config space.
 1.25.2.1  13-Aug-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #54):

sys/arch/aarch64/include/armreg.h: revision 1.26
sys/arch/arm/cortex/gtmr.c: revision 1.41
sys/arch/arm/include/armreg.h: revision 1.128
sys/arch/arm/cortex/gtmr_var.h: revision 1.12

Add support for physical timers and sprinkle isb where needed.
 1.30.2.1  29-Feb-2020  ad Sync with head.
 1.39.2.1  20-Apr-2020  bouyer Sync with HEAD
 1.54.2.1  03-Apr-2021  thorpej Sync with HEAD.
 1.55.4.1  01-Aug-2021  thorpej Sync with HEAD.
 1.66.2.1  02-Aug-2025  perseant Sync with HEAD

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