armreg.h revision 1.14
1 /* $NetBSD: armreg.h,v 1.14 2018/08/05 07:49:02 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _AARCH64_ARMREG_H_ 33 #define _AARCH64_ARMREG_H_ 34 35 #include <arm/cputypes.h> 36 #include <sys/types.h> 37 38 #define AARCH64REG_READ_INLINE2(regname, regdesc) \ 39 static __inline uint64_t \ 40 reg_##regname##_read(void) \ 41 { \ 42 uint64_t __rv; \ 43 __asm __volatile("mrs %0, " #regdesc : "=r"(__rv)); \ 44 return __rv; \ 45 } 46 47 #define AARCH64REG_WRITE_INLINE2(regname, regdesc) \ 48 static __inline void \ 49 reg_##regname##_write(uint64_t __val) \ 50 { \ 51 __asm __volatile("msr " #regdesc ", %0" :: "r"(__val)); \ 52 } 53 54 #define AARCH64REG_WRITEIMM_INLINE2(regname, regdesc) \ 55 static __inline void \ 56 reg_##regname##_write(uint64_t __val) \ 57 { \ 58 __asm __volatile("msr " #regdesc ", %0" :: "n"(__val)); \ 59 } 60 61 #define AARCH64REG_READ_INLINE(regname) \ 62 AARCH64REG_READ_INLINE2(regname, regname) 63 64 #define AARCH64REG_WRITE_INLINE(regname) \ 65 AARCH64REG_WRITE_INLINE2(regname, regname) 66 67 #define AARCH64REG_WRITEIMM_INLINE(regname) \ 68 AARCH64REG_WRITEIMM_INLINE2(regname, regname) 69 /* 70 * System registers available at EL0 (user) 71 */ 72 AARCH64REG_READ_INLINE(ctr_el0) // Cache Type Register 73 74 #define CTR_EL0_CWG_LINE __BITS(27,24) // Cacheback Writeback Granule 75 #define CTR_EL0_ERG_LINE __BITS(23,20) // Exclusives Reservation Granule 76 #define CTR_EL0_DMIN_LINE __BITS(19,16) // Dcache MIN LINE size (log2 - 2) 77 #define CTR_EL0_L1IP_MASK __BITS(15,14) 78 #define CTR_EL0_L1IP_AIVIVT 1 // ASID-tagged Virtual Index, Virtual Tag 79 #define CTR_EL0_L1IP_VIPT 2 // Virtual Index, Physical Tag 80 #define CTR_EL0_L1IP_PIPT 3 // Physical Index, Physical Tag 81 #define CTR_EL0_IMIN_LINE __BITS(3,0) // Icache MIN LINE size (log2 - 2) 82 83 AARCH64REG_READ_INLINE(dczid_el0) // Data Cache Zero ID Register 84 85 #define DCZID_DZP __BIT(4) // Data Zero Prohibited 86 #define DCZID_BS __BITS(3,0) // Block Size (log2 - 2) 87 88 AARCH64REG_READ_INLINE(fpcr) // Floating Point Control Register 89 AARCH64REG_WRITE_INLINE(fpcr) 90 91 #define FPCR_AHP __BIT(26) // Alternative Half Precision 92 #define FPCR_DN __BIT(25) // Default Nan Control 93 #define FPCR_FZ __BIT(24) // Flush-To-Zero 94 #define FPCR_RMODE __BITS(23,22) // Rounding Mode 95 #define FPCR_RN 0 // Round Nearest 96 #define FPCR_RP 1 // Round towards Plus infinity 97 #define FPCR_RM 2 // Round towards Minus infinity 98 #define FPCR_RZ 3 // Round towards Zero 99 #define FPCR_STRIDE __BITS(21,20) 100 #define FPCR_LEN __BITS(18,16) 101 #define FPCR_IDE __BIT(15) // Input Denormal Exception enable 102 #define FPCR_IXE __BIT(12) // IneXact Exception enable 103 #define FPCR_UFE __BIT(11) // UnderFlow Exception enable 104 #define FPCR_OFE __BIT(10) // OverFlow Exception enable 105 #define FPCR_DZE __BIT(9) // Divide by Zero Exception enable 106 #define FPCR_IOE __BIT(8) // Invalid Operation Exception enable 107 #define FPCR_ESUM 0x1F00 108 109 AARCH64REG_READ_INLINE(fpsr) // Floating Point Status Register 110 AARCH64REG_WRITE_INLINE(fpsr) 111 112 #define FPSR_N32 __BIT(31) // AARCH32 Negative 113 #define FPSR_Z32 __BIT(30) // AARCH32 Zero 114 #define FPSR_C32 __BIT(29) // AARCH32 Carry 115 #define FPSR_V32 __BIT(28) // AARCH32 Overflow 116 #define FPSR_QC __BIT(27) // SIMD Saturation 117 #define FPSR_IDC __BIT(7) // Input Denormal Cumulative status 118 #define FPSR_IXC __BIT(4) // IneXact Cumulative status 119 #define FPSR_UFC __BIT(3) // UnderFlow Cumulative status 120 #define FPSR_OFC __BIT(2) // OverFlow Cumulative status 121 #define FPSR_DZC __BIT(1) // Divide by Zero Cumulative status 122 #define FPSR_IOC __BIT(0) // Invalid Operation Cumulative status 123 #define FPSR_CSUM 0x1F 124 125 AARCH64REG_READ_INLINE(nzcv) // condition codes 126 AARCH64REG_WRITE_INLINE(nzcv) 127 128 #define NZCV_N __BIT(31) // Negative 129 #define NZCV_Z __BIT(30) // Zero 130 #define NZCV_C __BIT(29) // Carry 131 #define NZCV_V __BIT(28) // Overflow 132 133 AARCH64REG_READ_INLINE(tpidr_el0) // Thread Pointer ID Register (RW) 134 AARCH64REG_WRITE_INLINE(tpidr_el0) 135 136 AARCH64REG_READ_INLINE(tpidrro_el0) // Thread Pointer ID Register (RO) 137 138 /* 139 * From here on, these can only be accessed at EL1 (kernel) 140 */ 141 142 /* 143 * These are readonly registers 144 */ 145 AARCH64REG_READ_INLINE(aidr_el1) 146 147 AARCH64REG_READ_INLINE2(cbar_el1, s3_1_c15_c3_0) // Cortex-A57 148 149 #define CBAR_PA __BITS(47,18) 150 151 AARCH64REG_READ_INLINE(ccsidr_el1) 152 153 #define CCSIDR_WT __BIT(31) // Write-through supported 154 #define CCSIDR_WB __BIT(30) // Write-back supported 155 #define CCSIDR_RA __BIT(29) // Read-allocation supported 156 #define CCSIDR_WA __BIT(28) // Write-allocation supported 157 #define CCSIDR_NUMSET __BITS(27,13) // (Number of sets in cache) - 1 158 #define CCSIDR_ASSOC __BITS(12,3) // (Associativity of cache) - 1 159 #define CCSIDR_LINESIZE __BITS(2,0) // Number of bytes in cache line 160 161 AARCH64REG_READ_INLINE(clidr_el1) 162 163 #define CLIDR_LOUU __BITS(29,27) // Level of Unification Uniprocessor 164 #define CLIDR_LOC __BITS(26,24) // Level of Coherency 165 #define CLIDR_LOUIS __BITS(23,21) // Level of Unification InnerShareable*/ 166 #define CLIDR_CTYPE7 __BITS(20,18) // Cache Type field for level7 167 #define CLIDR_CTYPE6 __BITS(17,15) // Cache Type field for level6 168 #define CLIDR_CTYPE5 __BITS(14,12) // Cache Type field for level5 169 #define CLIDR_CTYPE4 __BITS(11,9) // Cache Type field for level4 170 #define CLIDR_CTYPE3 __BITS(8,6) // Cache Type field for level3 171 #define CLIDR_CTYPE2 __BITS(5,3) // Cache Type field for level2 172 #define CLIDR_CTYPE1 __BITS(2,0) // Cache Type field for level1 173 #define CLIDR_TYPE_NOCACHE 0 // No cache 174 #define CLIDR_TYPE_ICACHE 1 // Instruction cache only 175 #define CLIDR_TYPE_DCACHE 2 // Data cache only 176 #define CLIDR_TYPE_IDCACHE 3 // Separate inst and data caches 177 #define CLIDR_TYPE_UNIFIEDCACHE 4 // Unified cache 178 179 AARCH64REG_READ_INLINE(currentel) 180 AARCH64REG_READ_INLINE(id_aa64afr0_el1) 181 AARCH64REG_READ_INLINE(id_aa64afr1_el1) 182 AARCH64REG_READ_INLINE(id_aa64dfr0_el1) 183 184 #define ID_AA64DFR0_EL1_CTX_CMPS __BITS(31,28) 185 #define ID_AA64DFR0_EL1_WRPS __BITS(20,23) 186 #define ID_AA64DFR0_EL1_BRPS __BITS(12,15) 187 #define ID_AA64DFR0_EL1_PMUVER __BITS(8,11) 188 #define ID_AA64DFR0_EL1_PMUVER_NONE 0 189 #define ID_AA64DFR0_EL1_PMUVER_V3 1 190 #define ID_AA64DFR0_EL1_PMUVER_NOV3 2 191 #define ID_AA64DFR0_EL1_TRACEVER __BITS(4,7) 192 #define ID_AA64DFR0_EL1_TRACEVER_NONE 0 193 #define ID_AA64DFR0_EL1_TRACEVER_IMPL 1 194 #define ID_AA64DFR0_EL1_DEBUGVER __BITS(0,3) 195 #define ID_AA64DFR0_EL1_DEBUGVER_V8A 6 196 197 AARCH64REG_READ_INLINE(id_aa64dfr1_el1) 198 199 AARCH64REG_READ_INLINE(id_aa64isar0_el1) 200 201 #define ID_AA64ISAR0_EL1_CRC32 __BITS(19,16) 202 #define ID_AA64ISAR0_EL1_CRC32_NONE 0 203 #define ID_AA64ISAR0_EL1_CRC32_CRC32X 1 204 #define ID_AA64ISAR0_EL1_SHA2 __BITS(15,12) 205 #define ID_AA64ISAR0_EL1_SHA2_NONE 0 206 #define ID_AA64ISAR0_EL1_SHA2_SHA256HSU 1 207 #define ID_AA64ISAR0_EL1_SHA1 __BITS(11,8) 208 #define ID_AA64ISAR0_EL1_SHA1_NONE 0 209 #define ID_AA64ISAR0_EL1_SHA1_SHA1CPMHSU 1 210 #define ID_AA64ISAR0_EL1_AES __BITS(7,4) 211 #define ID_AA64ISAR0_EL1_AES_NONE 0 212 #define ID_AA64ISAR0_EL1_AES_AES 1 213 #define ID_AA64ISAR0_EL1_AES_PMUL 2 214 215 AARCH64REG_READ_INLINE(id_aa64isar1_el1) 216 AARCH64REG_READ_INLINE(id_aa64mmfr0_el1) 217 218 #define ID_AA64MMFR0_EL1_TGRAN4 __BITS(31,28) 219 #define ID_AA64MMFR0_EL1_TGRAN4_4KB 0 220 #define ID_AA64MMFR0_EL1_TGRAN4_NONE 15 221 #define ID_AA64MMFR0_EL1_TGRAN64 __BITS(24,27) 222 #define ID_AA64MMFR0_EL1_TGRAN64_64KB 0 223 #define ID_AA64MMFR0_EL1_TGRAN64_NONE 15 224 #define ID_AA64MMFR0_EL1_TGRAN16 __BITS(20,23) 225 #define ID_AA64MMFR0_EL1_TGRAN16_NONE 0 226 #define ID_AA64MMFR0_EL1_TGRAN16_16KB 1 227 #define ID_AA64MMFR0_EL1_BIGENDEL0 __BITS(16,19) 228 #define ID_AA64MMFR0_EL1_BIGENDEL0_NONE 0 229 #define ID_AA64MMFR0_EL1_BIGENDEL0_MIX 1 230 #define ID_AA64MMFR0_EL1_SNSMEM __BITS(12,15) 231 #define ID_AA64MMFR0_EL1_SNSMEM_NONE 0 232 #define ID_AA64MMFR0_EL1_SNSMEM_SNSMEM 1 233 #define ID_AA64MMFR0_EL1_BIGEND __BITS(8,11) 234 #define ID_AA64MMFR0_EL1_BIGEND_NONE 0 235 #define ID_AA64MMFR0_EL1_BIGEND_MIX 1 236 #define ID_AA64MMFR0_EL1_ASIDBITS __BITS(4,7) 237 #define ID_AA64MMFR0_EL1_ASIDBITS_8BIT 0 238 #define ID_AA64MMFR0_EL1_ASIDBITS_16BIT 2 239 #define ID_AA64MMFR0_EL1_PARANGE __BITS(0,3) 240 #define ID_AA64MMFR0_EL1_PARANGE_4G 0 241 #define ID_AA64MMFR0_EL1_PARANGE_64G 1 242 #define ID_AA64MMFR0_EL1_PARANGE_1T 2 243 #define ID_AA64MMFR0_EL1_PARANGE_4T 3 244 #define ID_AA64MMFR0_EL1_PARANGE_16T 4 245 #define ID_AA64MMFR0_EL1_PARANGE_256T 5 246 247 AARCH64REG_READ_INLINE(id_aa64mmfr1_el1) 248 AARCH64REG_READ_INLINE(id_aa64pfr0_el1) 249 AARCH64REG_READ_INLINE(id_aa64pfr1_el1) 250 AARCH64REG_READ_INLINE(id_pfr1_el1) 251 AARCH64REG_READ_INLINE(isr_el1) 252 AARCH64REG_READ_INLINE(midr_el1) 253 AARCH64REG_READ_INLINE(mpidr_el1) 254 255 #define MPIDR_AFF3 __BITS(32,39) 256 #define MPIDR_U __BIT(30) // 1 = Uni-Processor System 257 #define MPIDR_MT __BIT(24) // 1 = SMT(AFF0 is logical) 258 #define MPIDR_AFF2 __BITS(16,23) 259 #define MPIDR_AFF1 __BITS(8,15) 260 #define MPIDR_AFF0 __BITS(0,7) 261 262 AARCH64REG_READ_INLINE(mvfr0_el1) 263 264 #define MVFR0_FPROUND __BITS(31,28) 265 #define MVFR0_FPROUND_NEAREST 0 266 #define MVFR0_FPROUND_ALL 1 267 #define MVFR0_FPSHVEC __BITS(27,24) 268 #define MVFR0_FPSHVEC_NONE 0 269 #define MVFR0_FPSHVEC_SHVEC 1 270 #define MVFR0_FPSQRT __BITS(23,20) 271 #define MVFR0_FPSQRT_NONE 0 272 #define MVFR0_FPSQRT_VSQRT 1 273 #define MVFR0_FPDIVIDE __BITS(19,16) 274 #define MVFR0_FPDIVIDE_NONE 0 275 #define MVFR0_FPDIVIDE_VDIV 1 276 #define MVFR0_FPTRAP __BITS(15,12) 277 #define MVFR0_FPTRAP_NONE 0 278 #define MVFR0_FPTRAP_TRAP 1 279 #define MVFR0_FPDP __BITS(11,8) 280 #define MVFR0_FPDP_NONE 0 281 #define MVFR0_FPDP_VFPV2 1 282 #define MVFR0_FPDP_VFPV3 2 283 #define MVFR0_FPSP __BITS(7,4) 284 #define MVFR0_FPSP_NONE 0 285 #define MVFR0_FPSP_VFPV2 1 286 #define MVFR0_FPSP_VFPV3 2 287 #define MVFR0_SIMDREG __BITS(3,0) 288 #define MVFR0_SIMDREG_NONE 0 289 #define MVFR0_SIMDREG_16x64 1 290 #define MVFR0_SIMDREG_32x64 2 291 292 AARCH64REG_READ_INLINE(mvfr1_el1) 293 294 #define MVFR1_SIMDFMAC __BITS(31,28) 295 #define MVFR1_SIMDFMAC_NONE 0 296 #define MVFR1_SIMDFMAC_FMAC 1 297 #define MVFR1_FPHP __BITS(27,24) 298 #define MVFR1_FPHP_NONE 0 299 #define MVFR1_FPHP_HALF_SINGLE 1 300 #define MVFR1_FPHP_HALF_DOUBLE 2 301 #define MVFR1_SIMDHP __BITS(23,20) 302 #define MVFR1_SIMDHP_NONE 0 303 #define MVFR1_SIMDHP_HALF 1 304 #define MVFR1_SIMDSP __BITS(19,16) 305 #define MVFR1_SIMDSP_NONE 0 306 #define MVFR1_SIMDSP_SINGLE 1 307 #define MVFR1_SIMDINT __BITS(15,12) 308 #define MVFR1_SIMDINT_NONE 0 309 #define MVFR1_SIMDINT_INTEGER 1 310 #define MVFR1_SIMDLS __BITS(11,8) 311 #define MVFR1_SIMDLS_NONE 0 312 #define MVFR1_SIMDLS_LOADSTORE 1 313 #define MVFR1_FPDNAN __BITS(7,4) 314 #define MVFR1_FPDNAN_NONE 0 315 #define MVFR1_FPDNAN_NAN 1 316 #define MVFR1_FPFTZ __BITS(3,0) 317 #define MVFR1_FPFTZ_NONE 0 318 #define MVFR1_FPFTZ_DENORMAL 1 319 320 AARCH64REG_READ_INLINE(mvfr2_el1) 321 322 #define MVFR2_FPMISC __BITS(7,4) 323 #define MVFR2_FPMISC_NONE 0 324 #define MVFR2_FPMISC_SEL 1 325 #define MVFR2_FPMISC_DROUND 2 326 #define MVFR2_FPMISC_ROUNDINT 3 327 #define MVFR2_FPMISC_MAXMIN 4 328 #define MVFR2_SIMDMISC __BITS(3,0) 329 #define MVFR2_SIMDMISC_NONE 0 330 #define MVFR2_SIMDMISC_DROUND 1 331 #define MVFR2_SIMDMISC_ROUNDINT 2 332 #define MVFR2_SIMDMISC_MAXMIN 3 333 334 AARCH64REG_READ_INLINE(revidr_el1) 335 336 /* 337 * These are read/write registers 338 */ 339 AARCH64REG_READ_INLINE(cpacr_el1) // Coprocessor Access Control Regiser 340 AARCH64REG_WRITE_INLINE(cpacr_el1) 341 342 #define CPACR_TTA __BIT(28) // System Register Access Traps 343 #define CPACR_FPEN __BITS(21,20) 344 #define CPACR_FPEN_NONE __SHIFTIN(0, CPACR_FPEN) 345 #define CPACR_FPEN_EL1 __SHIFTIN(1, CPACR_FPEN) 346 #define CPACR_FPEN_NONE_2 __SHIFTIN(2, CPACR_FPEN) 347 #define CPACR_FPEN_ALL __SHIFTIN(3, CPACR_FPEN) 348 349 AARCH64REG_READ_INLINE(csselr_el1) // Cache Size Selection Register 350 AARCH64REG_WRITE_INLINE(csselr_el1) 351 352 #define CSSELR_LEVEL __BITS(3,1) // Cache level of required cache 353 #define CSSELR_IND __BIT(0) // Instruction not Data bit 354 355 AARCH64REG_READ_INLINE(daif) // Debug Async Irq Fiq mask register 356 AARCH64REG_WRITE_INLINE(daif) 357 AARCH64REG_WRITEIMM_INLINE(daifclr) 358 AARCH64REG_WRITEIMM_INLINE(daifset) 359 360 #define DAIF_D __BIT(9) // Debug Exception Mask 361 #define DAIF_A __BIT(8) // SError Abort Mask 362 #define DAIF_I __BIT(7) // IRQ Mask 363 #define DAIF_F __BIT(6) // FIQ Mask 364 #define DAIF_SETCLR_SHIFT 6 // for daifset/daifclr #imm shift 365 366 AARCH64REG_READ_INLINE(elr_el1) // Exception Link Register 367 AARCH64REG_WRITE_INLINE(elr_el1) 368 369 AARCH64REG_READ_INLINE(esr_el1) // Exception Symdrone Register 370 AARCH64REG_WRITE_INLINE(esr_el1) 371 372 #define ESR_EC __BITS(31,26) // Exception Cause 373 #define ESR_EC_UNKNOWN 0x00 // AXX: Unknown Reason 374 #define ESR_EC_WFX 0x01 // AXX: WFI or WFE instruction execution 375 #define ESR_EC_CP15_RT 0x03 // A32: MCR/MRC access to CP15 !EC=0 376 #define ESR_EC_CP15_RRT 0x04 // A32: MCRR/MRRC access to CP15 !EC=0 377 #define ESR_EC_CP14_RT 0x05 // A32: MCR/MRC access to CP14 378 #define ESR_EC_CP14_DT 0x06 // A32: LDC/STC access to CP14 379 #define ESR_EC_FP_ACCESS 0x07 // AXX: Access to SIMD/FP Registers 380 #define ESR_EC_FPID 0x08 // A32: MCR/MRC access to CP10 !EC=7 381 #define ESR_EC_CP14_RRT 0x0c // A32: MRRC access to CP14 382 #define ESR_EC_ILL_STATE 0x0e // AXX: Illegal Execution State 383 #define ESR_EC_SVC_A32 0x11 // A32: SVC Instruction Execution 384 #define ESR_EC_HVC_A32 0x12 // A32: HVC Instruction Execution 385 #define ESR_EC_SMC_A32 0x13 // A32: SMC Instruction Execution 386 #define ESR_EC_SVC_A64 0x15 // A64: SVC Instruction Execution 387 #define ESR_EC_HVC_A64 0x16 // A64: HVC Instruction Execution 388 #define ESR_EC_SMC_A64 0x17 // A64: SMC Instruction Execution 389 #define ESR_EC_SYS_REG 0x18 // A64: MSR/MRS/SYS instruction (!EC0/1/7) 390 #define ESR_EC_INSN_ABT_EL0 0x20 // AXX: Instruction Abort (EL0) 391 #define ESR_EC_INSN_ABT_EL1 0x21 // AXX: Instruction Abort (EL1) 392 #define ESR_EC_PC_ALIGNMENT 0x22 // AXX: Misaligned PC 393 #define ESR_EC_DATA_ABT_EL0 0x24 // AXX: Data Abort (EL0) 394 #define ESR_EC_DATA_ABT_EL1 0x25 // AXX: Data Abort (EL1) 395 #define ESR_EC_SP_ALIGNMENT 0x26 // AXX: Misaligned SP 396 #define ESR_EC_FP_TRAP_A32 0x28 // A32: FP Exception 397 #define ESR_EC_FP_TRAP_A64 0x2c // A64: FP Exception 398 #define ESR_EC_SERROR 0x2f // AXX: SError Interrupt 399 #define ESR_EC_BRKPNT_EL0 0x30 // AXX: Breakpoint Exception (EL0) 400 #define ESR_EC_BRKPNT_EL1 0x31 // AXX: Breakpoint Exception (EL1) 401 #define ESR_EC_SW_STEP_EL0 0x32 // AXX: Software Step (EL0) 402 #define ESR_EC_SW_STEP_EL1 0x33 // AXX: Software Step (EL1) 403 #define ESR_EC_WTCHPNT_EL0 0x34 // AXX: Watchpoint (EL0) 404 #define ESR_EC_WTCHPNT_EL1 0x35 // AXX: Watchpoint (EL1) 405 #define ESR_EC_BKPT_INSN_A32 0x38 // A32: BKPT Instruction Execution 406 #define ESR_EC_VECTOR_CATCH 0x3a // A32: Vector Catch Exception 407 #define ESR_EC_BKPT_INSN_A64 0x3c // A64: BKPT Instruction Execution 408 #define ESR_IL __BIT(25) // Instruction Length (1=32-bit) 409 #define ESR_ISS __BITS(24,0) // Instruction Specific Syndrome 410 #define ESR_ISS_CV __BIT(24) // common 411 #define ESR_ISS_COND __BITS(23,20) // common 412 #define ESR_ISS_WFX_TRAP_INSN __BIT(0) // for ESR_EC_WFX 413 #define ESR_ISS_MRC_OPC2 __BITS(19,17) // for ESR_EC_CP15_RT 414 #define ESR_ISS_MRC_OPC1 __BITS(16,14) // for ESR_EC_CP15_RT 415 #define ESR_ISS_MRC_CRN __BITS(13,10) // for ESR_EC_CP15_RT 416 #define ESR_ISS_MRC_RT __BITS(9,5) // for ESR_EC_CP15_RT 417 #define ESR_ISS_MRC_CRM __BITS(4,1) // for ESR_EC_CP15_RT 418 #define ESR_ISS_MRC_DIRECTION __BIT(0) // for ESR_EC_CP15_RT 419 #define ESR_ISS_MCRR_OPC1 __BITS(19,16) // for ESR_EC_CP15_RRT 420 #define ESR_ISS_MCRR_RT2 __BITS(14,10) // for ESR_EC_CP15_RRT 421 #define ESR_ISS_MCRR_RT __BITS(9,5) // for ESR_EC_CP15_RRT 422 #define ESR_ISS_MCRR_CRM __BITS(4,1) // for ESR_EC_CP15_RRT 423 #define ESR_ISS_MCRR_DIRECTION __BIT(0) // for ESR_EC_CP15_RRT 424 #define ESR_ISS_HVC_IMM16 __BITS(15,0) // for ESR_EC_{SVC,HVC} 425 // ... 426 #define ESR_ISS_INSNABORT_EA __BIT(9) // for ESC_RC_INSN_ABT_EL[01] 427 #define ESR_ISS_INSNABORT_S1PTW __BIT(7) // for ESC_RC_INSN_ABT_EL[01] 428 #define ESR_ISS_INSNABORT_IFSC __BITS(0,5) // for ESC_RC_INSN_ABT_EL[01] 429 #define ESR_ISS_DATAABORT_ISV __BIT(24) // for ESC_RC_DATA_ABT_EL[01] 430 #define ESR_ISS_DATAABORT_SAS __BITS(23,22) // for ESC_RC_DATA_ABT_EL[01] 431 #define ESR_ISS_DATAABORT_SSE __BIT(21) // for ESC_RC_DATA_ABT_EL[01] 432 #define ESR_ISS_DATAABORT_SRT __BITS(19,16) // for ESC_RC_DATA_ABT_EL[01] 433 #define ESR_ISS_DATAABORT_SF __BIT(15) // for ESC_RC_DATA_ABT_EL[01] 434 #define ESR_ISS_DATAABORT_AR __BIT(14) // for ESC_RC_DATA_ABT_EL[01] 435 #define ESR_ISS_DATAABORT_EA __BIT(9) // for ESC_RC_DATA_ABT_EL[01] 436 #define ESR_ISS_DATAABORT_CM __BIT(8) // for ESC_RC_DATA_ABT_EL[01] 437 #define ESR_ISS_DATAABORT_S1PTW __BIT(7) // for ESC_RC_DATA_ABT_EL[01] 438 #define ESR_ISS_DATAABORT_WnR __BIT(6) // for ESC_RC_DATA_ABT_EL[01] 439 #define ESR_ISS_DATAABORT_DFSC __BITS(0,5) // for ESC_RC_DATA_ABT_EL[01] 440 441 #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_0 0x00 442 #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_1 0x01 443 #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_2 0x02 444 #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_3 0x03 445 #define ESR_ISS_FSC_TRANSLATION_FAULT_0 0x04 446 #define ESR_ISS_FSC_TRANSLATION_FAULT_1 0x05 447 #define ESR_ISS_FSC_TRANSLATION_FAULT_2 0x06 448 #define ESR_ISS_FSC_TRANSLATION_FAULT_3 0x07 449 #define ESR_ISS_FSC_ACCESS_FAULT_0 0x08 450 #define ESR_ISS_FSC_ACCESS_FAULT_1 0x09 451 #define ESR_ISS_FSC_ACCESS_FAULT_2 0x0a 452 #define ESR_ISS_FSC_ACCESS_FAULT_3 0x0b 453 #define ESR_ISS_FSC_PERM_FAULT_0 0x0c 454 #define ESR_ISS_FSC_PERM_FAULT_1 0x0d 455 #define ESR_ISS_FSC_PERM_FAULT_2 0x0e 456 #define ESR_ISS_FSC_PERM_FAULT_3 0x0f 457 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT 0x10 458 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_0 0x14 459 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_1 0x15 460 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_2 0x16 461 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_3 0x17 462 #define ESR_ISS_FSC_SYNC_PARITY_ERROR 0x18 463 #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_0 0x1c 464 #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_1 0x1d 465 #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_2 0x1e 466 #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_3 0x1f 467 #define ESR_ISS_FSC_ALIGNMENT_FAULT 0x21 468 #define ESR_ISS_FSC_TLB_CONFLICT_FAULT 0x30 469 #define ESR_ISS_FSC_LOCKDOWN_ABORT 0x34 470 #define ESR_ISS_FSC_UNSUPPORTED_EXCLUSIVE 0x35 471 #define ESR_ISS_FSC_FIRST_LEVEL_DOMAIN_FAULT 0x3d 472 #define ESR_ISS_FSC_SECOND_LEVEL_DOMAIN_FAULT 0x3e 473 474 475 AARCH64REG_READ_INLINE(far_el1) // Fault Address Register 476 AARCH64REG_WRITE_INLINE(far_el1) 477 478 AARCH64REG_READ_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73 479 AARCH64REG_WRITE_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73 480 481 #define L2CTLR_NUMOFCORE __BITS(25,24) // Number of cores 482 #define L2CTLR_CPUCACHEPROT __BIT(22) // CPU Cache Protection 483 #define L2CTLR_SCUL2CACHEPROT __BIT(21) // SCU-L2 Cache Protection 484 #define L2CTLR_L2_INPUT_LATENCY __BIT(5) // L2 Data RAM input latency 485 #define L2CTLR_L2_OUTPUT_LATENCY __BIT(0) // L2 Data RAM output latency 486 487 AARCH64REG_READ_INLINE(mair_el1) // Memory Attribute Indirection Register 488 AARCH64REG_WRITE_INLINE(mair_el1) 489 490 #define MAIR_ATTR0 __BITS(7,0) 491 #define MAIR_ATTR1 __BITS(15,8) 492 #define MAIR_ATTR2 __BITS(23,16) 493 #define MAIR_ATTR3 __BITS(31,24) 494 #define MAIR_ATTR4 __BITS(39,32) 495 #define MAIR_ATTR5 __BITS(47,40) 496 #define MAIR_ATTR6 __BITS(55,48) 497 #define MAIR_ATTR7 __BITS(63,56) 498 #define MAIR_DEVICE_nGnRnE 0x00 // NoGathering,NoReordering,NoEarlyWriteAck. 499 #define MAIR_NORMAL_NC 0x44 500 #define MAIR_NORMAL_WT 0xbb 501 #define MAIR_NORMAL_WB 0xff 502 503 AARCH64REG_READ_INLINE(par_el1) // Physical Address Register 504 AARCH64REG_WRITE_INLINE(par_el1) 505 506 #define PAR_ATTR __BITS(63,56) // F=0 memory attributes 507 #define PAR_PA __BITS(47,12) // F=0 physical address 508 #define PAR_NS __BIT(9) // F=0 non-secure 509 #define PAR_S __BIT(9) // F=1 failure stage 510 #define PAR_SHA __BITS(8,7) // F=0 shareability attribute 511 #define PAR_SHA_NONE 0 512 #define PAR_SHA_OUTER 2 513 #define PAR_SHA_INNER 3 514 #define PAR_PTW __BIT(8) // F=1 partial table walk 515 #define PAR_FST __BITS(6,1) // F=1 fault status code 516 #define PAR_F __BIT(0) // translation failed 517 518 AARCH64REG_READ_INLINE(rmr_el1) // Reset Management Register 519 AARCH64REG_WRITE_INLINE(rmr_el1) 520 521 AARCH64REG_READ_INLINE(rvbar_el1) // Reset Vector Base Address Register 522 AARCH64REG_WRITE_INLINE(rvbar_el1) 523 524 AARCH64REG_READ_INLINE(sctlr_el1) // System Control Register 525 AARCH64REG_WRITE_INLINE(sctlr_el1) 526 527 #define SCTLR_RES0 0xc8222400 // Reserved ARMv8.0, write 0 528 #define SCTLR_RES1 0x30d00800 // Reserved ARMv8.0, write 1 529 #define SCTLR_M __BIT(0) 530 #define SCTLR_A __BIT(1) 531 #define SCTLR_C __BIT(2) 532 #define SCTLR_SA __BIT(3) 533 #define SCTLR_SA0 __BIT(4) 534 #define SCTLR_CP15BEN __BIT(5) 535 #define SCTLR_THEE __BIT(6) 536 #define SCTLR_ITD __BIT(7) 537 #define SCTLR_SED __BIT(8) 538 #define SCTLR_UMA __BIT(9) 539 #define SCTLR_I __BIT(12) 540 #define SCTLR_DZE __BIT(14) 541 #define SCTLR_UCT __BIT(15) 542 #define SCTLR_nTWI __BIT(16) 543 #define SCTLR_nTWE __BIT(18) 544 #define SCTLR_WXN __BIT(19) 545 #define SCTLR_IESB __BIT(21) 546 #define SCTLR_SPAN __BIT(23) 547 #define SCTLR_EOE __BIT(24) 548 #define SCTLR_EE __BIT(25) 549 #define SCTLR_UCI __BIT(26) 550 #define SCTLR_nTLSMD __BIT(28) 551 #define SCTLR_LSMAOE __BIT(29) 552 553 // current EL stack pointer 554 static __inline uint64_t 555 reg_sp_read(void) 556 { 557 uint64_t __rv; 558 __asm __volatile ("mov %0, sp" : "=r"(__rv)); 559 return __rv; 560 } 561 562 AARCH64REG_READ_INLINE(sp_el0) // EL0 Stack Pointer 563 AARCH64REG_WRITE_INLINE(sp_el0) 564 565 AARCH64REG_READ_INLINE(spsel) // Stack Pointer Select 566 AARCH64REG_WRITE_INLINE(spsel) 567 568 #define SPSEL_SP __BIT(0); // use SP_EL0 at all exception levels 569 570 AARCH64REG_READ_INLINE(spsr_el1) // Saved Program Status Register 571 AARCH64REG_WRITE_INLINE(spsr_el1) 572 573 #define SPSR_NZCV __BITS(31,28) // mask of N Z C V 574 #define SPSR_N __BIT(31) // Negative 575 #define SPSR_Z __BIT(30) // Zero 576 #define SPSR_C __BIT(29) // Carry 577 #define SPSR_V __BIT(28) // oVerflow 578 #define SPSR_A32_Q __BIT(27) // A32: Overflow 579 #define SPSR_A32_J __BIT(24) // A32: Jazelle Mode 580 #define SPSR_A32_IT1 __BIT(23) // A32: IT[1] 581 #define SPSR_A32_IT0 __BIT(22) // A32: IT[0] 582 #define SPSR_SS __BIT(21) // Software Step 583 #define SPSR_IL __BIT(20) // Instruction Length 584 #define SPSR_GE __BITS(19,16) // A32: SIMD GE 585 #define SPSR_IT7 __BIT(15) // A32: IT[7] 586 #define SPSR_IT6 __BIT(14) // A32: IT[6] 587 #define SPSR_IT5 __BIT(13) // A32: IT[5] 588 #define SPSR_IT4 __BIT(12) // A32: IT[4] 589 #define SPSR_IT3 __BIT(11) // A32: IT[3] 590 #define SPSR_IT2 __BIT(10) // A32: IT[2] 591 #define SPSR_A64_D __BIT(9) // A64: Debug Exception Mask 592 #define SPSR_A32_E __BIT(9) // A32: BE Endian Mode 593 #define SPSR_A __BIT(8) // Async abort (SError) Mask 594 #define SPSR_I __BIT(7) // IRQ Mask 595 #define SPSR_F __BIT(6) // FIQ Mask 596 #define SPSR_A32_T __BIT(5) // A32 Thumb Mode 597 #define SPSR_M __BITS(4,0) // Execution State 598 #define SPSR_M_EL3H 0x0d 599 #define SPSR_M_EL3T 0x0c 600 #define SPSR_M_EL2H 0x09 601 #define SPSR_M_EL2T 0x08 602 #define SPSR_M_EL1H 0x05 603 #define SPSR_M_EL1T 0x04 604 #define SPSR_M_EL0T 0x00 605 #define SPSR_M_SYS32 0x1f 606 #define SPSR_M_UND32 0x1b 607 #define SPSR_M_ABT32 0x17 608 #define SPSR_M_SVC32 0x13 609 #define SPSR_M_IRQ32 0x12 610 #define SPSR_M_FIQ32 0x11 611 #define SPSR_M_USR32 0x10 612 613 AARCH64REG_READ_INLINE(tcr_el1) // Translation Control Register 614 AARCH64REG_WRITE_INLINE(tcr_el1) 615 616 #define TCR_PAGE_SIZE1(tcr) (1L << ((1L << __SHIFTOUT(tcr, TCR_TG1)) + 8)) 617 618 AARCH64REG_READ_INLINE(tpidr_el1) // Thread ID Register (EL1) 619 AARCH64REG_WRITE_INLINE(tpidr_el1) 620 621 AARCH64REG_WRITE_INLINE(tpidrro_el0) // Thread ID Register (RO for EL0) 622 623 AARCH64REG_READ_INLINE(ttbr0_el1) // Translation Table Base Register 0 EL1 624 AARCH64REG_WRITE_INLINE(ttbr0_el1) 625 626 AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1 627 AARCH64REG_WRITE_INLINE(ttbr1_el1) 628 629 AARCH64REG_READ_INLINE(vbar_el1) // Vector Base Address Register 630 AARCH64REG_WRITE_INLINE(vbar_el1) 631 632 /* 633 * From here on, these are DEBUG registers 634 */ 635 AARCH64REG_READ_INLINE(dbgbcr0_el1) // Debug Breakpoint Control Register 0 636 AARCH64REG_WRITE_INLINE(dbgbcr0_el1) 637 AARCH64REG_READ_INLINE(dbgbcr1_el1) // Debug Breakpoint Control Register 1 638 AARCH64REG_WRITE_INLINE(dbgbcr1_el1) 639 AARCH64REG_READ_INLINE(dbgbcr2_el1) // Debug Breakpoint Control Register 2 640 AARCH64REG_WRITE_INLINE(dbgbcr2_el1) 641 AARCH64REG_READ_INLINE(dbgbcr3_el1) // Debug Breakpoint Control Register 3 642 AARCH64REG_WRITE_INLINE(dbgbcr3_el1) 643 AARCH64REG_READ_INLINE(dbgbcr4_el1) // Debug Breakpoint Control Register 4 644 AARCH64REG_WRITE_INLINE(dbgbcr4_el1) 645 AARCH64REG_READ_INLINE(dbgbcr5_el1) // Debug Breakpoint Control Register 5 646 AARCH64REG_WRITE_INLINE(dbgbcr5_el1) 647 AARCH64REG_READ_INLINE(dbgbcr6_el1) // Debug Breakpoint Control Register 6 648 AARCH64REG_WRITE_INLINE(dbgbcr6_el1) 649 AARCH64REG_READ_INLINE(dbgbcr7_el1) // Debug Breakpoint Control Register 7 650 AARCH64REG_WRITE_INLINE(dbgbcr7_el1) 651 AARCH64REG_READ_INLINE(dbgbcr8_el1) // Debug Breakpoint Control Register 8 652 AARCH64REG_WRITE_INLINE(dbgbcr8_el1) 653 AARCH64REG_READ_INLINE(dbgbcr9_el1) // Debug Breakpoint Control Register 9 654 AARCH64REG_WRITE_INLINE(dbgbcr9_el1) 655 AARCH64REG_READ_INLINE(dbgbcr10_el1) // Debug Breakpoint Control Register 10 656 AARCH64REG_WRITE_INLINE(dbgbcr10_el1) 657 AARCH64REG_READ_INLINE(dbgbcr11_el1) // Debug Breakpoint Control Register 11 658 AARCH64REG_WRITE_INLINE(dbgbcr11_el1) 659 AARCH64REG_READ_INLINE(dbgbcr12_el1) // Debug Breakpoint Control Register 12 660 AARCH64REG_WRITE_INLINE(dbgbcr12_el1) 661 AARCH64REG_READ_INLINE(dbgbcr13_el1) // Debug Breakpoint Control Register 13 662 AARCH64REG_WRITE_INLINE(dbgbcr13_el1) 663 AARCH64REG_READ_INLINE(dbgbcr14_el1) // Debug Breakpoint Control Register 14 664 AARCH64REG_WRITE_INLINE(dbgbcr14_el1) 665 AARCH64REG_READ_INLINE(dbgbcr15_el1) // Debug Breakpoint Control Register 15 666 AARCH64REG_WRITE_INLINE(dbgbcr15_el1) 667 668 #define DBGBCR_BT __BITS(23,20) 669 #define DBGBCR_LBN __BITS(19,16) 670 #define DBGBCR_SSC __BITS(15,14) 671 #define DBGBCR_HMC __BIT(13) 672 #define DBGBCR_BAS __BITS(8,5) 673 #define DBGBCR_PMC __BITS(2,1) 674 #define DBGBCR_E __BIT(0) 675 676 AARCH64REG_READ_INLINE(dbgbvr0_el1) // Debug Breakpoint Value Register 0 677 AARCH64REG_WRITE_INLINE(dbgbvr0_el1) 678 AARCH64REG_READ_INLINE(dbgbvr1_el1) // Debug Breakpoint Value Register 1 679 AARCH64REG_WRITE_INLINE(dbgbvr1_el1) 680 AARCH64REG_READ_INLINE(dbgbvr2_el1) // Debug Breakpoint Value Register 2 681 AARCH64REG_WRITE_INLINE(dbgbvr2_el1) 682 AARCH64REG_READ_INLINE(dbgbvr3_el1) // Debug Breakpoint Value Register 3 683 AARCH64REG_WRITE_INLINE(dbgbvr3_el1) 684 AARCH64REG_READ_INLINE(dbgbvr4_el1) // Debug Breakpoint Value Register 4 685 AARCH64REG_WRITE_INLINE(dbgbvr4_el1) 686 AARCH64REG_READ_INLINE(dbgbvr5_el1) // Debug Breakpoint Value Register 5 687 AARCH64REG_WRITE_INLINE(dbgbvr5_el1) 688 AARCH64REG_READ_INLINE(dbgbvr6_el1) // Debug Breakpoint Value Register 6 689 AARCH64REG_WRITE_INLINE(dbgbvr6_el1) 690 AARCH64REG_READ_INLINE(dbgbvr7_el1) // Debug Breakpoint Value Register 7 691 AARCH64REG_WRITE_INLINE(dbgbvr7_el1) 692 AARCH64REG_READ_INLINE(dbgbvr8_el1) // Debug Breakpoint Value Register 8 693 AARCH64REG_WRITE_INLINE(dbgbvr8_el1) 694 AARCH64REG_READ_INLINE(dbgbvr9_el1) // Debug Breakpoint Value Register 9 695 AARCH64REG_WRITE_INLINE(dbgbvr9_el1) 696 AARCH64REG_READ_INLINE(dbgbvr10_el1) // Debug Breakpoint Value Register 10 697 AARCH64REG_WRITE_INLINE(dbgbvr10_el1) 698 AARCH64REG_READ_INLINE(dbgbvr11_el1) // Debug Breakpoint Value Register 11 699 AARCH64REG_WRITE_INLINE(dbgbvr11_el1) 700 AARCH64REG_READ_INLINE(dbgbvr12_el1) // Debug Breakpoint Value Register 12 701 AARCH64REG_WRITE_INLINE(dbgbvr12_el1) 702 AARCH64REG_READ_INLINE(dbgbvr13_el1) // Debug Breakpoint Value Register 13 703 AARCH64REG_WRITE_INLINE(dbgbvr13_el1) 704 AARCH64REG_READ_INLINE(dbgbvr14_el1) // Debug Breakpoint Value Register 14 705 AARCH64REG_WRITE_INLINE(dbgbvr14_el1) 706 AARCH64REG_READ_INLINE(dbgbvr15_el1) // Debug Breakpoint Value Register 15 707 AARCH64REG_WRITE_INLINE(dbgbvr15_el1) 708 709 AARCH64REG_READ_INLINE(dbgwcr0_el1) // Debug Watchpoint Control Register 0 710 AARCH64REG_WRITE_INLINE(dbgwcr0_el1) 711 AARCH64REG_READ_INLINE(dbgwcr1_el1) // Debug Watchpoint Control Register 1 712 AARCH64REG_WRITE_INLINE(dbgwcr1_el1) 713 AARCH64REG_READ_INLINE(dbgwcr2_el1) // Debug Watchpoint Control Register 2 714 AARCH64REG_WRITE_INLINE(dbgwcr2_el1) 715 AARCH64REG_READ_INLINE(dbgwcr3_el1) // Debug Watchpoint Control Register 3 716 AARCH64REG_WRITE_INLINE(dbgwcr3_el1) 717 AARCH64REG_READ_INLINE(dbgwcr4_el1) // Debug Watchpoint Control Register 4 718 AARCH64REG_WRITE_INLINE(dbgwcr4_el1) 719 AARCH64REG_READ_INLINE(dbgwcr5_el1) // Debug Watchpoint Control Register 5 720 AARCH64REG_WRITE_INLINE(dbgwcr5_el1) 721 AARCH64REG_READ_INLINE(dbgwcr6_el1) // Debug Watchpoint Control Register 6 722 AARCH64REG_WRITE_INLINE(dbgwcr6_el1) 723 AARCH64REG_READ_INLINE(dbgwcr7_el1) // Debug Watchpoint Control Register 7 724 AARCH64REG_WRITE_INLINE(dbgwcr7_el1) 725 AARCH64REG_READ_INLINE(dbgwcr8_el1) // Debug Watchpoint Control Register 8 726 AARCH64REG_WRITE_INLINE(dbgwcr8_el1) 727 AARCH64REG_READ_INLINE(dbgwcr9_el1) // Debug Watchpoint Control Register 9 728 AARCH64REG_WRITE_INLINE(dbgwcr9_el1) 729 AARCH64REG_READ_INLINE(dbgwcr10_el1) // Debug Watchpoint Control Register 10 730 AARCH64REG_WRITE_INLINE(dbgwcr10_el1) 731 AARCH64REG_READ_INLINE(dbgwcr11_el1) // Debug Watchpoint Control Register 11 732 AARCH64REG_WRITE_INLINE(dbgwcr11_el1) 733 AARCH64REG_READ_INLINE(dbgwcr12_el1) // Debug Watchpoint Control Register 12 734 AARCH64REG_WRITE_INLINE(dbgwcr12_el1) 735 AARCH64REG_READ_INLINE(dbgwcr13_el1) // Debug Watchpoint Control Register 13 736 AARCH64REG_WRITE_INLINE(dbgwcr13_el1) 737 AARCH64REG_READ_INLINE(dbgwcr14_el1) // Debug Watchpoint Control Register 14 738 AARCH64REG_WRITE_INLINE(dbgwcr14_el1) 739 AARCH64REG_READ_INLINE(dbgwcr15_el1) // Debug Watchpoint Control Register 15 740 AARCH64REG_WRITE_INLINE(dbgwcr15_el1) 741 742 #define DBGWCR_MASK __BITS(28,24) 743 #define DBGWCR_WT __BIT(20) 744 #define DBGWCR_LBN __BITS(19,16) 745 #define DBGWCR_SSC __BITS(15,14) 746 #define DBGWCR_HMC __BIT(13) 747 #define DBGWCR_BAS __BITS(12,5) 748 #define DBGWCR_LSC __BITS(4,3) 749 #define DBGWCR_PAC __BITS(2,1) 750 #define DBGWCR_E __BIT(0) 751 752 AARCH64REG_READ_INLINE(dbgwvr0_el1) // Debug Watchpoint Value Register 0 753 AARCH64REG_WRITE_INLINE(dbgwvr0_el1) 754 AARCH64REG_READ_INLINE(dbgwvr1_el1) // Debug Watchpoint Value Register 1 755 AARCH64REG_WRITE_INLINE(dbgwvr1_el1) 756 AARCH64REG_READ_INLINE(dbgwvr2_el1) // Debug Watchpoint Value Register 2 757 AARCH64REG_WRITE_INLINE(dbgwvr2_el1) 758 AARCH64REG_READ_INLINE(dbgwvr3_el1) // Debug Watchpoint Value Register 3 759 AARCH64REG_WRITE_INLINE(dbgwvr3_el1) 760 AARCH64REG_READ_INLINE(dbgwvr4_el1) // Debug Watchpoint Value Register 4 761 AARCH64REG_WRITE_INLINE(dbgwvr4_el1) 762 AARCH64REG_READ_INLINE(dbgwvr5_el1) // Debug Watchpoint Value Register 5 763 AARCH64REG_WRITE_INLINE(dbgwvr5_el1) 764 AARCH64REG_READ_INLINE(dbgwvr6_el1) // Debug Watchpoint Value Register 6 765 AARCH64REG_WRITE_INLINE(dbgwvr6_el1) 766 AARCH64REG_READ_INLINE(dbgwvr7_el1) // Debug Watchpoint Value Register 7 767 AARCH64REG_WRITE_INLINE(dbgwvr7_el1) 768 AARCH64REG_READ_INLINE(dbgwvr8_el1) // Debug Watchpoint Value Register 8 769 AARCH64REG_WRITE_INLINE(dbgwvr8_el1) 770 AARCH64REG_READ_INLINE(dbgwvr9_el1) // Debug Watchpoint Value Register 9 771 AARCH64REG_WRITE_INLINE(dbgwvr9_el1) 772 AARCH64REG_READ_INLINE(dbgwvr10_el1) // Debug Watchpoint Value Register 10 773 AARCH64REG_WRITE_INLINE(dbgwvr10_el1) 774 AARCH64REG_READ_INLINE(dbgwvr11_el1) // Debug Watchpoint Value Register 11 775 AARCH64REG_WRITE_INLINE(dbgwvr11_el1) 776 AARCH64REG_READ_INLINE(dbgwvr12_el1) // Debug Watchpoint Value Register 12 777 AARCH64REG_WRITE_INLINE(dbgwvr12_el1) 778 AARCH64REG_READ_INLINE(dbgwvr13_el1) // Debug Watchpoint Value Register 13 779 AARCH64REG_WRITE_INLINE(dbgwvr13_el1) 780 AARCH64REG_READ_INLINE(dbgwvr14_el1) // Debug Watchpoint Value Register 14 781 AARCH64REG_WRITE_INLINE(dbgwvr14_el1) 782 AARCH64REG_READ_INLINE(dbgwvr15_el1) // Debug Watchpoint Value Register 15 783 AARCH64REG_WRITE_INLINE(dbgwvr15_el1) 784 785 #define DBGWVR_MASK __BITS(64,3) 786 787 788 AARCH64REG_READ_INLINE(mdscr_el1) // Monitor Debug System Control Register 789 AARCH64REG_WRITE_INLINE(mdscr_el1) 790 791 AARCH64REG_WRITE_INLINE(oslar_el1) // OS Lock Access Register 792 793 AARCH64REG_READ_INLINE(oslsr_el1) // OS Lock Status Register 794 795 /* 796 * From here on, these are PMC registers 797 */ 798 799 AARCH64REG_READ_INLINE(pmccfiltr_el0) 800 AARCH64REG_WRITE_INLINE(pmccfiltr_el0) 801 802 #define PMCCFILTR_P __BIT(31) // Don't count cycles in EL1 803 #define PMCCFILTR_U __BIT(30) // Don't count cycles in EL0 804 #define PMCCFILTR_NSK __BIT(29) // Don't count cycles in NS EL1 805 #define PMCCFILTR_NSU __BIT(28) // Don't count cycles in NS EL0 806 #define PMCCFILTR_NSH __BIT(27) // Don't count cycles in NS EL2 807 #define PMCCFILTR_M __BIT(26) // Don't count cycles in EL3 808 809 AARCH64REG_READ_INLINE(pmccntr_el0) 810 811 AARCH64REG_READ_INLINE(pmceid0_el0) 812 AARCH64REG_READ_INLINE(pmceid1_el0) 813 814 AARCH64REG_WRITE_INLINE(pmcntenclr_el0) 815 AARCH64REG_WRITE_INLINE(pmcntenset_el0) 816 817 AARCH64REG_READ_INLINE(pmcr_el0) 818 AARCH64REG_WRITE_INLINE(pmcr_el0) 819 820 #define PMCR_IMP __BITS(31,24) // Implementor code 821 #define PMCR_IDCODE __BITS(23,16) // Identification code 822 #define PMCR_N __BITS(15,11) // Number of event counters 823 #define PMCR_LC __BIT(6) // Long cycle counter enable 824 #define PMCR_DP __BIT(5) // Disable cycle counter when event 825 // counting is prohibited 826 #define PMCR_X __BIT(4) // Enable export of events 827 #define PMCR_D __BIT(3) // Clock divider 828 #define PMCR_C __BIT(2) // Cycle counter reset 829 #define PMCR_P __BIT(1) // Event counter reset 830 #define PMCR_E __BIT(0) // Enable 831 832 833 AARCH64REG_READ_INLINE(pmevcntr1_el0) 834 AARCH64REG_WRITE_INLINE(pmevcntr1_el0) 835 836 AARCH64REG_READ_INLINE(pmevtyper1_el0) 837 AARCH64REG_WRITE_INLINE(pmevtyper1_el0) 838 839 #define PMEVTYPER_P __BIT(31) // Don't count events in EL1 840 #define PMEVTYPER_U __BIT(30) // Don't count events in EL0 841 #define PMEVTYPER_NSK __BIT(29) // Don't count events in NS EL1 842 #define PMEVTYPER_NSU __BIT(28) // Don't count events in NS EL0 843 #define PMEVTYPER_NSH __BIT(27) // Count events in NS EL2 844 #define PMEVTYPER_M __BIT(26) // Don't count events in EL3 845 #define PMEVTYPER_MT __BIT(25) // Count events on all CPUs with same 846 // aff1 level 847 #define PMEVTYPER_EVTCOUNT __BITS(15,0) // Event to count 848 849 AARCH64REG_WRITE_INLINE(pmintenclr_el1) 850 AARCH64REG_WRITE_INLINE(pmintenset_el1) 851 852 AARCH64REG_WRITE_INLINE(pmovsclr_el0) 853 AARCH64REG_READ_INLINE(pmovsset_el0) 854 AARCH64REG_WRITE_INLINE(pmovsset_el0) 855 856 AARCH64REG_WRITE_INLINE(pmselr_el0) 857 858 AARCH64REG_WRITE_INLINE(pmswinc_el0) 859 860 AARCH64REG_READ_INLINE(pmuserenr_el0) 861 AARCH64REG_WRITE_INLINE(pmuserenr_el0) 862 863 AARCH64REG_READ_INLINE(pmxevcntr_el0) 864 AARCH64REG_WRITE_INLINE(pmxevcntr_el0) 865 866 AARCH64REG_READ_INLINE(pmxevtyper_el0) 867 AARCH64REG_WRITE_INLINE(pmxevtyper_el0) 868 869 /* 870 * Generic timer registers 871 */ 872 873 AARCH64REG_READ_INLINE(cntfrq_el0) 874 875 AARCH64REG_READ_INLINE(cnthctl_el2) 876 AARCH64REG_WRITE_INLINE(cnthctl_el2) 877 878 #define CNTHCTL_EVNTDIR __BIT(3) 879 #define CNTHCTL_EVNTEN __BIT(2) 880 #define CNTHCTL_EL1PCEN __BIT(1) 881 #define CNTHCTL_EL1PCTEN __BIT(0) 882 883 AARCH64REG_READ_INLINE(cntkctl_el1) 884 AARCH64REG_WRITE_INLINE(cntkctl_el1) 885 886 #define CNTKCTL_EL0PTEN __BIT(9) // EL0 access for CNTP CVAL/TVAL/CTL 887 #define CNTKCTL_PL0PTEN CNTKCTL_EL0PTEN 888 #define CNTKCTL_EL0VTEN __BIT(8) // EL0 access for CNTV CVAL/TVAL/CTL 889 #define CNTKCTL_PL0VTEN CNTKCTL_EL0VTEN 890 #define CNTKCTL_ELNTI __BITS(7,4) 891 #define CNTKCTL_EVNTDIR __BIT(3) 892 #define CNTKCTL_EVNTEN __BIT(2) 893 #define CNTKCTL_EL0VCTEN __BIT(1) // EL0 access for CNTVCT and CNTFRQ 894 #define CNTKCTL_PL0VCTEN CNTKCTL_EL0VCTEN 895 #define CNTKCTL_EL0PCTEN __BIT(0) // EL0 access for CNTPCT and CNTFRQ 896 #define CNTKCTL_PL0PCTEN CNTKCTL_EL0PCTEN 897 898 AARCH64REG_READ_INLINE(cntp_ctl_el0) 899 AARCH64REG_WRITE_INLINE(cntp_ctl_el0) 900 AARCH64REG_READ_INLINE(cntp_cval_el0) 901 AARCH64REG_WRITE_INLINE(cntp_cval_el0) 902 AARCH64REG_READ_INLINE(cntp_tval_el0) 903 AARCH64REG_WRITE_INLINE(cntp_tval_el0) 904 AARCH64REG_READ_INLINE(cntpct_el0) 905 AARCH64REG_WRITE_INLINE(cntpct_el0) 906 907 AARCH64REG_READ_INLINE(cntps_ctl_el1) 908 AARCH64REG_WRITE_INLINE(cntps_ctl_el1) 909 AARCH64REG_READ_INLINE(cntps_cval_el1) 910 AARCH64REG_WRITE_INLINE(cntps_cval_el1) 911 AARCH64REG_READ_INLINE(cntps_tval_el1) 912 AARCH64REG_WRITE_INLINE(cntps_tval_el1) 913 914 AARCH64REG_READ_INLINE(cntv_ctl_el0) 915 AARCH64REG_WRITE_INLINE(cntv_ctl_el0) 916 AARCH64REG_READ_INLINE(cntv_cval_el0) 917 AARCH64REG_WRITE_INLINE(cntv_cval_el0) 918 AARCH64REG_READ_INLINE(cntv_tval_el0) 919 AARCH64REG_WRITE_INLINE(cntv_tval_el0) 920 AARCH64REG_READ_INLINE(cntvct_el0) 921 AARCH64REG_WRITE_INLINE(cntvct_el0) 922 923 #define CNTCTL_ISTATUS __BIT(2) // Interrupt Asserted 924 #define CNTCTL_IMASK __BIT(1) // Timer Interrupt is Masked 925 #define CNTCTL_ENABLE __BIT(0) // Timer Enabled 926 927 928 // ID_AA64PFR0_EL1: AArch64 Processor Feature Register 0 929 #define ID_AA64PFR0_EL1_GIC __BITS(24,27) // GIC CPU IF 930 #define ID_AA64PFR0_EL1_GIC_SHIFT 24 931 #define ID_AA64PFR0_EL1_GIC_CPUIF_EN 1 932 #define ID_AA64PFR0_EL1_GIC_CPUIF_NONE 0 933 #define ID_AA64PFR0_EL1_ADVSIMD __BITS(23,20) // SIMD 934 #define ID_AA64PFR0_EL1_ADV_SIMD_IMPL 0x0 935 #define ID_AA64PFR0_EL1_ADV_SIMD_NONE 0xf 936 #define ID_AA64PFR0_EL1_FP __BITS(19,16) // FP 937 #define ID_AA64PFR0_EL1_FP_IMPL 0x0 938 #define ID_AA64PFR0_EL1_FP_NONE 0xf 939 #define ID_AA64PFR0_EL1_EL3 __BITS(15,12) // EL3 handling 940 #define ID_AA64PFR0_EL1_EL3_NONE 0 941 #define ID_AA64PFR0_EL1_EL3_64 1 942 #define ID_AA64PFR0_EL1_EL3_64_32 2 943 #define ID_AA64PFR0_EL1_EL2 __BITS(11,8) // EL2 handling 944 #define ID_AA64PFR0_EL1_EL2_NONE 0 945 #define ID_AA64PFR0_EL1_EL2_64 1 946 #define ID_AA64PFR0_EL1_EL2_64_32 2 947 #define ID_AA64PFR0_EL1_EL1 __BITS(7,4) // EL1 handling 948 #define ID_AA64PFR0_EL1_EL1_64 1 949 #define ID_AA64PFR0_EL1_EL1_64_32 2 950 #define ID_AA64PFR0_EL1_EL0 __BITS(3,0) // EL0 handling 951 #define ID_AA64PFR0_EL1_EL0_64 1 952 #define ID_AA64PFR0_EL1_EL0_64_32 2 953 954 // ICC_SRE_EL1: Interrupt Controller System Register Enable register 955 #define ICC_SRE_EL1_SRE __BIT(0) 956 #define ICC_SRE_EL1_DFB __BIT(1) 957 #define ICC_SRE_EL1_DIB __BIT(2) 958 959 // ICC_SRE_EL2: Interrupt Controller System Register Enable register 960 #define ICC_SRE_EL2_SRE __BIT(0) 961 #define ICC_SRE_EL2_DFB __BIT(1) 962 #define ICC_SRE_EL2_DIB __BIT(2) 963 #define ICC_SRE_EL2_EN __BIT(3) 964 965 966 /* 967 * GENERIC TIMER REGISTER ACCESS 968 */ 969 static __inline uint32_t 970 gtmr_cntfrq_read(void) 971 { 972 973 return reg_cntfrq_el0_read(); 974 } 975 976 static __inline uint32_t 977 gtmr_cntk_ctl_read(void) 978 { 979 980 return reg_cntkctl_el1_read(); 981 } 982 983 static __inline void 984 gtmr_cntk_ctl_write(uint32_t val) 985 { 986 987 reg_cntkctl_el1_write(val); 988 } 989 990 /* 991 * Counter-timer Virtual Count timer 992 */ 993 static __inline uint64_t 994 gtmr_cntpct_read(void) 995 { 996 997 return reg_cntpct_el0_read(); 998 } 999 1000 static __inline uint64_t 1001 gtmr_cntvct_read(void) 1002 { 1003 1004 return reg_cntvct_el0_read(); 1005 } 1006 1007 /* 1008 * Counter-timer Virtual Timer Control register 1009 */ 1010 static __inline uint32_t 1011 gtmr_cntv_ctl_read(void) 1012 { 1013 1014 return reg_cntv_ctl_el0_read(); 1015 } 1016 1017 static __inline void 1018 gtmr_cntv_ctl_write(uint32_t val) 1019 { 1020 1021 reg_cntv_ctl_el0_write(val); 1022 } 1023 1024 static __inline void 1025 gtmr_cntp_ctl_write(uint32_t val) 1026 { 1027 1028 1029 reg_cntp_ctl_el0_write(val); 1030 } 1031 1032 /* 1033 * Counter-timer Virtual Timer TimerValue register 1034 */ 1035 static __inline uint32_t 1036 gtmr_cntv_tval_read(void) 1037 { 1038 1039 return reg_cntv_tval_el0_read(); 1040 } 1041 1042 static __inline void 1043 gtmr_cntv_tval_write(uint32_t val) 1044 { 1045 1046 reg_cntv_tval_el0_write(val); 1047 } 1048 1049 1050 /* 1051 * Counter-timer Virtual Timer CompareValue register 1052 */ 1053 static __inline uint64_t 1054 gtmr_cntv_cval_read(void) 1055 { 1056 1057 return reg_cntv_cval_el0_read(); 1058 } 1059 1060 #endif /* _AARCH64_ARMREG_H_ */ 1061
Indexes created Wed Oct 01 19:09:53 GMT 2025