armreg.h revision 1.16
1 /* $NetBSD: armreg.h,v 1.16 2018/08/09 10:27:17 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _AARCH64_ARMREG_H_ 33 #define _AARCH64_ARMREG_H_ 34 35 #include <arm/cputypes.h> 36 #include <sys/types.h> 37 38 #define AARCH64REG_READ_INLINE2(regname, regdesc) \ 39 static __inline uint64_t \ 40 reg_##regname##_read(void) \ 41 { \ 42 uint64_t __rv; \ 43 __asm __volatile("mrs %0, " #regdesc : "=r"(__rv)); \ 44 return __rv; \ 45 } 46 47 #define AARCH64REG_WRITE_INLINE2(regname, regdesc) \ 48 static __inline void \ 49 reg_##regname##_write(uint64_t __val) \ 50 { \ 51 __asm __volatile("msr " #regdesc ", %0" :: "r"(__val)); \ 52 } 53 54 #define AARCH64REG_WRITEIMM_INLINE2(regname, regdesc) \ 55 static __inline void \ 56 reg_##regname##_write(uint64_t __val) \ 57 { \ 58 __asm __volatile("msr " #regdesc ", %0" :: "n"(__val)); \ 59 } 60 61 #define AARCH64REG_READ_INLINE(regname) \ 62 AARCH64REG_READ_INLINE2(regname, regname) 63 64 #define AARCH64REG_WRITE_INLINE(regname) \ 65 AARCH64REG_WRITE_INLINE2(regname, regname) 66 67 #define AARCH64REG_WRITEIMM_INLINE(regname) \ 68 AARCH64REG_WRITEIMM_INLINE2(regname, regname) 69 70 #define AARCH64REG_READWRITE_INLINE2(regname, regdesc) \ 71 AARCH64REG_READ_INLINE2(regname, regdesc) \ 72 AARCH64REG_WRITE_INLINE2(regname, regdesc) 73 74 /* 75 * System registers available at EL0 (user) 76 */ 77 AARCH64REG_READ_INLINE(ctr_el0) // Cache Type Register 78 79 #define CTR_EL0_CWG_LINE __BITS(27,24) // Cacheback Writeback Granule 80 #define CTR_EL0_ERG_LINE __BITS(23,20) // Exclusives Reservation Granule 81 #define CTR_EL0_DMIN_LINE __BITS(19,16) // Dcache MIN LINE size (log2 - 2) 82 #define CTR_EL0_L1IP_MASK __BITS(15,14) 83 #define CTR_EL0_L1IP_AIVIVT 1 // ASID-tagged Virtual Index, Virtual Tag 84 #define CTR_EL0_L1IP_VIPT 2 // Virtual Index, Physical Tag 85 #define CTR_EL0_L1IP_PIPT 3 // Physical Index, Physical Tag 86 #define CTR_EL0_IMIN_LINE __BITS(3,0) // Icache MIN LINE size (log2 - 2) 87 88 AARCH64REG_READ_INLINE(dczid_el0) // Data Cache Zero ID Register 89 90 #define DCZID_DZP __BIT(4) // Data Zero Prohibited 91 #define DCZID_BS __BITS(3,0) // Block Size (log2 - 2) 92 93 AARCH64REG_READ_INLINE(fpcr) // Floating Point Control Register 94 AARCH64REG_WRITE_INLINE(fpcr) 95 96 #define FPCR_AHP __BIT(26) // Alternative Half Precision 97 #define FPCR_DN __BIT(25) // Default Nan Control 98 #define FPCR_FZ __BIT(24) // Flush-To-Zero 99 #define FPCR_RMODE __BITS(23,22) // Rounding Mode 100 #define FPCR_RN 0 // Round Nearest 101 #define FPCR_RP 1 // Round towards Plus infinity 102 #define FPCR_RM 2 // Round towards Minus infinity 103 #define FPCR_RZ 3 // Round towards Zero 104 #define FPCR_STRIDE __BITS(21,20) 105 #define FPCR_LEN __BITS(18,16) 106 #define FPCR_IDE __BIT(15) // Input Denormal Exception enable 107 #define FPCR_IXE __BIT(12) // IneXact Exception enable 108 #define FPCR_UFE __BIT(11) // UnderFlow Exception enable 109 #define FPCR_OFE __BIT(10) // OverFlow Exception enable 110 #define FPCR_DZE __BIT(9) // Divide by Zero Exception enable 111 #define FPCR_IOE __BIT(8) // Invalid Operation Exception enable 112 #define FPCR_ESUM 0x1F00 113 114 AARCH64REG_READ_INLINE(fpsr) // Floating Point Status Register 115 AARCH64REG_WRITE_INLINE(fpsr) 116 117 #define FPSR_N32 __BIT(31) // AARCH32 Negative 118 #define FPSR_Z32 __BIT(30) // AARCH32 Zero 119 #define FPSR_C32 __BIT(29) // AARCH32 Carry 120 #define FPSR_V32 __BIT(28) // AARCH32 Overflow 121 #define FPSR_QC __BIT(27) // SIMD Saturation 122 #define FPSR_IDC __BIT(7) // Input Denormal Cumulative status 123 #define FPSR_IXC __BIT(4) // IneXact Cumulative status 124 #define FPSR_UFC __BIT(3) // UnderFlow Cumulative status 125 #define FPSR_OFC __BIT(2) // OverFlow Cumulative status 126 #define FPSR_DZC __BIT(1) // Divide by Zero Cumulative status 127 #define FPSR_IOC __BIT(0) // Invalid Operation Cumulative status 128 #define FPSR_CSUM 0x1F 129 130 AARCH64REG_READ_INLINE(nzcv) // condition codes 131 AARCH64REG_WRITE_INLINE(nzcv) 132 133 #define NZCV_N __BIT(31) // Negative 134 #define NZCV_Z __BIT(30) // Zero 135 #define NZCV_C __BIT(29) // Carry 136 #define NZCV_V __BIT(28) // Overflow 137 138 AARCH64REG_READ_INLINE(tpidr_el0) // Thread Pointer ID Register (RW) 139 AARCH64REG_WRITE_INLINE(tpidr_el0) 140 141 AARCH64REG_READ_INLINE(tpidrro_el0) // Thread Pointer ID Register (RO) 142 143 /* 144 * From here on, these can only be accessed at EL1 (kernel) 145 */ 146 147 /* 148 * These are readonly registers 149 */ 150 AARCH64REG_READ_INLINE(aidr_el1) 151 152 AARCH64REG_READ_INLINE2(cbar_el1, s3_1_c15_c3_0) // Cortex-A57 153 154 #define CBAR_PA __BITS(47,18) 155 156 AARCH64REG_READ_INLINE(ccsidr_el1) 157 158 #define CCSIDR_WT __BIT(31) // Write-through supported 159 #define CCSIDR_WB __BIT(30) // Write-back supported 160 #define CCSIDR_RA __BIT(29) // Read-allocation supported 161 #define CCSIDR_WA __BIT(28) // Write-allocation supported 162 #define CCSIDR_NUMSET __BITS(27,13) // (Number of sets in cache) - 1 163 #define CCSIDR_ASSOC __BITS(12,3) // (Associativity of cache) - 1 164 #define CCSIDR_LINESIZE __BITS(2,0) // Number of bytes in cache line 165 166 AARCH64REG_READ_INLINE(clidr_el1) 167 168 #define CLIDR_LOUU __BITS(29,27) // Level of Unification Uniprocessor 169 #define CLIDR_LOC __BITS(26,24) // Level of Coherency 170 #define CLIDR_LOUIS __BITS(23,21) // Level of Unification InnerShareable*/ 171 #define CLIDR_CTYPE7 __BITS(20,18) // Cache Type field for level7 172 #define CLIDR_CTYPE6 __BITS(17,15) // Cache Type field for level6 173 #define CLIDR_CTYPE5 __BITS(14,12) // Cache Type field for level5 174 #define CLIDR_CTYPE4 __BITS(11,9) // Cache Type field for level4 175 #define CLIDR_CTYPE3 __BITS(8,6) // Cache Type field for level3 176 #define CLIDR_CTYPE2 __BITS(5,3) // Cache Type field for level2 177 #define CLIDR_CTYPE1 __BITS(2,0) // Cache Type field for level1 178 #define CLIDR_TYPE_NOCACHE 0 // No cache 179 #define CLIDR_TYPE_ICACHE 1 // Instruction cache only 180 #define CLIDR_TYPE_DCACHE 2 // Data cache only 181 #define CLIDR_TYPE_IDCACHE 3 // Separate inst and data caches 182 #define CLIDR_TYPE_UNIFIEDCACHE 4 // Unified cache 183 184 AARCH64REG_READ_INLINE(currentel) 185 AARCH64REG_READ_INLINE(id_aa64afr0_el1) 186 AARCH64REG_READ_INLINE(id_aa64afr1_el1) 187 AARCH64REG_READ_INLINE(id_aa64dfr0_el1) 188 189 #define ID_AA64DFR0_EL1_CTX_CMPS __BITS(31,28) 190 #define ID_AA64DFR0_EL1_WRPS __BITS(20,23) 191 #define ID_AA64DFR0_EL1_BRPS __BITS(12,15) 192 #define ID_AA64DFR0_EL1_PMUVER __BITS(8,11) 193 #define ID_AA64DFR0_EL1_PMUVER_NONE 0 194 #define ID_AA64DFR0_EL1_PMUVER_V3 1 195 #define ID_AA64DFR0_EL1_PMUVER_NOV3 2 196 #define ID_AA64DFR0_EL1_TRACEVER __BITS(4,7) 197 #define ID_AA64DFR0_EL1_TRACEVER_NONE 0 198 #define ID_AA64DFR0_EL1_TRACEVER_IMPL 1 199 #define ID_AA64DFR0_EL1_DEBUGVER __BITS(0,3) 200 #define ID_AA64DFR0_EL1_DEBUGVER_V8A 6 201 202 AARCH64REG_READ_INLINE(id_aa64dfr1_el1) 203 204 AARCH64REG_READ_INLINE(id_aa64isar0_el1) 205 206 #define ID_AA64ISAR0_EL1_CRC32 __BITS(19,16) 207 #define ID_AA64ISAR0_EL1_CRC32_NONE 0 208 #define ID_AA64ISAR0_EL1_CRC32_CRC32X 1 209 #define ID_AA64ISAR0_EL1_SHA2 __BITS(15,12) 210 #define ID_AA64ISAR0_EL1_SHA2_NONE 0 211 #define ID_AA64ISAR0_EL1_SHA2_SHA256HSU 1 212 #define ID_AA64ISAR0_EL1_SHA1 __BITS(11,8) 213 #define ID_AA64ISAR0_EL1_SHA1_NONE 0 214 #define ID_AA64ISAR0_EL1_SHA1_SHA1CPMHSU 1 215 #define ID_AA64ISAR0_EL1_AES __BITS(7,4) 216 #define ID_AA64ISAR0_EL1_AES_NONE 0 217 #define ID_AA64ISAR0_EL1_AES_AES 1 218 #define ID_AA64ISAR0_EL1_AES_PMUL 2 219 220 AARCH64REG_READ_INLINE(id_aa64isar1_el1) 221 AARCH64REG_READ_INLINE(id_aa64mmfr0_el1) 222 223 #define ID_AA64MMFR0_EL1_TGRAN4 __BITS(31,28) 224 #define ID_AA64MMFR0_EL1_TGRAN4_4KB 0 225 #define ID_AA64MMFR0_EL1_TGRAN4_NONE 15 226 #define ID_AA64MMFR0_EL1_TGRAN64 __BITS(24,27) 227 #define ID_AA64MMFR0_EL1_TGRAN64_64KB 0 228 #define ID_AA64MMFR0_EL1_TGRAN64_NONE 15 229 #define ID_AA64MMFR0_EL1_TGRAN16 __BITS(20,23) 230 #define ID_AA64MMFR0_EL1_TGRAN16_NONE 0 231 #define ID_AA64MMFR0_EL1_TGRAN16_16KB 1 232 #define ID_AA64MMFR0_EL1_BIGENDEL0 __BITS(16,19) 233 #define ID_AA64MMFR0_EL1_BIGENDEL0_NONE 0 234 #define ID_AA64MMFR0_EL1_BIGENDEL0_MIX 1 235 #define ID_AA64MMFR0_EL1_SNSMEM __BITS(12,15) 236 #define ID_AA64MMFR0_EL1_SNSMEM_NONE 0 237 #define ID_AA64MMFR0_EL1_SNSMEM_SNSMEM 1 238 #define ID_AA64MMFR0_EL1_BIGEND __BITS(8,11) 239 #define ID_AA64MMFR0_EL1_BIGEND_NONE 0 240 #define ID_AA64MMFR0_EL1_BIGEND_MIX 1 241 #define ID_AA64MMFR0_EL1_ASIDBITS __BITS(4,7) 242 #define ID_AA64MMFR0_EL1_ASIDBITS_8BIT 0 243 #define ID_AA64MMFR0_EL1_ASIDBITS_16BIT 2 244 #define ID_AA64MMFR0_EL1_PARANGE __BITS(0,3) 245 #define ID_AA64MMFR0_EL1_PARANGE_4G 0 246 #define ID_AA64MMFR0_EL1_PARANGE_64G 1 247 #define ID_AA64MMFR0_EL1_PARANGE_1T 2 248 #define ID_AA64MMFR0_EL1_PARANGE_4T 3 249 #define ID_AA64MMFR0_EL1_PARANGE_16T 4 250 #define ID_AA64MMFR0_EL1_PARANGE_256T 5 251 252 AARCH64REG_READ_INLINE(id_aa64mmfr1_el1) 253 AARCH64REG_READ_INLINE(id_aa64pfr0_el1) 254 AARCH64REG_READ_INLINE(id_aa64pfr1_el1) 255 AARCH64REG_READ_INLINE(id_pfr1_el1) 256 AARCH64REG_READ_INLINE(isr_el1) 257 AARCH64REG_READ_INLINE(midr_el1) 258 AARCH64REG_READ_INLINE(mpidr_el1) 259 260 #define MPIDR_AFF3 __BITS(32,39) 261 #define MPIDR_U __BIT(30) // 1 = Uni-Processor System 262 #define MPIDR_MT __BIT(24) // 1 = SMT(AFF0 is logical) 263 #define MPIDR_AFF2 __BITS(16,23) 264 #define MPIDR_AFF1 __BITS(8,15) 265 #define MPIDR_AFF0 __BITS(0,7) 266 267 AARCH64REG_READ_INLINE(mvfr0_el1) 268 269 #define MVFR0_FPROUND __BITS(31,28) 270 #define MVFR0_FPROUND_NEAREST 0 271 #define MVFR0_FPROUND_ALL 1 272 #define MVFR0_FPSHVEC __BITS(27,24) 273 #define MVFR0_FPSHVEC_NONE 0 274 #define MVFR0_FPSHVEC_SHVEC 1 275 #define MVFR0_FPSQRT __BITS(23,20) 276 #define MVFR0_FPSQRT_NONE 0 277 #define MVFR0_FPSQRT_VSQRT 1 278 #define MVFR0_FPDIVIDE __BITS(19,16) 279 #define MVFR0_FPDIVIDE_NONE 0 280 #define MVFR0_FPDIVIDE_VDIV 1 281 #define MVFR0_FPTRAP __BITS(15,12) 282 #define MVFR0_FPTRAP_NONE 0 283 #define MVFR0_FPTRAP_TRAP 1 284 #define MVFR0_FPDP __BITS(11,8) 285 #define MVFR0_FPDP_NONE 0 286 #define MVFR0_FPDP_VFPV2 1 287 #define MVFR0_FPDP_VFPV3 2 288 #define MVFR0_FPSP __BITS(7,4) 289 #define MVFR0_FPSP_NONE 0 290 #define MVFR0_FPSP_VFPV2 1 291 #define MVFR0_FPSP_VFPV3 2 292 #define MVFR0_SIMDREG __BITS(3,0) 293 #define MVFR0_SIMDREG_NONE 0 294 #define MVFR0_SIMDREG_16x64 1 295 #define MVFR0_SIMDREG_32x64 2 296 297 AARCH64REG_READ_INLINE(mvfr1_el1) 298 299 #define MVFR1_SIMDFMAC __BITS(31,28) 300 #define MVFR1_SIMDFMAC_NONE 0 301 #define MVFR1_SIMDFMAC_FMAC 1 302 #define MVFR1_FPHP __BITS(27,24) 303 #define MVFR1_FPHP_NONE 0 304 #define MVFR1_FPHP_HALF_SINGLE 1 305 #define MVFR1_FPHP_HALF_DOUBLE 2 306 #define MVFR1_SIMDHP __BITS(23,20) 307 #define MVFR1_SIMDHP_NONE 0 308 #define MVFR1_SIMDHP_HALF 1 309 #define MVFR1_SIMDSP __BITS(19,16) 310 #define MVFR1_SIMDSP_NONE 0 311 #define MVFR1_SIMDSP_SINGLE 1 312 #define MVFR1_SIMDINT __BITS(15,12) 313 #define MVFR1_SIMDINT_NONE 0 314 #define MVFR1_SIMDINT_INTEGER 1 315 #define MVFR1_SIMDLS __BITS(11,8) 316 #define MVFR1_SIMDLS_NONE 0 317 #define MVFR1_SIMDLS_LOADSTORE 1 318 #define MVFR1_FPDNAN __BITS(7,4) 319 #define MVFR1_FPDNAN_NONE 0 320 #define MVFR1_FPDNAN_NAN 1 321 #define MVFR1_FPFTZ __BITS(3,0) 322 #define MVFR1_FPFTZ_NONE 0 323 #define MVFR1_FPFTZ_DENORMAL 1 324 325 AARCH64REG_READ_INLINE(mvfr2_el1) 326 327 #define MVFR2_FPMISC __BITS(7,4) 328 #define MVFR2_FPMISC_NONE 0 329 #define MVFR2_FPMISC_SEL 1 330 #define MVFR2_FPMISC_DROUND 2 331 #define MVFR2_FPMISC_ROUNDINT 3 332 #define MVFR2_FPMISC_MAXMIN 4 333 #define MVFR2_SIMDMISC __BITS(3,0) 334 #define MVFR2_SIMDMISC_NONE 0 335 #define MVFR2_SIMDMISC_DROUND 1 336 #define MVFR2_SIMDMISC_ROUNDINT 2 337 #define MVFR2_SIMDMISC_MAXMIN 3 338 339 AARCH64REG_READ_INLINE(revidr_el1) 340 341 /* 342 * These are read/write registers 343 */ 344 AARCH64REG_READ_INLINE(cpacr_el1) // Coprocessor Access Control Regiser 345 AARCH64REG_WRITE_INLINE(cpacr_el1) 346 347 #define CPACR_TTA __BIT(28) // System Register Access Traps 348 #define CPACR_FPEN __BITS(21,20) 349 #define CPACR_FPEN_NONE __SHIFTIN(0, CPACR_FPEN) 350 #define CPACR_FPEN_EL1 __SHIFTIN(1, CPACR_FPEN) 351 #define CPACR_FPEN_NONE_2 __SHIFTIN(2, CPACR_FPEN) 352 #define CPACR_FPEN_ALL __SHIFTIN(3, CPACR_FPEN) 353 354 AARCH64REG_READ_INLINE(csselr_el1) // Cache Size Selection Register 355 AARCH64REG_WRITE_INLINE(csselr_el1) 356 357 #define CSSELR_LEVEL __BITS(3,1) // Cache level of required cache 358 #define CSSELR_IND __BIT(0) // Instruction not Data bit 359 360 AARCH64REG_READ_INLINE(daif) // Debug Async Irq Fiq mask register 361 AARCH64REG_WRITE_INLINE(daif) 362 AARCH64REG_WRITEIMM_INLINE(daifclr) 363 AARCH64REG_WRITEIMM_INLINE(daifset) 364 365 #define DAIF_D __BIT(9) // Debug Exception Mask 366 #define DAIF_A __BIT(8) // SError Abort Mask 367 #define DAIF_I __BIT(7) // IRQ Mask 368 #define DAIF_F __BIT(6) // FIQ Mask 369 #define DAIF_SETCLR_SHIFT 6 // for daifset/daifclr #imm shift 370 371 AARCH64REG_READ_INLINE(elr_el1) // Exception Link Register 372 AARCH64REG_WRITE_INLINE(elr_el1) 373 374 AARCH64REG_READ_INLINE(esr_el1) // Exception Symdrone Register 375 AARCH64REG_WRITE_INLINE(esr_el1) 376 377 #define ESR_EC __BITS(31,26) // Exception Cause 378 #define ESR_EC_UNKNOWN 0x00 // AXX: Unknown Reason 379 #define ESR_EC_WFX 0x01 // AXX: WFI or WFE instruction execution 380 #define ESR_EC_CP15_RT 0x03 // A32: MCR/MRC access to CP15 !EC=0 381 #define ESR_EC_CP15_RRT 0x04 // A32: MCRR/MRRC access to CP15 !EC=0 382 #define ESR_EC_CP14_RT 0x05 // A32: MCR/MRC access to CP14 383 #define ESR_EC_CP14_DT 0x06 // A32: LDC/STC access to CP14 384 #define ESR_EC_FP_ACCESS 0x07 // AXX: Access to SIMD/FP Registers 385 #define ESR_EC_FPID 0x08 // A32: MCR/MRC access to CP10 !EC=7 386 #define ESR_EC_CP14_RRT 0x0c // A32: MRRC access to CP14 387 #define ESR_EC_ILL_STATE 0x0e // AXX: Illegal Execution State 388 #define ESR_EC_SVC_A32 0x11 // A32: SVC Instruction Execution 389 #define ESR_EC_HVC_A32 0x12 // A32: HVC Instruction Execution 390 #define ESR_EC_SMC_A32 0x13 // A32: SMC Instruction Execution 391 #define ESR_EC_SVC_A64 0x15 // A64: SVC Instruction Execution 392 #define ESR_EC_HVC_A64 0x16 // A64: HVC Instruction Execution 393 #define ESR_EC_SMC_A64 0x17 // A64: SMC Instruction Execution 394 #define ESR_EC_SYS_REG 0x18 // A64: MSR/MRS/SYS instruction (!EC0/1/7) 395 #define ESR_EC_INSN_ABT_EL0 0x20 // AXX: Instruction Abort (EL0) 396 #define ESR_EC_INSN_ABT_EL1 0x21 // AXX: Instruction Abort (EL1) 397 #define ESR_EC_PC_ALIGNMENT 0x22 // AXX: Misaligned PC 398 #define ESR_EC_DATA_ABT_EL0 0x24 // AXX: Data Abort (EL0) 399 #define ESR_EC_DATA_ABT_EL1 0x25 // AXX: Data Abort (EL1) 400 #define ESR_EC_SP_ALIGNMENT 0x26 // AXX: Misaligned SP 401 #define ESR_EC_FP_TRAP_A32 0x28 // A32: FP Exception 402 #define ESR_EC_FP_TRAP_A64 0x2c // A64: FP Exception 403 #define ESR_EC_SERROR 0x2f // AXX: SError Interrupt 404 #define ESR_EC_BRKPNT_EL0 0x30 // AXX: Breakpoint Exception (EL0) 405 #define ESR_EC_BRKPNT_EL1 0x31 // AXX: Breakpoint Exception (EL1) 406 #define ESR_EC_SW_STEP_EL0 0x32 // AXX: Software Step (EL0) 407 #define ESR_EC_SW_STEP_EL1 0x33 // AXX: Software Step (EL1) 408 #define ESR_EC_WTCHPNT_EL0 0x34 // AXX: Watchpoint (EL0) 409 #define ESR_EC_WTCHPNT_EL1 0x35 // AXX: Watchpoint (EL1) 410 #define ESR_EC_BKPT_INSN_A32 0x38 // A32: BKPT Instruction Execution 411 #define ESR_EC_VECTOR_CATCH 0x3a // A32: Vector Catch Exception 412 #define ESR_EC_BKPT_INSN_A64 0x3c // A64: BKPT Instruction Execution 413 #define ESR_IL __BIT(25) // Instruction Length (1=32-bit) 414 #define ESR_ISS __BITS(24,0) // Instruction Specific Syndrome 415 #define ESR_ISS_CV __BIT(24) // common 416 #define ESR_ISS_COND __BITS(23,20) // common 417 #define ESR_ISS_WFX_TRAP_INSN __BIT(0) // for ESR_EC_WFX 418 #define ESR_ISS_MRC_OPC2 __BITS(19,17) // for ESR_EC_CP15_RT 419 #define ESR_ISS_MRC_OPC1 __BITS(16,14) // for ESR_EC_CP15_RT 420 #define ESR_ISS_MRC_CRN __BITS(13,10) // for ESR_EC_CP15_RT 421 #define ESR_ISS_MRC_RT __BITS(9,5) // for ESR_EC_CP15_RT 422 #define ESR_ISS_MRC_CRM __BITS(4,1) // for ESR_EC_CP15_RT 423 #define ESR_ISS_MRC_DIRECTION __BIT(0) // for ESR_EC_CP15_RT 424 #define ESR_ISS_MCRR_OPC1 __BITS(19,16) // for ESR_EC_CP15_RRT 425 #define ESR_ISS_MCRR_RT2 __BITS(14,10) // for ESR_EC_CP15_RRT 426 #define ESR_ISS_MCRR_RT __BITS(9,5) // for ESR_EC_CP15_RRT 427 #define ESR_ISS_MCRR_CRM __BITS(4,1) // for ESR_EC_CP15_RRT 428 #define ESR_ISS_MCRR_DIRECTION __BIT(0) // for ESR_EC_CP15_RRT 429 #define ESR_ISS_HVC_IMM16 __BITS(15,0) // for ESR_EC_{SVC,HVC} 430 // ... 431 #define ESR_ISS_INSNABORT_EA __BIT(9) // for ESC_RC_INSN_ABT_EL[01] 432 #define ESR_ISS_INSNABORT_S1PTW __BIT(7) // for ESC_RC_INSN_ABT_EL[01] 433 #define ESR_ISS_INSNABORT_IFSC __BITS(0,5) // for ESC_RC_INSN_ABT_EL[01] 434 #define ESR_ISS_DATAABORT_ISV __BIT(24) // for ESC_RC_DATA_ABT_EL[01] 435 #define ESR_ISS_DATAABORT_SAS __BITS(23,22) // for ESC_RC_DATA_ABT_EL[01] 436 #define ESR_ISS_DATAABORT_SSE __BIT(21) // for ESC_RC_DATA_ABT_EL[01] 437 #define ESR_ISS_DATAABORT_SRT __BITS(19,16) // for ESC_RC_DATA_ABT_EL[01] 438 #define ESR_ISS_DATAABORT_SF __BIT(15) // for ESC_RC_DATA_ABT_EL[01] 439 #define ESR_ISS_DATAABORT_AR __BIT(14) // for ESC_RC_DATA_ABT_EL[01] 440 #define ESR_ISS_DATAABORT_EA __BIT(9) // for ESC_RC_DATA_ABT_EL[01] 441 #define ESR_ISS_DATAABORT_CM __BIT(8) // for ESC_RC_DATA_ABT_EL[01] 442 #define ESR_ISS_DATAABORT_S1PTW __BIT(7) // for ESC_RC_DATA_ABT_EL[01] 443 #define ESR_ISS_DATAABORT_WnR __BIT(6) // for ESC_RC_DATA_ABT_EL[01] 444 #define ESR_ISS_DATAABORT_DFSC __BITS(0,5) // for ESC_RC_DATA_ABT_EL[01] 445 446 #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_0 0x00 447 #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_1 0x01 448 #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_2 0x02 449 #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_3 0x03 450 #define ESR_ISS_FSC_TRANSLATION_FAULT_0 0x04 451 #define ESR_ISS_FSC_TRANSLATION_FAULT_1 0x05 452 #define ESR_ISS_FSC_TRANSLATION_FAULT_2 0x06 453 #define ESR_ISS_FSC_TRANSLATION_FAULT_3 0x07 454 #define ESR_ISS_FSC_ACCESS_FAULT_0 0x08 455 #define ESR_ISS_FSC_ACCESS_FAULT_1 0x09 456 #define ESR_ISS_FSC_ACCESS_FAULT_2 0x0a 457 #define ESR_ISS_FSC_ACCESS_FAULT_3 0x0b 458 #define ESR_ISS_FSC_PERM_FAULT_0 0x0c 459 #define ESR_ISS_FSC_PERM_FAULT_1 0x0d 460 #define ESR_ISS_FSC_PERM_FAULT_2 0x0e 461 #define ESR_ISS_FSC_PERM_FAULT_3 0x0f 462 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT 0x10 463 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_0 0x14 464 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_1 0x15 465 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_2 0x16 466 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_3 0x17 467 #define ESR_ISS_FSC_SYNC_PARITY_ERROR 0x18 468 #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_0 0x1c 469 #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_1 0x1d 470 #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_2 0x1e 471 #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_3 0x1f 472 #define ESR_ISS_FSC_ALIGNMENT_FAULT 0x21 473 #define ESR_ISS_FSC_TLB_CONFLICT_FAULT 0x30 474 #define ESR_ISS_FSC_LOCKDOWN_ABORT 0x34 475 #define ESR_ISS_FSC_UNSUPPORTED_EXCLUSIVE 0x35 476 #define ESR_ISS_FSC_FIRST_LEVEL_DOMAIN_FAULT 0x3d 477 #define ESR_ISS_FSC_SECOND_LEVEL_DOMAIN_FAULT 0x3e 478 479 480 AARCH64REG_READ_INLINE(far_el1) // Fault Address Register 481 AARCH64REG_WRITE_INLINE(far_el1) 482 483 AARCH64REG_READ_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73 484 AARCH64REG_WRITE_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73 485 486 #define L2CTLR_NUMOFCORE __BITS(25,24) // Number of cores 487 #define L2CTLR_CPUCACHEPROT __BIT(22) // CPU Cache Protection 488 #define L2CTLR_SCUL2CACHEPROT __BIT(21) // SCU-L2 Cache Protection 489 #define L2CTLR_L2_INPUT_LATENCY __BIT(5) // L2 Data RAM input latency 490 #define L2CTLR_L2_OUTPUT_LATENCY __BIT(0) // L2 Data RAM output latency 491 492 AARCH64REG_READ_INLINE(mair_el1) // Memory Attribute Indirection Register 493 AARCH64REG_WRITE_INLINE(mair_el1) 494 495 #define MAIR_ATTR0 __BITS(7,0) 496 #define MAIR_ATTR1 __BITS(15,8) 497 #define MAIR_ATTR2 __BITS(23,16) 498 #define MAIR_ATTR3 __BITS(31,24) 499 #define MAIR_ATTR4 __BITS(39,32) 500 #define MAIR_ATTR5 __BITS(47,40) 501 #define MAIR_ATTR6 __BITS(55,48) 502 #define MAIR_ATTR7 __BITS(63,56) 503 #define MAIR_DEVICE_nGnRnE 0x00 // NoGathering,NoReordering,NoEarlyWriteAck. 504 #define MAIR_NORMAL_NC 0x44 505 #define MAIR_NORMAL_WT 0xbb 506 #define MAIR_NORMAL_WB 0xff 507 508 AARCH64REG_READ_INLINE(par_el1) // Physical Address Register 509 AARCH64REG_WRITE_INLINE(par_el1) 510 511 #define PAR_ATTR __BITS(63,56) // F=0 memory attributes 512 #define PAR_PA __BITS(47,12) // F=0 physical address 513 #define PAR_NS __BIT(9) // F=0 non-secure 514 #define PAR_S __BIT(9) // F=1 failure stage 515 #define PAR_SHA __BITS(8,7) // F=0 shareability attribute 516 #define PAR_SHA_NONE 0 517 #define PAR_SHA_OUTER 2 518 #define PAR_SHA_INNER 3 519 #define PAR_PTW __BIT(8) // F=1 partial table walk 520 #define PAR_FST __BITS(6,1) // F=1 fault status code 521 #define PAR_F __BIT(0) // translation failed 522 523 AARCH64REG_READ_INLINE(rmr_el1) // Reset Management Register 524 AARCH64REG_WRITE_INLINE(rmr_el1) 525 526 AARCH64REG_READ_INLINE(rvbar_el1) // Reset Vector Base Address Register 527 AARCH64REG_WRITE_INLINE(rvbar_el1) 528 529 AARCH64REG_READ_INLINE(sctlr_el1) // System Control Register 530 AARCH64REG_WRITE_INLINE(sctlr_el1) 531 532 #define SCTLR_RES0 0xc8222400 // Reserved ARMv8.0, write 0 533 #define SCTLR_RES1 0x30d00800 // Reserved ARMv8.0, write 1 534 #define SCTLR_M __BIT(0) 535 #define SCTLR_A __BIT(1) 536 #define SCTLR_C __BIT(2) 537 #define SCTLR_SA __BIT(3) 538 #define SCTLR_SA0 __BIT(4) 539 #define SCTLR_CP15BEN __BIT(5) 540 #define SCTLR_THEE __BIT(6) 541 #define SCTLR_ITD __BIT(7) 542 #define SCTLR_SED __BIT(8) 543 #define SCTLR_UMA __BIT(9) 544 #define SCTLR_I __BIT(12) 545 #define SCTLR_DZE __BIT(14) 546 #define SCTLR_UCT __BIT(15) 547 #define SCTLR_nTWI __BIT(16) 548 #define SCTLR_nTWE __BIT(18) 549 #define SCTLR_WXN __BIT(19) 550 #define SCTLR_IESB __BIT(21) 551 #define SCTLR_SPAN __BIT(23) 552 #define SCTLR_EOE __BIT(24) 553 #define SCTLR_EE __BIT(25) 554 #define SCTLR_UCI __BIT(26) 555 #define SCTLR_nTLSMD __BIT(28) 556 #define SCTLR_LSMAOE __BIT(29) 557 558 // current EL stack pointer 559 static __inline uint64_t 560 reg_sp_read(void) 561 { 562 uint64_t __rv; 563 __asm __volatile ("mov %0, sp" : "=r"(__rv)); 564 return __rv; 565 } 566 567 AARCH64REG_READ_INLINE(sp_el0) // EL0 Stack Pointer 568 AARCH64REG_WRITE_INLINE(sp_el0) 569 570 AARCH64REG_READ_INLINE(spsel) // Stack Pointer Select 571 AARCH64REG_WRITE_INLINE(spsel) 572 573 #define SPSEL_SP __BIT(0); // use SP_EL0 at all exception levels 574 575 AARCH64REG_READ_INLINE(spsr_el1) // Saved Program Status Register 576 AARCH64REG_WRITE_INLINE(spsr_el1) 577 578 #define SPSR_NZCV __BITS(31,28) // mask of N Z C V 579 #define SPSR_N __BIT(31) // Negative 580 #define SPSR_Z __BIT(30) // Zero 581 #define SPSR_C __BIT(29) // Carry 582 #define SPSR_V __BIT(28) // oVerflow 583 #define SPSR_A32_Q __BIT(27) // A32: Overflow 584 #define SPSR_A32_J __BIT(24) // A32: Jazelle Mode 585 #define SPSR_A32_IT1 __BIT(23) // A32: IT[1] 586 #define SPSR_A32_IT0 __BIT(22) // A32: IT[0] 587 #define SPSR_SS __BIT(21) // Software Step 588 #define SPSR_IL __BIT(20) // Instruction Length 589 #define SPSR_GE __BITS(19,16) // A32: SIMD GE 590 #define SPSR_IT7 __BIT(15) // A32: IT[7] 591 #define SPSR_IT6 __BIT(14) // A32: IT[6] 592 #define SPSR_IT5 __BIT(13) // A32: IT[5] 593 #define SPSR_IT4 __BIT(12) // A32: IT[4] 594 #define SPSR_IT3 __BIT(11) // A32: IT[3] 595 #define SPSR_IT2 __BIT(10) // A32: IT[2] 596 #define SPSR_A64_D __BIT(9) // A64: Debug Exception Mask 597 #define SPSR_A32_E __BIT(9) // A32: BE Endian Mode 598 #define SPSR_A __BIT(8) // Async abort (SError) Mask 599 #define SPSR_I __BIT(7) // IRQ Mask 600 #define SPSR_F __BIT(6) // FIQ Mask 601 #define SPSR_A32_T __BIT(5) // A32 Thumb Mode 602 #define SPSR_M __BITS(4,0) // Execution State 603 #define SPSR_M_EL3H 0x0d 604 #define SPSR_M_EL3T 0x0c 605 #define SPSR_M_EL2H 0x09 606 #define SPSR_M_EL2T 0x08 607 #define SPSR_M_EL1H 0x05 608 #define SPSR_M_EL1T 0x04 609 #define SPSR_M_EL0T 0x00 610 #define SPSR_M_SYS32 0x1f 611 #define SPSR_M_UND32 0x1b 612 #define SPSR_M_ABT32 0x17 613 #define SPSR_M_SVC32 0x13 614 #define SPSR_M_IRQ32 0x12 615 #define SPSR_M_FIQ32 0x11 616 #define SPSR_M_USR32 0x10 617 618 AARCH64REG_READ_INLINE(tcr_el1) // Translation Control Register 619 AARCH64REG_WRITE_INLINE(tcr_el1) 620 621 #define TCR_PAGE_SIZE1(tcr) (1L << ((1L << __SHIFTOUT(tcr, TCR_TG1)) + 8)) 622 623 AARCH64REG_READ_INLINE(tpidr_el1) // Thread ID Register (EL1) 624 AARCH64REG_WRITE_INLINE(tpidr_el1) 625 626 AARCH64REG_WRITE_INLINE(tpidrro_el0) // Thread ID Register (RO for EL0) 627 628 AARCH64REG_READ_INLINE(ttbr0_el1) // Translation Table Base Register 0 EL1 629 AARCH64REG_WRITE_INLINE(ttbr0_el1) 630 631 AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1 632 AARCH64REG_WRITE_INLINE(ttbr1_el1) 633 634 AARCH64REG_READ_INLINE(vbar_el1) // Vector Base Address Register 635 AARCH64REG_WRITE_INLINE(vbar_el1) 636 637 /* 638 * From here on, these are DEBUG registers 639 */ 640 AARCH64REG_READ_INLINE(dbgbcr0_el1) // Debug Breakpoint Control Register 0 641 AARCH64REG_WRITE_INLINE(dbgbcr0_el1) 642 AARCH64REG_READ_INLINE(dbgbcr1_el1) // Debug Breakpoint Control Register 1 643 AARCH64REG_WRITE_INLINE(dbgbcr1_el1) 644 AARCH64REG_READ_INLINE(dbgbcr2_el1) // Debug Breakpoint Control Register 2 645 AARCH64REG_WRITE_INLINE(dbgbcr2_el1) 646 AARCH64REG_READ_INLINE(dbgbcr3_el1) // Debug Breakpoint Control Register 3 647 AARCH64REG_WRITE_INLINE(dbgbcr3_el1) 648 AARCH64REG_READ_INLINE(dbgbcr4_el1) // Debug Breakpoint Control Register 4 649 AARCH64REG_WRITE_INLINE(dbgbcr4_el1) 650 AARCH64REG_READ_INLINE(dbgbcr5_el1) // Debug Breakpoint Control Register 5 651 AARCH64REG_WRITE_INLINE(dbgbcr5_el1) 652 AARCH64REG_READ_INLINE(dbgbcr6_el1) // Debug Breakpoint Control Register 6 653 AARCH64REG_WRITE_INLINE(dbgbcr6_el1) 654 AARCH64REG_READ_INLINE(dbgbcr7_el1) // Debug Breakpoint Control Register 7 655 AARCH64REG_WRITE_INLINE(dbgbcr7_el1) 656 AARCH64REG_READ_INLINE(dbgbcr8_el1) // Debug Breakpoint Control Register 8 657 AARCH64REG_WRITE_INLINE(dbgbcr8_el1) 658 AARCH64REG_READ_INLINE(dbgbcr9_el1) // Debug Breakpoint Control Register 9 659 AARCH64REG_WRITE_INLINE(dbgbcr9_el1) 660 AARCH64REG_READ_INLINE(dbgbcr10_el1) // Debug Breakpoint Control Register 10 661 AARCH64REG_WRITE_INLINE(dbgbcr10_el1) 662 AARCH64REG_READ_INLINE(dbgbcr11_el1) // Debug Breakpoint Control Register 11 663 AARCH64REG_WRITE_INLINE(dbgbcr11_el1) 664 AARCH64REG_READ_INLINE(dbgbcr12_el1) // Debug Breakpoint Control Register 12 665 AARCH64REG_WRITE_INLINE(dbgbcr12_el1) 666 AARCH64REG_READ_INLINE(dbgbcr13_el1) // Debug Breakpoint Control Register 13 667 AARCH64REG_WRITE_INLINE(dbgbcr13_el1) 668 AARCH64REG_READ_INLINE(dbgbcr14_el1) // Debug Breakpoint Control Register 14 669 AARCH64REG_WRITE_INLINE(dbgbcr14_el1) 670 AARCH64REG_READ_INLINE(dbgbcr15_el1) // Debug Breakpoint Control Register 15 671 AARCH64REG_WRITE_INLINE(dbgbcr15_el1) 672 673 #define DBGBCR_BT __BITS(23,20) 674 #define DBGBCR_LBN __BITS(19,16) 675 #define DBGBCR_SSC __BITS(15,14) 676 #define DBGBCR_HMC __BIT(13) 677 #define DBGBCR_BAS __BITS(8,5) 678 #define DBGBCR_PMC __BITS(2,1) 679 #define DBGBCR_E __BIT(0) 680 681 AARCH64REG_READ_INLINE(dbgbvr0_el1) // Debug Breakpoint Value Register 0 682 AARCH64REG_WRITE_INLINE(dbgbvr0_el1) 683 AARCH64REG_READ_INLINE(dbgbvr1_el1) // Debug Breakpoint Value Register 1 684 AARCH64REG_WRITE_INLINE(dbgbvr1_el1) 685 AARCH64REG_READ_INLINE(dbgbvr2_el1) // Debug Breakpoint Value Register 2 686 AARCH64REG_WRITE_INLINE(dbgbvr2_el1) 687 AARCH64REG_READ_INLINE(dbgbvr3_el1) // Debug Breakpoint Value Register 3 688 AARCH64REG_WRITE_INLINE(dbgbvr3_el1) 689 AARCH64REG_READ_INLINE(dbgbvr4_el1) // Debug Breakpoint Value Register 4 690 AARCH64REG_WRITE_INLINE(dbgbvr4_el1) 691 AARCH64REG_READ_INLINE(dbgbvr5_el1) // Debug Breakpoint Value Register 5 692 AARCH64REG_WRITE_INLINE(dbgbvr5_el1) 693 AARCH64REG_READ_INLINE(dbgbvr6_el1) // Debug Breakpoint Value Register 6 694 AARCH64REG_WRITE_INLINE(dbgbvr6_el1) 695 AARCH64REG_READ_INLINE(dbgbvr7_el1) // Debug Breakpoint Value Register 7 696 AARCH64REG_WRITE_INLINE(dbgbvr7_el1) 697 AARCH64REG_READ_INLINE(dbgbvr8_el1) // Debug Breakpoint Value Register 8 698 AARCH64REG_WRITE_INLINE(dbgbvr8_el1) 699 AARCH64REG_READ_INLINE(dbgbvr9_el1) // Debug Breakpoint Value Register 9 700 AARCH64REG_WRITE_INLINE(dbgbvr9_el1) 701 AARCH64REG_READ_INLINE(dbgbvr10_el1) // Debug Breakpoint Value Register 10 702 AARCH64REG_WRITE_INLINE(dbgbvr10_el1) 703 AARCH64REG_READ_INLINE(dbgbvr11_el1) // Debug Breakpoint Value Register 11 704 AARCH64REG_WRITE_INLINE(dbgbvr11_el1) 705 AARCH64REG_READ_INLINE(dbgbvr12_el1) // Debug Breakpoint Value Register 12 706 AARCH64REG_WRITE_INLINE(dbgbvr12_el1) 707 AARCH64REG_READ_INLINE(dbgbvr13_el1) // Debug Breakpoint Value Register 13 708 AARCH64REG_WRITE_INLINE(dbgbvr13_el1) 709 AARCH64REG_READ_INLINE(dbgbvr14_el1) // Debug Breakpoint Value Register 14 710 AARCH64REG_WRITE_INLINE(dbgbvr14_el1) 711 AARCH64REG_READ_INLINE(dbgbvr15_el1) // Debug Breakpoint Value Register 15 712 AARCH64REG_WRITE_INLINE(dbgbvr15_el1) 713 714 AARCH64REG_READ_INLINE(dbgwcr0_el1) // Debug Watchpoint Control Register 0 715 AARCH64REG_WRITE_INLINE(dbgwcr0_el1) 716 AARCH64REG_READ_INLINE(dbgwcr1_el1) // Debug Watchpoint Control Register 1 717 AARCH64REG_WRITE_INLINE(dbgwcr1_el1) 718 AARCH64REG_READ_INLINE(dbgwcr2_el1) // Debug Watchpoint Control Register 2 719 AARCH64REG_WRITE_INLINE(dbgwcr2_el1) 720 AARCH64REG_READ_INLINE(dbgwcr3_el1) // Debug Watchpoint Control Register 3 721 AARCH64REG_WRITE_INLINE(dbgwcr3_el1) 722 AARCH64REG_READ_INLINE(dbgwcr4_el1) // Debug Watchpoint Control Register 4 723 AARCH64REG_WRITE_INLINE(dbgwcr4_el1) 724 AARCH64REG_READ_INLINE(dbgwcr5_el1) // Debug Watchpoint Control Register 5 725 AARCH64REG_WRITE_INLINE(dbgwcr5_el1) 726 AARCH64REG_READ_INLINE(dbgwcr6_el1) // Debug Watchpoint Control Register 6 727 AARCH64REG_WRITE_INLINE(dbgwcr6_el1) 728 AARCH64REG_READ_INLINE(dbgwcr7_el1) // Debug Watchpoint Control Register 7 729 AARCH64REG_WRITE_INLINE(dbgwcr7_el1) 730 AARCH64REG_READ_INLINE(dbgwcr8_el1) // Debug Watchpoint Control Register 8 731 AARCH64REG_WRITE_INLINE(dbgwcr8_el1) 732 AARCH64REG_READ_INLINE(dbgwcr9_el1) // Debug Watchpoint Control Register 9 733 AARCH64REG_WRITE_INLINE(dbgwcr9_el1) 734 AARCH64REG_READ_INLINE(dbgwcr10_el1) // Debug Watchpoint Control Register 10 735 AARCH64REG_WRITE_INLINE(dbgwcr10_el1) 736 AARCH64REG_READ_INLINE(dbgwcr11_el1) // Debug Watchpoint Control Register 11 737 AARCH64REG_WRITE_INLINE(dbgwcr11_el1) 738 AARCH64REG_READ_INLINE(dbgwcr12_el1) // Debug Watchpoint Control Register 12 739 AARCH64REG_WRITE_INLINE(dbgwcr12_el1) 740 AARCH64REG_READ_INLINE(dbgwcr13_el1) // Debug Watchpoint Control Register 13 741 AARCH64REG_WRITE_INLINE(dbgwcr13_el1) 742 AARCH64REG_READ_INLINE(dbgwcr14_el1) // Debug Watchpoint Control Register 14 743 AARCH64REG_WRITE_INLINE(dbgwcr14_el1) 744 AARCH64REG_READ_INLINE(dbgwcr15_el1) // Debug Watchpoint Control Register 15 745 AARCH64REG_WRITE_INLINE(dbgwcr15_el1) 746 747 #define DBGWCR_MASK __BITS(28,24) 748 #define DBGWCR_WT __BIT(20) 749 #define DBGWCR_LBN __BITS(19,16) 750 #define DBGWCR_SSC __BITS(15,14) 751 #define DBGWCR_HMC __BIT(13) 752 #define DBGWCR_BAS __BITS(12,5) 753 #define DBGWCR_LSC __BITS(4,3) 754 #define DBGWCR_PAC __BITS(2,1) 755 #define DBGWCR_E __BIT(0) 756 757 AARCH64REG_READ_INLINE(dbgwvr0_el1) // Debug Watchpoint Value Register 0 758 AARCH64REG_WRITE_INLINE(dbgwvr0_el1) 759 AARCH64REG_READ_INLINE(dbgwvr1_el1) // Debug Watchpoint Value Register 1 760 AARCH64REG_WRITE_INLINE(dbgwvr1_el1) 761 AARCH64REG_READ_INLINE(dbgwvr2_el1) // Debug Watchpoint Value Register 2 762 AARCH64REG_WRITE_INLINE(dbgwvr2_el1) 763 AARCH64REG_READ_INLINE(dbgwvr3_el1) // Debug Watchpoint Value Register 3 764 AARCH64REG_WRITE_INLINE(dbgwvr3_el1) 765 AARCH64REG_READ_INLINE(dbgwvr4_el1) // Debug Watchpoint Value Register 4 766 AARCH64REG_WRITE_INLINE(dbgwvr4_el1) 767 AARCH64REG_READ_INLINE(dbgwvr5_el1) // Debug Watchpoint Value Register 5 768 AARCH64REG_WRITE_INLINE(dbgwvr5_el1) 769 AARCH64REG_READ_INLINE(dbgwvr6_el1) // Debug Watchpoint Value Register 6 770 AARCH64REG_WRITE_INLINE(dbgwvr6_el1) 771 AARCH64REG_READ_INLINE(dbgwvr7_el1) // Debug Watchpoint Value Register 7 772 AARCH64REG_WRITE_INLINE(dbgwvr7_el1) 773 AARCH64REG_READ_INLINE(dbgwvr8_el1) // Debug Watchpoint Value Register 8 774 AARCH64REG_WRITE_INLINE(dbgwvr8_el1) 775 AARCH64REG_READ_INLINE(dbgwvr9_el1) // Debug Watchpoint Value Register 9 776 AARCH64REG_WRITE_INLINE(dbgwvr9_el1) 777 AARCH64REG_READ_INLINE(dbgwvr10_el1) // Debug Watchpoint Value Register 10 778 AARCH64REG_WRITE_INLINE(dbgwvr10_el1) 779 AARCH64REG_READ_INLINE(dbgwvr11_el1) // Debug Watchpoint Value Register 11 780 AARCH64REG_WRITE_INLINE(dbgwvr11_el1) 781 AARCH64REG_READ_INLINE(dbgwvr12_el1) // Debug Watchpoint Value Register 12 782 AARCH64REG_WRITE_INLINE(dbgwvr12_el1) 783 AARCH64REG_READ_INLINE(dbgwvr13_el1) // Debug Watchpoint Value Register 13 784 AARCH64REG_WRITE_INLINE(dbgwvr13_el1) 785 AARCH64REG_READ_INLINE(dbgwvr14_el1) // Debug Watchpoint Value Register 14 786 AARCH64REG_WRITE_INLINE(dbgwvr14_el1) 787 AARCH64REG_READ_INLINE(dbgwvr15_el1) // Debug Watchpoint Value Register 15 788 AARCH64REG_WRITE_INLINE(dbgwvr15_el1) 789 790 #define DBGWVR_MASK __BITS(64,3) 791 792 793 AARCH64REG_READ_INLINE(mdscr_el1) // Monitor Debug System Control Register 794 AARCH64REG_WRITE_INLINE(mdscr_el1) 795 796 AARCH64REG_WRITE_INLINE(oslar_el1) // OS Lock Access Register 797 798 AARCH64REG_READ_INLINE(oslsr_el1) // OS Lock Status Register 799 800 /* 801 * From here on, these are PMC registers 802 */ 803 804 AARCH64REG_READ_INLINE(pmccfiltr_el0) 805 AARCH64REG_WRITE_INLINE(pmccfiltr_el0) 806 807 #define PMCCFILTR_P __BIT(31) // Don't count cycles in EL1 808 #define PMCCFILTR_U __BIT(30) // Don't count cycles in EL0 809 #define PMCCFILTR_NSK __BIT(29) // Don't count cycles in NS EL1 810 #define PMCCFILTR_NSU __BIT(28) // Don't count cycles in NS EL0 811 #define PMCCFILTR_NSH __BIT(27) // Don't count cycles in NS EL2 812 #define PMCCFILTR_M __BIT(26) // Don't count cycles in EL3 813 814 AARCH64REG_READ_INLINE(pmccntr_el0) 815 816 AARCH64REG_READ_INLINE(pmceid0_el0) 817 AARCH64REG_READ_INLINE(pmceid1_el0) 818 819 AARCH64REG_WRITE_INLINE(pmcntenclr_el0) 820 AARCH64REG_WRITE_INLINE(pmcntenset_el0) 821 822 AARCH64REG_READ_INLINE(pmcr_el0) 823 AARCH64REG_WRITE_INLINE(pmcr_el0) 824 825 #define PMCR_IMP __BITS(31,24) // Implementor code 826 #define PMCR_IDCODE __BITS(23,16) // Identification code 827 #define PMCR_N __BITS(15,11) // Number of event counters 828 #define PMCR_LC __BIT(6) // Long cycle counter enable 829 #define PMCR_DP __BIT(5) // Disable cycle counter when event 830 // counting is prohibited 831 #define PMCR_X __BIT(4) // Enable export of events 832 #define PMCR_D __BIT(3) // Clock divider 833 #define PMCR_C __BIT(2) // Cycle counter reset 834 #define PMCR_P __BIT(1) // Event counter reset 835 #define PMCR_E __BIT(0) // Enable 836 837 838 AARCH64REG_READ_INLINE(pmevcntr1_el0) 839 AARCH64REG_WRITE_INLINE(pmevcntr1_el0) 840 841 AARCH64REG_READ_INLINE(pmevtyper1_el0) 842 AARCH64REG_WRITE_INLINE(pmevtyper1_el0) 843 844 #define PMEVTYPER_P __BIT(31) // Don't count events in EL1 845 #define PMEVTYPER_U __BIT(30) // Don't count events in EL0 846 #define PMEVTYPER_NSK __BIT(29) // Don't count events in NS EL1 847 #define PMEVTYPER_NSU __BIT(28) // Don't count events in NS EL0 848 #define PMEVTYPER_NSH __BIT(27) // Count events in NS EL2 849 #define PMEVTYPER_M __BIT(26) // Don't count events in EL3 850 #define PMEVTYPER_MT __BIT(25) // Count events on all CPUs with same 851 // aff1 level 852 #define PMEVTYPER_EVTCOUNT __BITS(15,0) // Event to count 853 854 AARCH64REG_WRITE_INLINE(pmintenclr_el1) 855 AARCH64REG_WRITE_INLINE(pmintenset_el1) 856 857 AARCH64REG_WRITE_INLINE(pmovsclr_el0) 858 AARCH64REG_READ_INLINE(pmovsset_el0) 859 AARCH64REG_WRITE_INLINE(pmovsset_el0) 860 861 AARCH64REG_WRITE_INLINE(pmselr_el0) 862 863 AARCH64REG_WRITE_INLINE(pmswinc_el0) 864 865 AARCH64REG_READ_INLINE(pmuserenr_el0) 866 AARCH64REG_WRITE_INLINE(pmuserenr_el0) 867 868 AARCH64REG_READ_INLINE(pmxevcntr_el0) 869 AARCH64REG_WRITE_INLINE(pmxevcntr_el0) 870 871 AARCH64REG_READ_INLINE(pmxevtyper_el0) 872 AARCH64REG_WRITE_INLINE(pmxevtyper_el0) 873 874 /* 875 * Generic timer registers 876 */ 877 878 AARCH64REG_READ_INLINE(cntfrq_el0) 879 880 AARCH64REG_READ_INLINE(cnthctl_el2) 881 AARCH64REG_WRITE_INLINE(cnthctl_el2) 882 883 #define CNTHCTL_EVNTDIR __BIT(3) 884 #define CNTHCTL_EVNTEN __BIT(2) 885 #define CNTHCTL_EL1PCEN __BIT(1) 886 #define CNTHCTL_EL1PCTEN __BIT(0) 887 888 AARCH64REG_READ_INLINE(cntkctl_el1) 889 AARCH64REG_WRITE_INLINE(cntkctl_el1) 890 891 #define CNTKCTL_EL0PTEN __BIT(9) // EL0 access for CNTP CVAL/TVAL/CTL 892 #define CNTKCTL_PL0PTEN CNTKCTL_EL0PTEN 893 #define CNTKCTL_EL0VTEN __BIT(8) // EL0 access for CNTV CVAL/TVAL/CTL 894 #define CNTKCTL_PL0VTEN CNTKCTL_EL0VTEN 895 #define CNTKCTL_ELNTI __BITS(7,4) 896 #define CNTKCTL_EVNTDIR __BIT(3) 897 #define CNTKCTL_EVNTEN __BIT(2) 898 #define CNTKCTL_EL0VCTEN __BIT(1) // EL0 access for CNTVCT and CNTFRQ 899 #define CNTKCTL_PL0VCTEN CNTKCTL_EL0VCTEN 900 #define CNTKCTL_EL0PCTEN __BIT(0) // EL0 access for CNTPCT and CNTFRQ 901 #define CNTKCTL_PL0PCTEN CNTKCTL_EL0PCTEN 902 903 AARCH64REG_READ_INLINE(cntp_ctl_el0) 904 AARCH64REG_WRITE_INLINE(cntp_ctl_el0) 905 AARCH64REG_READ_INLINE(cntp_cval_el0) 906 AARCH64REG_WRITE_INLINE(cntp_cval_el0) 907 AARCH64REG_READ_INLINE(cntp_tval_el0) 908 AARCH64REG_WRITE_INLINE(cntp_tval_el0) 909 AARCH64REG_READ_INLINE(cntpct_el0) 910 AARCH64REG_WRITE_INLINE(cntpct_el0) 911 912 AARCH64REG_READ_INLINE(cntps_ctl_el1) 913 AARCH64REG_WRITE_INLINE(cntps_ctl_el1) 914 AARCH64REG_READ_INLINE(cntps_cval_el1) 915 AARCH64REG_WRITE_INLINE(cntps_cval_el1) 916 AARCH64REG_READ_INLINE(cntps_tval_el1) 917 AARCH64REG_WRITE_INLINE(cntps_tval_el1) 918 919 AARCH64REG_READ_INLINE(cntv_ctl_el0) 920 AARCH64REG_WRITE_INLINE(cntv_ctl_el0) 921 AARCH64REG_READ_INLINE(cntv_cval_el0) 922 AARCH64REG_WRITE_INLINE(cntv_cval_el0) 923 AARCH64REG_READ_INLINE(cntv_tval_el0) 924 AARCH64REG_WRITE_INLINE(cntv_tval_el0) 925 AARCH64REG_READ_INLINE(cntvct_el0) 926 AARCH64REG_WRITE_INLINE(cntvct_el0) 927 928 #define CNTCTL_ISTATUS __BIT(2) // Interrupt Asserted 929 #define CNTCTL_IMASK __BIT(1) // Timer Interrupt is Masked 930 #define CNTCTL_ENABLE __BIT(0) // Timer Enabled 931 932 933 // ID_AA64PFR0_EL1: AArch64 Processor Feature Register 0 934 #define ID_AA64PFR0_EL1_GIC __BITS(24,27) // GIC CPU IF 935 #define ID_AA64PFR0_EL1_GIC_SHIFT 24 936 #define ID_AA64PFR0_EL1_GIC_CPUIF_EN 1 937 #define ID_AA64PFR0_EL1_GIC_CPUIF_NONE 0 938 #define ID_AA64PFR0_EL1_ADVSIMD __BITS(23,20) // SIMD 939 #define ID_AA64PFR0_EL1_ADV_SIMD_IMPL 0x0 940 #define ID_AA64PFR0_EL1_ADV_SIMD_NONE 0xf 941 #define ID_AA64PFR0_EL1_FP __BITS(19,16) // FP 942 #define ID_AA64PFR0_EL1_FP_IMPL 0x0 943 #define ID_AA64PFR0_EL1_FP_NONE 0xf 944 #define ID_AA64PFR0_EL1_EL3 __BITS(15,12) // EL3 handling 945 #define ID_AA64PFR0_EL1_EL3_NONE 0 946 #define ID_AA64PFR0_EL1_EL3_64 1 947 #define ID_AA64PFR0_EL1_EL3_64_32 2 948 #define ID_AA64PFR0_EL1_EL2 __BITS(11,8) // EL2 handling 949 #define ID_AA64PFR0_EL1_EL2_NONE 0 950 #define ID_AA64PFR0_EL1_EL2_64 1 951 #define ID_AA64PFR0_EL1_EL2_64_32 2 952 #define ID_AA64PFR0_EL1_EL1 __BITS(7,4) // EL1 handling 953 #define ID_AA64PFR0_EL1_EL1_64 1 954 #define ID_AA64PFR0_EL1_EL1_64_32 2 955 #define ID_AA64PFR0_EL1_EL0 __BITS(3,0) // EL0 handling 956 #define ID_AA64PFR0_EL1_EL0_64 1 957 #define ID_AA64PFR0_EL1_EL0_64_32 2 958 959 /* 960 * GICv3 system registers 961 */ 962 AARCH64REG_READWRITE_INLINE2(icc_sre_el1, s3_0_c12_c12_5) 963 AARCH64REG_READWRITE_INLINE2(icc_ctlr_el1, s3_0_c12_c12_4) 964 AARCH64REG_READWRITE_INLINE2(icc_pmr_el1, s3_0_c4_c6_0) 965 AARCH64REG_READWRITE_INLINE2(icc_bpr0_el1, s3_0_c12_c8_3) 966 AARCH64REG_READWRITE_INLINE2(icc_bpr1_el1, s3_0_c12_c12_3) 967 AARCH64REG_READWRITE_INLINE2(icc_igrpen0_el1, s3_0_c12_c12_6) 968 AARCH64REG_READWRITE_INLINE2(icc_igrpen1_el1, s3_0_c12_c12_7) 969 AARCH64REG_READWRITE_INLINE2(icc_eoir0_el1, s3_0_c12_c8_1) 970 AARCH64REG_READWRITE_INLINE2(icc_eoir1_el1, s3_0_c12_c12_1) 971 AARCH64REG_READWRITE_INLINE2(icc_sgi1r_el1, s3_0_c12_c11_5) 972 AARCH64REG_READ_INLINE2(icc_iar1_el1, s3_0_c12_c12_0) 973 974 // ICC_SRE_EL1: Interrupt Controller System Register Enable register 975 #define ICC_SRE_EL1_DIB __BIT(2) 976 #define ICC_SRE_EL1_DFB __BIT(1) 977 #define ICC_SRE_EL1_SRE __BIT(0) 978 979 // ICC_SRE_EL2: Interrupt Controller System Register Enable register 980 #define ICC_SRE_EL2_EN __BIT(3) 981 #define ICC_SRE_EL2_DIB __BIT(2) 982 #define ICC_SRE_EL2_DFB __BIT(1) 983 #define ICC_SRE_EL2_SRE __BIT(0) 984 985 // ICC_BPR[01]_EL1: Interrupt Controller Binary Point Register 0/1 986 #define ICC_BPR_EL1_BinaryPoint __BITS(2,0) 987 988 // ICC_CTLR_EL1: Interrupt Controller Control Register 989 #define ICC_CTLR_EL1_A3V __BIT(15) 990 #define ICC_CTLR_EL1_SEIS __BIT(14) 991 #define ICC_CTLR_EL1_IDbits __BITS(13,11) 992 #define ICC_CTLR_EL1_PRIbits __BITS(10,8) 993 #define ICC_CTLR_EL1_PMHE __BIT(6) 994 #define ICC_CTLR_EL1_EOImode __BIT(1) 995 #define ICC_CTLR_EL1_CBPR __BIT(0) 996 997 // ICC_IGRPEN[01]_EL1: Interrupt Controller Interrupt Group 0/1 Enable register 998 #define ICC_IGRPEN_EL1_Enable __BIT(0) 999 1000 // ICC_SGI[01]R_EL1: Interrupt Controller Software Generated Interrupt Group 0/1 Register 1001 #define ICC_SGIR_EL1_Aff3 __BITS(55,48) 1002 #define ICC_SGIR_EL1_IRM __BIT(40) 1003 #define ICC_SGIR_EL1_Aff2 __BITS(39,32) 1004 #define ICC_SGIR_EL1_INTID __BITS(27,24) 1005 #define ICC_SGIR_EL1_Aff1 __BITS(23,16) 1006 #define ICC_SGIR_EL1_TargetList __BITS(15,0) 1007 #define ICC_SGIR_EL1_Aff (ICC_SGIR_EL1_Aff3|ICC_SGIR_EL1_Aff2|ICC_SGIR_EL1_Aff1) 1008 1009 // ICC_IAR[01]_EL1: Interrupt Controller Interrupt Acknowledge Register 0/1 1010 #define ICC_IAR_INTID __BITS(23,0) 1011 #define ICC_IAR_INTID_SPURIOUS 1023 1012 1013 /* 1014 * GICv3 REGISTER ACCESS 1015 */ 1016 1017 #define icc_sre_read reg_icc_sre_el1_read 1018 #define icc_sre_write reg_icc_sre_el1_write 1019 #define icc_pmr_write reg_icc_pmr_el1_write 1020 #define icc_bpr0_write reg_icc_bpr0_el1_write 1021 #define icc_bpr1_write reg_icc_bpr1_el1_write 1022 #define icc_ctlr_read reg_icc_ctlr_el1_read 1023 #define icc_ctlr_write reg_icc_ctlr_el1_write 1024 #define icc_igrpen1_write reg_icc_igrpen1_el1_write 1025 #define icc_sgi1r_write reg_icc_sgi1r_el1_write 1026 #define icc_iar1_read reg_icc_iar1_el1_read 1027 #define icc_eoi1r_write reg_icc_eoir1_el1_write 1028 1029 /* 1030 * GENERIC TIMER REGISTER ACCESS 1031 */ 1032 static __inline uint32_t 1033 gtmr_cntfrq_read(void) 1034 { 1035 1036 return reg_cntfrq_el0_read(); 1037 } 1038 1039 static __inline uint32_t 1040 gtmr_cntk_ctl_read(void) 1041 { 1042 1043 return reg_cntkctl_el1_read(); 1044 } 1045 1046 static __inline void 1047 gtmr_cntk_ctl_write(uint32_t val) 1048 { 1049 1050 reg_cntkctl_el1_write(val); 1051 } 1052 1053 /* 1054 * Counter-timer Virtual Count timer 1055 */ 1056 static __inline uint64_t 1057 gtmr_cntpct_read(void) 1058 { 1059 1060 return reg_cntpct_el0_read(); 1061 } 1062 1063 static __inline uint64_t 1064 gtmr_cntvct_read(void) 1065 { 1066 1067 return reg_cntvct_el0_read(); 1068 } 1069 1070 /* 1071 * Counter-timer Virtual Timer Control register 1072 */ 1073 static __inline uint32_t 1074 gtmr_cntv_ctl_read(void) 1075 { 1076 1077 return reg_cntv_ctl_el0_read(); 1078 } 1079 1080 static __inline void 1081 gtmr_cntv_ctl_write(uint32_t val) 1082 { 1083 1084 reg_cntv_ctl_el0_write(val); 1085 } 1086 1087 static __inline void 1088 gtmr_cntp_ctl_write(uint32_t val) 1089 { 1090 1091 1092 reg_cntp_ctl_el0_write(val); 1093 } 1094 1095 /* 1096 * Counter-timer Virtual Timer TimerValue register 1097 */ 1098 static __inline uint32_t 1099 gtmr_cntv_tval_read(void) 1100 { 1101 1102 return reg_cntv_tval_el0_read(); 1103 } 1104 1105 static __inline void 1106 gtmr_cntv_tval_write(uint32_t val) 1107 { 1108 1109 reg_cntv_tval_el0_write(val); 1110 } 1111 1112 1113 /* 1114 * Counter-timer Virtual Timer CompareValue register 1115 */ 1116 static __inline uint64_t 1117 gtmr_cntv_cval_read(void) 1118 { 1119 1120 return reg_cntv_cval_el0_read(); 1121 } 1122 1123 #endif /* _AARCH64_ARMREG_H_ */ 1124
Indexes created Thu Oct 02 14:10:14 GMT 2025