armreg.h revision 1.22
1 /* $NetBSD: armreg.h,v 1.22 2018/12/13 10:44:25 ryo Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _AARCH64_ARMREG_H_ 33 #define _AARCH64_ARMREG_H_ 34 35 #include <arm/cputypes.h> 36 #include <sys/types.h> 37 38 #define AARCH64REG_READ_INLINE2(regname, regdesc) \ 39 static __inline uint64_t \ 40 reg_##regname##_read(void) \ 41 { \ 42 uint64_t __rv; \ 43 __asm __volatile("mrs %0, " #regdesc : "=r"(__rv)); \ 44 return __rv; \ 45 } 46 47 #define AARCH64REG_WRITE_INLINE2(regname, regdesc) \ 48 static __inline void \ 49 reg_##regname##_write(uint64_t __val) \ 50 { \ 51 __asm __volatile("msr " #regdesc ", %0" :: "r"(__val)); \ 52 } 53 54 #define AARCH64REG_WRITEIMM_INLINE2(regname, regdesc) \ 55 static __inline void \ 56 reg_##regname##_write(uint64_t __val) \ 57 { \ 58 __asm __volatile("msr " #regdesc ", %0" :: "n"(__val)); \ 59 } 60 61 #define AARCH64REG_READ_INLINE(regname) \ 62 AARCH64REG_READ_INLINE2(regname, regname) 63 64 #define AARCH64REG_WRITE_INLINE(regname) \ 65 AARCH64REG_WRITE_INLINE2(regname, regname) 66 67 #define AARCH64REG_WRITEIMM_INLINE(regname) \ 68 AARCH64REG_WRITEIMM_INLINE2(regname, regname) 69 70 #define AARCH64REG_READWRITE_INLINE2(regname, regdesc) \ 71 AARCH64REG_READ_INLINE2(regname, regdesc) \ 72 AARCH64REG_WRITE_INLINE2(regname, regdesc) 73 74 /* 75 * System registers available at EL0 (user) 76 */ 77 AARCH64REG_READ_INLINE(ctr_el0) // Cache Type Register 78 79 #define CTR_EL0_CWG_LINE __BITS(27,24) // Cacheback Writeback Granule 80 #define CTR_EL0_ERG_LINE __BITS(23,20) // Exclusives Reservation Granule 81 #define CTR_EL0_DMIN_LINE __BITS(19,16) // Dcache MIN LINE size (log2 - 2) 82 #define CTR_EL0_L1IP_MASK __BITS(15,14) 83 #define CTR_EL0_L1IP_AIVIVT 1 // ASID-tagged Virtual Index, Virtual Tag 84 #define CTR_EL0_L1IP_VIPT 2 // Virtual Index, Physical Tag 85 #define CTR_EL0_L1IP_PIPT 3 // Physical Index, Physical Tag 86 #define CTR_EL0_IMIN_LINE __BITS(3,0) // Icache MIN LINE size (log2 - 2) 87 88 AARCH64REG_READ_INLINE(dczid_el0) // Data Cache Zero ID Register 89 90 #define DCZID_DZP __BIT(4) // Data Zero Prohibited 91 #define DCZID_BS __BITS(3,0) // Block Size (log2 - 2) 92 93 AARCH64REG_READ_INLINE(fpcr) // Floating Point Control Register 94 AARCH64REG_WRITE_INLINE(fpcr) 95 96 #define FPCR_AHP __BIT(26) // Alternative Half Precision 97 #define FPCR_DN __BIT(25) // Default Nan Control 98 #define FPCR_FZ __BIT(24) // Flush-To-Zero 99 #define FPCR_RMODE __BITS(23,22) // Rounding Mode 100 #define FPCR_RN 0 // Round Nearest 101 #define FPCR_RP 1 // Round towards Plus infinity 102 #define FPCR_RM 2 // Round towards Minus infinity 103 #define FPCR_RZ 3 // Round towards Zero 104 #define FPCR_STRIDE __BITS(21,20) 105 #define FPCR_FZ16 __BIT(19) // Flush-To-Zero for FP16 106 #define FPCR_LEN __BITS(18,16) 107 #define FPCR_IDE __BIT(15) // Input Denormal Exception enable 108 #define FPCR_IXE __BIT(12) // IneXact Exception enable 109 #define FPCR_UFE __BIT(11) // UnderFlow Exception enable 110 #define FPCR_OFE __BIT(10) // OverFlow Exception enable 111 #define FPCR_DZE __BIT(9) // Divide by Zero Exception enable 112 #define FPCR_IOE __BIT(8) // Invalid Operation Exception enable 113 #define FPCR_ESUM 0x1F00 114 115 AARCH64REG_READ_INLINE(fpsr) // Floating Point Status Register 116 AARCH64REG_WRITE_INLINE(fpsr) 117 118 #define FPSR_N32 __BIT(31) // AARCH32 Negative 119 #define FPSR_Z32 __BIT(30) // AARCH32 Zero 120 #define FPSR_C32 __BIT(29) // AARCH32 Carry 121 #define FPSR_V32 __BIT(28) // AARCH32 Overflow 122 #define FPSR_QC __BIT(27) // SIMD Saturation 123 #define FPSR_IDC __BIT(7) // Input Denormal Cumulative status 124 #define FPSR_IXC __BIT(4) // IneXact Cumulative status 125 #define FPSR_UFC __BIT(3) // UnderFlow Cumulative status 126 #define FPSR_OFC __BIT(2) // OverFlow Cumulative status 127 #define FPSR_DZC __BIT(1) // Divide by Zero Cumulative status 128 #define FPSR_IOC __BIT(0) // Invalid Operation Cumulative status 129 #define FPSR_CSUM 0x1F 130 131 AARCH64REG_READ_INLINE(nzcv) // condition codes 132 AARCH64REG_WRITE_INLINE(nzcv) 133 134 #define NZCV_N __BIT(31) // Negative 135 #define NZCV_Z __BIT(30) // Zero 136 #define NZCV_C __BIT(29) // Carry 137 #define NZCV_V __BIT(28) // Overflow 138 139 AARCH64REG_READ_INLINE(tpidr_el0) // Thread Pointer ID Register (RW) 140 AARCH64REG_WRITE_INLINE(tpidr_el0) 141 142 AARCH64REG_READ_INLINE(tpidrro_el0) // Thread Pointer ID Register (RO) 143 144 /* 145 * From here on, these can only be accessed at EL1 (kernel) 146 */ 147 148 /* 149 * These are readonly registers 150 */ 151 AARCH64REG_READ_INLINE(aidr_el1) 152 153 AARCH64REG_READ_INLINE2(cbar_el1, s3_1_c15_c3_0) // Cortex-A57 154 155 #define CBAR_PA __BITS(47,18) 156 157 AARCH64REG_READ_INLINE(ccsidr_el1) 158 159 #define CCSIDR_WT __BIT(31) // Write-through supported 160 #define CCSIDR_WB __BIT(30) // Write-back supported 161 #define CCSIDR_RA __BIT(29) // Read-allocation supported 162 #define CCSIDR_WA __BIT(28) // Write-allocation supported 163 #define CCSIDR_NUMSET __BITS(27,13) // (Number of sets in cache) - 1 164 #define CCSIDR_ASSOC __BITS(12,3) // (Associativity of cache) - 1 165 #define CCSIDR_LINESIZE __BITS(2,0) // Number of bytes in cache line 166 167 AARCH64REG_READ_INLINE(clidr_el1) 168 169 #define CLIDR_LOUU __BITS(29,27) // Level of Unification Uniprocessor 170 #define CLIDR_LOC __BITS(26,24) // Level of Coherency 171 #define CLIDR_LOUIS __BITS(23,21) // Level of Unification InnerShareable*/ 172 #define CLIDR_CTYPE7 __BITS(20,18) // Cache Type field for level7 173 #define CLIDR_CTYPE6 __BITS(17,15) // Cache Type field for level6 174 #define CLIDR_CTYPE5 __BITS(14,12) // Cache Type field for level5 175 #define CLIDR_CTYPE4 __BITS(11,9) // Cache Type field for level4 176 #define CLIDR_CTYPE3 __BITS(8,6) // Cache Type field for level3 177 #define CLIDR_CTYPE2 __BITS(5,3) // Cache Type field for level2 178 #define CLIDR_CTYPE1 __BITS(2,0) // Cache Type field for level1 179 #define CLIDR_TYPE_NOCACHE 0 // No cache 180 #define CLIDR_TYPE_ICACHE 1 // Instruction cache only 181 #define CLIDR_TYPE_DCACHE 2 // Data cache only 182 #define CLIDR_TYPE_IDCACHE 3 // Separate inst and data caches 183 #define CLIDR_TYPE_UNIFIEDCACHE 4 // Unified cache 184 185 AARCH64REG_READ_INLINE(currentel) 186 AARCH64REG_READ_INLINE(id_aa64afr0_el1) 187 AARCH64REG_READ_INLINE(id_aa64afr1_el1) 188 AARCH64REG_READ_INLINE(id_aa64dfr0_el1) 189 190 #define ID_AA64DFR0_EL1_CTX_CMPS __BITS(31,28) 191 #define ID_AA64DFR0_EL1_WRPS __BITS(20,23) 192 #define ID_AA64DFR0_EL1_BRPS __BITS(12,15) 193 #define ID_AA64DFR0_EL1_PMUVER __BITS(8,11) 194 #define ID_AA64DFR0_EL1_PMUVER_NONE 0 195 #define ID_AA64DFR0_EL1_PMUVER_V3 1 196 #define ID_AA64DFR0_EL1_PMUVER_NOV3 2 197 #define ID_AA64DFR0_EL1_TRACEVER __BITS(4,7) 198 #define ID_AA64DFR0_EL1_TRACEVER_NONE 0 199 #define ID_AA64DFR0_EL1_TRACEVER_IMPL 1 200 #define ID_AA64DFR0_EL1_DEBUGVER __BITS(0,3) 201 #define ID_AA64DFR0_EL1_DEBUGVER_V8A 6 202 203 AARCH64REG_READ_INLINE(id_aa64dfr1_el1) 204 205 AARCH64REG_READ_INLINE(id_aa64isar0_el1) 206 207 #define ID_AA64ISAR0_EL1_CRC32 __BITS(19,16) 208 #define ID_AA64ISAR0_EL1_CRC32_NONE 0 209 #define ID_AA64ISAR0_EL1_CRC32_CRC32X 1 210 #define ID_AA64ISAR0_EL1_SHA2 __BITS(15,12) 211 #define ID_AA64ISAR0_EL1_SHA2_NONE 0 212 #define ID_AA64ISAR0_EL1_SHA2_SHA256HSU 1 213 #define ID_AA64ISAR0_EL1_SHA1 __BITS(11,8) 214 #define ID_AA64ISAR0_EL1_SHA1_NONE 0 215 #define ID_AA64ISAR0_EL1_SHA1_SHA1CPMHSU 1 216 #define ID_AA64ISAR0_EL1_AES __BITS(7,4) 217 #define ID_AA64ISAR0_EL1_AES_NONE 0 218 #define ID_AA64ISAR0_EL1_AES_AES 1 219 #define ID_AA64ISAR0_EL1_AES_PMUL 2 220 221 AARCH64REG_READ_INLINE(id_aa64isar1_el1) 222 AARCH64REG_READ_INLINE(id_aa64mmfr0_el1) 223 224 #define ID_AA64MMFR0_EL1_TGRAN4 __BITS(31,28) 225 #define ID_AA64MMFR0_EL1_TGRAN4_4KB 0 226 #define ID_AA64MMFR0_EL1_TGRAN4_NONE 15 227 #define ID_AA64MMFR0_EL1_TGRAN64 __BITS(24,27) 228 #define ID_AA64MMFR0_EL1_TGRAN64_64KB 0 229 #define ID_AA64MMFR0_EL1_TGRAN64_NONE 15 230 #define ID_AA64MMFR0_EL1_TGRAN16 __BITS(20,23) 231 #define ID_AA64MMFR0_EL1_TGRAN16_NONE 0 232 #define ID_AA64MMFR0_EL1_TGRAN16_16KB 1 233 #define ID_AA64MMFR0_EL1_BIGENDEL0 __BITS(16,19) 234 #define ID_AA64MMFR0_EL1_BIGENDEL0_NONE 0 235 #define ID_AA64MMFR0_EL1_BIGENDEL0_MIX 1 236 #define ID_AA64MMFR0_EL1_SNSMEM __BITS(12,15) 237 #define ID_AA64MMFR0_EL1_SNSMEM_NONE 0 238 #define ID_AA64MMFR0_EL1_SNSMEM_SNSMEM 1 239 #define ID_AA64MMFR0_EL1_BIGEND __BITS(8,11) 240 #define ID_AA64MMFR0_EL1_BIGEND_NONE 0 241 #define ID_AA64MMFR0_EL1_BIGEND_MIX 1 242 #define ID_AA64MMFR0_EL1_ASIDBITS __BITS(4,7) 243 #define ID_AA64MMFR0_EL1_ASIDBITS_8BIT 0 244 #define ID_AA64MMFR0_EL1_ASIDBITS_16BIT 2 245 #define ID_AA64MMFR0_EL1_PARANGE __BITS(0,3) 246 #define ID_AA64MMFR0_EL1_PARANGE_4G 0 247 #define ID_AA64MMFR0_EL1_PARANGE_64G 1 248 #define ID_AA64MMFR0_EL1_PARANGE_1T 2 249 #define ID_AA64MMFR0_EL1_PARANGE_4T 3 250 #define ID_AA64MMFR0_EL1_PARANGE_16T 4 251 #define ID_AA64MMFR0_EL1_PARANGE_256T 5 252 253 AARCH64REG_READ_INLINE(id_aa64mmfr1_el1) 254 AARCH64REG_READ_INLINE(id_aa64mmfr2_el1) 255 AARCH64REG_READ_INLINE(id_aa64pfr0_el1) 256 AARCH64REG_READ_INLINE(id_aa64pfr1_el1) 257 AARCH64REG_READ_INLINE(id_aa64zfr0_el1) 258 AARCH64REG_READ_INLINE(id_pfr1_el1) 259 AARCH64REG_READ_INLINE(isr_el1) 260 AARCH64REG_READ_INLINE(midr_el1) 261 AARCH64REG_READ_INLINE(mpidr_el1) 262 263 #define MIDR_EL1_IMPL __BITS(31,24) // Implementor 264 #define MIDR_EL1_VARIANT __BITS(23,20) // CPU Variant 265 #define MIDR_EL1_ARCH __BITS(19,16) // Architecture 266 #define MIDR_EL1_PARTNUM __BITS(15,4) // PartNum 267 #define MIDR_EL1_REVISION __BITS(3,0) // Revision 268 269 #define MPIDR_AFF3 __BITS(32,39) 270 #define MPIDR_U __BIT(30) // 1 = Uni-Processor System 271 #define MPIDR_MT __BIT(24) // 1 = SMT(AFF0 is logical) 272 #define MPIDR_AFF2 __BITS(16,23) 273 #define MPIDR_AFF1 __BITS(8,15) 274 #define MPIDR_AFF0 __BITS(0,7) 275 276 AARCH64REG_READ_INLINE(mvfr0_el1) 277 278 #define MVFR0_FPROUND __BITS(31,28) 279 #define MVFR0_FPROUND_NEAREST 0 280 #define MVFR0_FPROUND_ALL 1 281 #define MVFR0_FPSHVEC __BITS(27,24) 282 #define MVFR0_FPSHVEC_NONE 0 283 #define MVFR0_FPSHVEC_SHVEC 1 284 #define MVFR0_FPSQRT __BITS(23,20) 285 #define MVFR0_FPSQRT_NONE 0 286 #define MVFR0_FPSQRT_VSQRT 1 287 #define MVFR0_FPDIVIDE __BITS(19,16) 288 #define MVFR0_FPDIVIDE_NONE 0 289 #define MVFR0_FPDIVIDE_VDIV 1 290 #define MVFR0_FPTRAP __BITS(15,12) 291 #define MVFR0_FPTRAP_NONE 0 292 #define MVFR0_FPTRAP_TRAP 1 293 #define MVFR0_FPDP __BITS(11,8) 294 #define MVFR0_FPDP_NONE 0 295 #define MVFR0_FPDP_VFPV2 1 296 #define MVFR0_FPDP_VFPV3 2 297 #define MVFR0_FPSP __BITS(7,4) 298 #define MVFR0_FPSP_NONE 0 299 #define MVFR0_FPSP_VFPV2 1 300 #define MVFR0_FPSP_VFPV3 2 301 #define MVFR0_SIMDREG __BITS(3,0) 302 #define MVFR0_SIMDREG_NONE 0 303 #define MVFR0_SIMDREG_16x64 1 304 #define MVFR0_SIMDREG_32x64 2 305 306 AARCH64REG_READ_INLINE(mvfr1_el1) 307 308 #define MVFR1_SIMDFMAC __BITS(31,28) 309 #define MVFR1_SIMDFMAC_NONE 0 310 #define MVFR1_SIMDFMAC_FMAC 1 311 #define MVFR1_FPHP __BITS(27,24) 312 #define MVFR1_FPHP_NONE 0 313 #define MVFR1_FPHP_HALF_SINGLE 1 314 #define MVFR1_FPHP_HALF_DOUBLE 2 315 #define MVFR1_FPHP_HALF_ARITH 3 316 #define MVFR1_SIMDHP __BITS(23,20) 317 #define MVFR1_SIMDHP_NONE 0 318 #define MVFR1_SIMDHP_HALF 1 319 #define MVFR1_SIMDHP_HALF_ARITH 3 320 #define MVFR1_SIMDSP __BITS(19,16) 321 #define MVFR1_SIMDSP_NONE 0 322 #define MVFR1_SIMDSP_SINGLE 1 323 #define MVFR1_SIMDINT __BITS(15,12) 324 #define MVFR1_SIMDINT_NONE 0 325 #define MVFR1_SIMDINT_INTEGER 1 326 #define MVFR1_SIMDLS __BITS(11,8) 327 #define MVFR1_SIMDLS_NONE 0 328 #define MVFR1_SIMDLS_LOADSTORE 1 329 #define MVFR1_FPDNAN __BITS(7,4) 330 #define MVFR1_FPDNAN_NONE 0 331 #define MVFR1_FPDNAN_NAN 1 332 #define MVFR1_FPFTZ __BITS(3,0) 333 #define MVFR1_FPFTZ_NONE 0 334 #define MVFR1_FPFTZ_DENORMAL 1 335 336 AARCH64REG_READ_INLINE(mvfr2_el1) 337 338 #define MVFR2_FPMISC __BITS(7,4) 339 #define MVFR2_FPMISC_NONE 0 340 #define MVFR2_FPMISC_SEL 1 341 #define MVFR2_FPMISC_DROUND 2 342 #define MVFR2_FPMISC_ROUNDINT 3 343 #define MVFR2_FPMISC_MAXMIN 4 344 #define MVFR2_SIMDMISC __BITS(3,0) 345 #define MVFR2_SIMDMISC_NONE 0 346 #define MVFR2_SIMDMISC_DROUND 1 347 #define MVFR2_SIMDMISC_ROUNDINT 2 348 #define MVFR2_SIMDMISC_MAXMIN 3 349 350 AARCH64REG_READ_INLINE(revidr_el1) 351 352 /* 353 * These are read/write registers 354 */ 355 AARCH64REG_READ_INLINE(cpacr_el1) // Coprocessor Access Control Regiser 356 AARCH64REG_WRITE_INLINE(cpacr_el1) 357 358 #define CPACR_TTA __BIT(28) // System Register Access Traps 359 #define CPACR_FPEN __BITS(21,20) 360 #define CPACR_FPEN_NONE __SHIFTIN(0, CPACR_FPEN) 361 #define CPACR_FPEN_EL1 __SHIFTIN(1, CPACR_FPEN) 362 #define CPACR_FPEN_NONE_2 __SHIFTIN(2, CPACR_FPEN) 363 #define CPACR_FPEN_ALL __SHIFTIN(3, CPACR_FPEN) 364 365 AARCH64REG_READ_INLINE(csselr_el1) // Cache Size Selection Register 366 AARCH64REG_WRITE_INLINE(csselr_el1) 367 368 #define CSSELR_LEVEL __BITS(3,1) // Cache level of required cache 369 #define CSSELR_IND __BIT(0) // Instruction not Data bit 370 371 AARCH64REG_READ_INLINE(daif) // Debug Async Irq Fiq mask register 372 AARCH64REG_WRITE_INLINE(daif) 373 AARCH64REG_WRITEIMM_INLINE(daifclr) 374 AARCH64REG_WRITEIMM_INLINE(daifset) 375 376 #define DAIF_D __BIT(9) // Debug Exception Mask 377 #define DAIF_A __BIT(8) // SError Abort Mask 378 #define DAIF_I __BIT(7) // IRQ Mask 379 #define DAIF_F __BIT(6) // FIQ Mask 380 #define DAIF_SETCLR_SHIFT 6 // for daifset/daifclr #imm shift 381 382 AARCH64REG_READ_INLINE(elr_el1) // Exception Link Register 383 AARCH64REG_WRITE_INLINE(elr_el1) 384 385 AARCH64REG_READ_INLINE(esr_el1) // Exception Symdrone Register 386 AARCH64REG_WRITE_INLINE(esr_el1) 387 388 #define ESR_EC __BITS(31,26) // Exception Cause 389 #define ESR_EC_UNKNOWN 0x00 // AXX: Unknown Reason 390 #define ESR_EC_WFX 0x01 // AXX: WFI or WFE instruction execution 391 #define ESR_EC_CP15_RT 0x03 // A32: MCR/MRC access to CP15 !EC=0 392 #define ESR_EC_CP15_RRT 0x04 // A32: MCRR/MRRC access to CP15 !EC=0 393 #define ESR_EC_CP14_RT 0x05 // A32: MCR/MRC access to CP14 394 #define ESR_EC_CP14_DT 0x06 // A32: LDC/STC access to CP14 395 #define ESR_EC_FP_ACCESS 0x07 // AXX: Access to SIMD/FP Registers 396 #define ESR_EC_FPID 0x08 // A32: MCR/MRC access to CP10 !EC=7 397 #define ESR_EC_CP14_RRT 0x0c // A32: MRRC access to CP14 398 #define ESR_EC_ILL_STATE 0x0e // AXX: Illegal Execution State 399 #define ESR_EC_SVC_A32 0x11 // A32: SVC Instruction Execution 400 #define ESR_EC_HVC_A32 0x12 // A32: HVC Instruction Execution 401 #define ESR_EC_SMC_A32 0x13 // A32: SMC Instruction Execution 402 #define ESR_EC_SVC_A64 0x15 // A64: SVC Instruction Execution 403 #define ESR_EC_HVC_A64 0x16 // A64: HVC Instruction Execution 404 #define ESR_EC_SMC_A64 0x17 // A64: SMC Instruction Execution 405 #define ESR_EC_SYS_REG 0x18 // A64: MSR/MRS/SYS instruction (!EC0/1/7) 406 #define ESR_EC_INSN_ABT_EL0 0x20 // AXX: Instruction Abort (EL0) 407 #define ESR_EC_INSN_ABT_EL1 0x21 // AXX: Instruction Abort (EL1) 408 #define ESR_EC_PC_ALIGNMENT 0x22 // AXX: Misaligned PC 409 #define ESR_EC_DATA_ABT_EL0 0x24 // AXX: Data Abort (EL0) 410 #define ESR_EC_DATA_ABT_EL1 0x25 // AXX: Data Abort (EL1) 411 #define ESR_EC_SP_ALIGNMENT 0x26 // AXX: Misaligned SP 412 #define ESR_EC_FP_TRAP_A32 0x28 // A32: FP Exception 413 #define ESR_EC_FP_TRAP_A64 0x2c // A64: FP Exception 414 #define ESR_EC_SERROR 0x2f // AXX: SError Interrupt 415 #define ESR_EC_BRKPNT_EL0 0x30 // AXX: Breakpoint Exception (EL0) 416 #define ESR_EC_BRKPNT_EL1 0x31 // AXX: Breakpoint Exception (EL1) 417 #define ESR_EC_SW_STEP_EL0 0x32 // AXX: Software Step (EL0) 418 #define ESR_EC_SW_STEP_EL1 0x33 // AXX: Software Step (EL1) 419 #define ESR_EC_WTCHPNT_EL0 0x34 // AXX: Watchpoint (EL0) 420 #define ESR_EC_WTCHPNT_EL1 0x35 // AXX: Watchpoint (EL1) 421 #define ESR_EC_BKPT_INSN_A32 0x38 // A32: BKPT Instruction Execution 422 #define ESR_EC_VECTOR_CATCH 0x3a // A32: Vector Catch Exception 423 #define ESR_EC_BKPT_INSN_A64 0x3c // A64: BKPT Instruction Execution 424 #define ESR_IL __BIT(25) // Instruction Length (1=32-bit) 425 #define ESR_ISS __BITS(24,0) // Instruction Specific Syndrome 426 #define ESR_ISS_CV __BIT(24) // common 427 #define ESR_ISS_COND __BITS(23,20) // common 428 #define ESR_ISS_WFX_TRAP_INSN __BIT(0) // for ESR_EC_WFX 429 #define ESR_ISS_MRC_OPC2 __BITS(19,17) // for ESR_EC_CP15_RT 430 #define ESR_ISS_MRC_OPC1 __BITS(16,14) // for ESR_EC_CP15_RT 431 #define ESR_ISS_MRC_CRN __BITS(13,10) // for ESR_EC_CP15_RT 432 #define ESR_ISS_MRC_RT __BITS(9,5) // for ESR_EC_CP15_RT 433 #define ESR_ISS_MRC_CRM __BITS(4,1) // for ESR_EC_CP15_RT 434 #define ESR_ISS_MRC_DIRECTION __BIT(0) // for ESR_EC_CP15_RT 435 #define ESR_ISS_MCRR_OPC1 __BITS(19,16) // for ESR_EC_CP15_RRT 436 #define ESR_ISS_MCRR_RT2 __BITS(14,10) // for ESR_EC_CP15_RRT 437 #define ESR_ISS_MCRR_RT __BITS(9,5) // for ESR_EC_CP15_RRT 438 #define ESR_ISS_MCRR_CRM __BITS(4,1) // for ESR_EC_CP15_RRT 439 #define ESR_ISS_MCRR_DIRECTION __BIT(0) // for ESR_EC_CP15_RRT 440 #define ESR_ISS_HVC_IMM16 __BITS(15,0) // for ESR_EC_{SVC,HVC} 441 // ... 442 #define ESR_ISS_INSNABORT_EA __BIT(9) // for ESC_RC_INSN_ABT_EL[01] 443 #define ESR_ISS_INSNABORT_S1PTW __BIT(7) // for ESC_RC_INSN_ABT_EL[01] 444 #define ESR_ISS_INSNABORT_IFSC __BITS(0,5) // for ESC_RC_INSN_ABT_EL[01] 445 #define ESR_ISS_DATAABORT_ISV __BIT(24) // for ESC_RC_DATA_ABT_EL[01] 446 #define ESR_ISS_DATAABORT_SAS __BITS(23,22) // for ESC_RC_DATA_ABT_EL[01] 447 #define ESR_ISS_DATAABORT_SSE __BIT(21) // for ESC_RC_DATA_ABT_EL[01] 448 #define ESR_ISS_DATAABORT_SRT __BITS(19,16) // for ESC_RC_DATA_ABT_EL[01] 449 #define ESR_ISS_DATAABORT_SF __BIT(15) // for ESC_RC_DATA_ABT_EL[01] 450 #define ESR_ISS_DATAABORT_AR __BIT(14) // for ESC_RC_DATA_ABT_EL[01] 451 #define ESR_ISS_DATAABORT_EA __BIT(9) // for ESC_RC_DATA_ABT_EL[01] 452 #define ESR_ISS_DATAABORT_CM __BIT(8) // for ESC_RC_DATA_ABT_EL[01] 453 #define ESR_ISS_DATAABORT_S1PTW __BIT(7) // for ESC_RC_DATA_ABT_EL[01] 454 #define ESR_ISS_DATAABORT_WnR __BIT(6) // for ESC_RC_DATA_ABT_EL[01] 455 #define ESR_ISS_DATAABORT_DFSC __BITS(0,5) // for ESC_RC_DATA_ABT_EL[01] 456 457 #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_0 0x00 458 #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_1 0x01 459 #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_2 0x02 460 #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_3 0x03 461 #define ESR_ISS_FSC_TRANSLATION_FAULT_0 0x04 462 #define ESR_ISS_FSC_TRANSLATION_FAULT_1 0x05 463 #define ESR_ISS_FSC_TRANSLATION_FAULT_2 0x06 464 #define ESR_ISS_FSC_TRANSLATION_FAULT_3 0x07 465 #define ESR_ISS_FSC_ACCESS_FAULT_0 0x08 466 #define ESR_ISS_FSC_ACCESS_FAULT_1 0x09 467 #define ESR_ISS_FSC_ACCESS_FAULT_2 0x0a 468 #define ESR_ISS_FSC_ACCESS_FAULT_3 0x0b 469 #define ESR_ISS_FSC_PERM_FAULT_0 0x0c 470 #define ESR_ISS_FSC_PERM_FAULT_1 0x0d 471 #define ESR_ISS_FSC_PERM_FAULT_2 0x0e 472 #define ESR_ISS_FSC_PERM_FAULT_3 0x0f 473 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT 0x10 474 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_0 0x14 475 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_1 0x15 476 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_2 0x16 477 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_3 0x17 478 #define ESR_ISS_FSC_SYNC_PARITY_ERROR 0x18 479 #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_0 0x1c 480 #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_1 0x1d 481 #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_2 0x1e 482 #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_3 0x1f 483 #define ESR_ISS_FSC_ALIGNMENT_FAULT 0x21 484 #define ESR_ISS_FSC_TLB_CONFLICT_FAULT 0x30 485 #define ESR_ISS_FSC_LOCKDOWN_ABORT 0x34 486 #define ESR_ISS_FSC_UNSUPPORTED_EXCLUSIVE 0x35 487 #define ESR_ISS_FSC_FIRST_LEVEL_DOMAIN_FAULT 0x3d 488 #define ESR_ISS_FSC_SECOND_LEVEL_DOMAIN_FAULT 0x3e 489 490 491 AARCH64REG_READ_INLINE(far_el1) // Fault Address Register 492 AARCH64REG_WRITE_INLINE(far_el1) 493 494 AARCH64REG_READ_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73 495 AARCH64REG_WRITE_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73 496 497 #define L2CTLR_NUMOFCORE __BITS(25,24) // Number of cores 498 #define L2CTLR_CPUCACHEPROT __BIT(22) // CPU Cache Protection 499 #define L2CTLR_SCUL2CACHEPROT __BIT(21) // SCU-L2 Cache Protection 500 #define L2CTLR_L2_INPUT_LATENCY __BIT(5) // L2 Data RAM input latency 501 #define L2CTLR_L2_OUTPUT_LATENCY __BIT(0) // L2 Data RAM output latency 502 503 AARCH64REG_READ_INLINE(mair_el1) // Memory Attribute Indirection Register 504 AARCH64REG_WRITE_INLINE(mair_el1) 505 506 #define MAIR_ATTR0 __BITS(7,0) 507 #define MAIR_ATTR1 __BITS(15,8) 508 #define MAIR_ATTR2 __BITS(23,16) 509 #define MAIR_ATTR3 __BITS(31,24) 510 #define MAIR_ATTR4 __BITS(39,32) 511 #define MAIR_ATTR5 __BITS(47,40) 512 #define MAIR_ATTR6 __BITS(55,48) 513 #define MAIR_ATTR7 __BITS(63,56) 514 #define MAIR_DEVICE_nGnRnE 0x00 // NoGathering,NoReordering,NoEarlyWriteAck. 515 #define MAIR_NORMAL_NC 0x44 516 #define MAIR_NORMAL_WT 0xbb 517 #define MAIR_NORMAL_WB 0xff 518 519 AARCH64REG_READ_INLINE(par_el1) // Physical Address Register 520 AARCH64REG_WRITE_INLINE(par_el1) 521 522 #define PAR_ATTR __BITS(63,56) // F=0 memory attributes 523 #define PAR_PA __BITS(47,12) // F=0 physical address 524 #define PAR_NS __BIT(9) // F=0 non-secure 525 #define PAR_S __BIT(9) // F=1 failure stage 526 #define PAR_SHA __BITS(8,7) // F=0 shareability attribute 527 #define PAR_SHA_NONE 0 528 #define PAR_SHA_OUTER 2 529 #define PAR_SHA_INNER 3 530 #define PAR_PTW __BIT(8) // F=1 partial table walk 531 #define PAR_FST __BITS(6,1) // F=1 fault status code 532 #define PAR_F __BIT(0) // translation failed 533 534 AARCH64REG_READ_INLINE(rmr_el1) // Reset Management Register 535 AARCH64REG_WRITE_INLINE(rmr_el1) 536 537 AARCH64REG_READ_INLINE(rvbar_el1) // Reset Vector Base Address Register 538 AARCH64REG_WRITE_INLINE(rvbar_el1) 539 540 AARCH64REG_READ_INLINE(sctlr_el1) // System Control Register 541 AARCH64REG_WRITE_INLINE(sctlr_el1) 542 543 #define SCTLR_RES0 0xc8222400 // Reserved ARMv8.0, write 0 544 #define SCTLR_RES1 0x30d00800 // Reserved ARMv8.0, write 1 545 #define SCTLR_M __BIT(0) 546 #define SCTLR_A __BIT(1) 547 #define SCTLR_C __BIT(2) 548 #define SCTLR_SA __BIT(3) 549 #define SCTLR_SA0 __BIT(4) 550 #define SCTLR_CP15BEN __BIT(5) 551 #define SCTLR_THEE __BIT(6) 552 #define SCTLR_ITD __BIT(7) 553 #define SCTLR_SED __BIT(8) 554 #define SCTLR_UMA __BIT(9) 555 #define SCTLR_I __BIT(12) 556 #define SCTLR_DZE __BIT(14) 557 #define SCTLR_UCT __BIT(15) 558 #define SCTLR_nTWI __BIT(16) 559 #define SCTLR_nTWE __BIT(18) 560 #define SCTLR_WXN __BIT(19) 561 #define SCTLR_IESB __BIT(21) 562 #define SCTLR_SPAN __BIT(23) 563 #define SCTLR_EOE __BIT(24) 564 #define SCTLR_EE __BIT(25) 565 #define SCTLR_UCI __BIT(26) 566 #define SCTLR_nTLSMD __BIT(28) 567 #define SCTLR_LSMAOE __BIT(29) 568 569 // current EL stack pointer 570 static __inline uint64_t 571 reg_sp_read(void) 572 { 573 uint64_t __rv; 574 __asm __volatile ("mov %0, sp" : "=r"(__rv)); 575 return __rv; 576 } 577 578 AARCH64REG_READ_INLINE(sp_el0) // EL0 Stack Pointer 579 AARCH64REG_WRITE_INLINE(sp_el0) 580 581 AARCH64REG_READ_INLINE(spsel) // Stack Pointer Select 582 AARCH64REG_WRITE_INLINE(spsel) 583 584 #define SPSEL_SP __BIT(0); // use SP_EL0 at all exception levels 585 586 AARCH64REG_READ_INLINE(spsr_el1) // Saved Program Status Register 587 AARCH64REG_WRITE_INLINE(spsr_el1) 588 589 #define SPSR_NZCV __BITS(31,28) // mask of N Z C V 590 #define SPSR_N __BIT(31) // Negative 591 #define SPSR_Z __BIT(30) // Zero 592 #define SPSR_C __BIT(29) // Carry 593 #define SPSR_V __BIT(28) // oVerflow 594 #define SPSR_A32_Q __BIT(27) // A32: Overflow 595 #define SPSR_A32_J __BIT(24) // A32: Jazelle Mode 596 #define SPSR_A32_IT1 __BIT(23) // A32: IT[1] 597 #define SPSR_A32_IT0 __BIT(22) // A32: IT[0] 598 #define SPSR_SS __BIT(21) // Software Step 599 #define SPSR_SS_SHIFT 21 600 #define SPSR_IL __BIT(20) // Instruction Length 601 #define SPSR_GE __BITS(19,16) // A32: SIMD GE 602 #define SPSR_IT7 __BIT(15) // A32: IT[7] 603 #define SPSR_IT6 __BIT(14) // A32: IT[6] 604 #define SPSR_IT5 __BIT(13) // A32: IT[5] 605 #define SPSR_IT4 __BIT(12) // A32: IT[4] 606 #define SPSR_IT3 __BIT(11) // A32: IT[3] 607 #define SPSR_IT2 __BIT(10) // A32: IT[2] 608 #define SPSR_A64_D __BIT(9) // A64: Debug Exception Mask 609 #define SPSR_A32_E __BIT(9) // A32: BE Endian Mode 610 #define SPSR_A __BIT(8) // Async abort (SError) Mask 611 #define SPSR_I __BIT(7) // IRQ Mask 612 #define SPSR_F __BIT(6) // FIQ Mask 613 #define SPSR_A32_T __BIT(5) // A32 Thumb Mode 614 #define SPSR_A32 __BIT(4) // A32 Mode (a part of SPSR_M) 615 #define SPSR_M __BITS(4,0) // Execution State 616 #define SPSR_M_EL3H 0x0d 617 #define SPSR_M_EL3T 0x0c 618 #define SPSR_M_EL2H 0x09 619 #define SPSR_M_EL2T 0x08 620 #define SPSR_M_EL1H 0x05 621 #define SPSR_M_EL1T 0x04 622 #define SPSR_M_EL0T 0x00 623 #define SPSR_M_SYS32 0x1f 624 #define SPSR_M_UND32 0x1b 625 #define SPSR_M_ABT32 0x17 626 #define SPSR_M_SVC32 0x13 627 #define SPSR_M_IRQ32 0x12 628 #define SPSR_M_FIQ32 0x11 629 #define SPSR_M_USR32 0x10 630 631 AARCH64REG_READ_INLINE(tcr_el1) // Translation Control Register 632 AARCH64REG_WRITE_INLINE(tcr_el1) 633 634 #define TCR_PAGE_SIZE1(tcr) (1L << ((1L << __SHIFTOUT(tcr, TCR_TG1)) + 8)) 635 636 AARCH64REG_READ_INLINE(tpidr_el1) // Thread ID Register (EL1) 637 AARCH64REG_WRITE_INLINE(tpidr_el1) 638 639 AARCH64REG_WRITE_INLINE(tpidrro_el0) // Thread ID Register (RO for EL0) 640 641 AARCH64REG_READ_INLINE(ttbr0_el1) // Translation Table Base Register 0 EL1 642 AARCH64REG_WRITE_INLINE(ttbr0_el1) 643 644 AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1 645 AARCH64REG_WRITE_INLINE(ttbr1_el1) 646 647 AARCH64REG_READ_INLINE(vbar_el1) // Vector Base Address Register 648 AARCH64REG_WRITE_INLINE(vbar_el1) 649 650 /* 651 * From here on, these are DEBUG registers 652 */ 653 AARCH64REG_READ_INLINE(dbgbcr0_el1) // Debug Breakpoint Control Register 0 654 AARCH64REG_WRITE_INLINE(dbgbcr0_el1) 655 AARCH64REG_READ_INLINE(dbgbcr1_el1) // Debug Breakpoint Control Register 1 656 AARCH64REG_WRITE_INLINE(dbgbcr1_el1) 657 AARCH64REG_READ_INLINE(dbgbcr2_el1) // Debug Breakpoint Control Register 2 658 AARCH64REG_WRITE_INLINE(dbgbcr2_el1) 659 AARCH64REG_READ_INLINE(dbgbcr3_el1) // Debug Breakpoint Control Register 3 660 AARCH64REG_WRITE_INLINE(dbgbcr3_el1) 661 AARCH64REG_READ_INLINE(dbgbcr4_el1) // Debug Breakpoint Control Register 4 662 AARCH64REG_WRITE_INLINE(dbgbcr4_el1) 663 AARCH64REG_READ_INLINE(dbgbcr5_el1) // Debug Breakpoint Control Register 5 664 AARCH64REG_WRITE_INLINE(dbgbcr5_el1) 665 AARCH64REG_READ_INLINE(dbgbcr6_el1) // Debug Breakpoint Control Register 6 666 AARCH64REG_WRITE_INLINE(dbgbcr6_el1) 667 AARCH64REG_READ_INLINE(dbgbcr7_el1) // Debug Breakpoint Control Register 7 668 AARCH64REG_WRITE_INLINE(dbgbcr7_el1) 669 AARCH64REG_READ_INLINE(dbgbcr8_el1) // Debug Breakpoint Control Register 8 670 AARCH64REG_WRITE_INLINE(dbgbcr8_el1) 671 AARCH64REG_READ_INLINE(dbgbcr9_el1) // Debug Breakpoint Control Register 9 672 AARCH64REG_WRITE_INLINE(dbgbcr9_el1) 673 AARCH64REG_READ_INLINE(dbgbcr10_el1) // Debug Breakpoint Control Register 10 674 AARCH64REG_WRITE_INLINE(dbgbcr10_el1) 675 AARCH64REG_READ_INLINE(dbgbcr11_el1) // Debug Breakpoint Control Register 11 676 AARCH64REG_WRITE_INLINE(dbgbcr11_el1) 677 AARCH64REG_READ_INLINE(dbgbcr12_el1) // Debug Breakpoint Control Register 12 678 AARCH64REG_WRITE_INLINE(dbgbcr12_el1) 679 AARCH64REG_READ_INLINE(dbgbcr13_el1) // Debug Breakpoint Control Register 13 680 AARCH64REG_WRITE_INLINE(dbgbcr13_el1) 681 AARCH64REG_READ_INLINE(dbgbcr14_el1) // Debug Breakpoint Control Register 14 682 AARCH64REG_WRITE_INLINE(dbgbcr14_el1) 683 AARCH64REG_READ_INLINE(dbgbcr15_el1) // Debug Breakpoint Control Register 15 684 AARCH64REG_WRITE_INLINE(dbgbcr15_el1) 685 686 #define DBGBCR_BT __BITS(23,20) 687 #define DBGBCR_LBN __BITS(19,16) 688 #define DBGBCR_SSC __BITS(15,14) 689 #define DBGBCR_HMC __BIT(13) 690 #define DBGBCR_BAS __BITS(8,5) 691 #define DBGBCR_PMC __BITS(2,1) 692 #define DBGBCR_E __BIT(0) 693 694 AARCH64REG_READ_INLINE(dbgbvr0_el1) // Debug Breakpoint Value Register 0 695 AARCH64REG_WRITE_INLINE(dbgbvr0_el1) 696 AARCH64REG_READ_INLINE(dbgbvr1_el1) // Debug Breakpoint Value Register 1 697 AARCH64REG_WRITE_INLINE(dbgbvr1_el1) 698 AARCH64REG_READ_INLINE(dbgbvr2_el1) // Debug Breakpoint Value Register 2 699 AARCH64REG_WRITE_INLINE(dbgbvr2_el1) 700 AARCH64REG_READ_INLINE(dbgbvr3_el1) // Debug Breakpoint Value Register 3 701 AARCH64REG_WRITE_INLINE(dbgbvr3_el1) 702 AARCH64REG_READ_INLINE(dbgbvr4_el1) // Debug Breakpoint Value Register 4 703 AARCH64REG_WRITE_INLINE(dbgbvr4_el1) 704 AARCH64REG_READ_INLINE(dbgbvr5_el1) // Debug Breakpoint Value Register 5 705 AARCH64REG_WRITE_INLINE(dbgbvr5_el1) 706 AARCH64REG_READ_INLINE(dbgbvr6_el1) // Debug Breakpoint Value Register 6 707 AARCH64REG_WRITE_INLINE(dbgbvr6_el1) 708 AARCH64REG_READ_INLINE(dbgbvr7_el1) // Debug Breakpoint Value Register 7 709 AARCH64REG_WRITE_INLINE(dbgbvr7_el1) 710 AARCH64REG_READ_INLINE(dbgbvr8_el1) // Debug Breakpoint Value Register 8 711 AARCH64REG_WRITE_INLINE(dbgbvr8_el1) 712 AARCH64REG_READ_INLINE(dbgbvr9_el1) // Debug Breakpoint Value Register 9 713 AARCH64REG_WRITE_INLINE(dbgbvr9_el1) 714 AARCH64REG_READ_INLINE(dbgbvr10_el1) // Debug Breakpoint Value Register 10 715 AARCH64REG_WRITE_INLINE(dbgbvr10_el1) 716 AARCH64REG_READ_INLINE(dbgbvr11_el1) // Debug Breakpoint Value Register 11 717 AARCH64REG_WRITE_INLINE(dbgbvr11_el1) 718 AARCH64REG_READ_INLINE(dbgbvr12_el1) // Debug Breakpoint Value Register 12 719 AARCH64REG_WRITE_INLINE(dbgbvr12_el1) 720 AARCH64REG_READ_INLINE(dbgbvr13_el1) // Debug Breakpoint Value Register 13 721 AARCH64REG_WRITE_INLINE(dbgbvr13_el1) 722 AARCH64REG_READ_INLINE(dbgbvr14_el1) // Debug Breakpoint Value Register 14 723 AARCH64REG_WRITE_INLINE(dbgbvr14_el1) 724 AARCH64REG_READ_INLINE(dbgbvr15_el1) // Debug Breakpoint Value Register 15 725 AARCH64REG_WRITE_INLINE(dbgbvr15_el1) 726 727 AARCH64REG_READ_INLINE(dbgwcr0_el1) // Debug Watchpoint Control Register 0 728 AARCH64REG_WRITE_INLINE(dbgwcr0_el1) 729 AARCH64REG_READ_INLINE(dbgwcr1_el1) // Debug Watchpoint Control Register 1 730 AARCH64REG_WRITE_INLINE(dbgwcr1_el1) 731 AARCH64REG_READ_INLINE(dbgwcr2_el1) // Debug Watchpoint Control Register 2 732 AARCH64REG_WRITE_INLINE(dbgwcr2_el1) 733 AARCH64REG_READ_INLINE(dbgwcr3_el1) // Debug Watchpoint Control Register 3 734 AARCH64REG_WRITE_INLINE(dbgwcr3_el1) 735 AARCH64REG_READ_INLINE(dbgwcr4_el1) // Debug Watchpoint Control Register 4 736 AARCH64REG_WRITE_INLINE(dbgwcr4_el1) 737 AARCH64REG_READ_INLINE(dbgwcr5_el1) // Debug Watchpoint Control Register 5 738 AARCH64REG_WRITE_INLINE(dbgwcr5_el1) 739 AARCH64REG_READ_INLINE(dbgwcr6_el1) // Debug Watchpoint Control Register 6 740 AARCH64REG_WRITE_INLINE(dbgwcr6_el1) 741 AARCH64REG_READ_INLINE(dbgwcr7_el1) // Debug Watchpoint Control Register 7 742 AARCH64REG_WRITE_INLINE(dbgwcr7_el1) 743 AARCH64REG_READ_INLINE(dbgwcr8_el1) // Debug Watchpoint Control Register 8 744 AARCH64REG_WRITE_INLINE(dbgwcr8_el1) 745 AARCH64REG_READ_INLINE(dbgwcr9_el1) // Debug Watchpoint Control Register 9 746 AARCH64REG_WRITE_INLINE(dbgwcr9_el1) 747 AARCH64REG_READ_INLINE(dbgwcr10_el1) // Debug Watchpoint Control Register 10 748 AARCH64REG_WRITE_INLINE(dbgwcr10_el1) 749 AARCH64REG_READ_INLINE(dbgwcr11_el1) // Debug Watchpoint Control Register 11 750 AARCH64REG_WRITE_INLINE(dbgwcr11_el1) 751 AARCH64REG_READ_INLINE(dbgwcr12_el1) // Debug Watchpoint Control Register 12 752 AARCH64REG_WRITE_INLINE(dbgwcr12_el1) 753 AARCH64REG_READ_INLINE(dbgwcr13_el1) // Debug Watchpoint Control Register 13 754 AARCH64REG_WRITE_INLINE(dbgwcr13_el1) 755 AARCH64REG_READ_INLINE(dbgwcr14_el1) // Debug Watchpoint Control Register 14 756 AARCH64REG_WRITE_INLINE(dbgwcr14_el1) 757 AARCH64REG_READ_INLINE(dbgwcr15_el1) // Debug Watchpoint Control Register 15 758 AARCH64REG_WRITE_INLINE(dbgwcr15_el1) 759 760 #define DBGWCR_MASK __BITS(28,24) 761 #define DBGWCR_WT __BIT(20) 762 #define DBGWCR_LBN __BITS(19,16) 763 #define DBGWCR_SSC __BITS(15,14) 764 #define DBGWCR_HMC __BIT(13) 765 #define DBGWCR_BAS __BITS(12,5) 766 #define DBGWCR_LSC __BITS(4,3) 767 #define DBGWCR_PAC __BITS(2,1) 768 #define DBGWCR_E __BIT(0) 769 770 AARCH64REG_READ_INLINE(dbgwvr0_el1) // Debug Watchpoint Value Register 0 771 AARCH64REG_WRITE_INLINE(dbgwvr0_el1) 772 AARCH64REG_READ_INLINE(dbgwvr1_el1) // Debug Watchpoint Value Register 1 773 AARCH64REG_WRITE_INLINE(dbgwvr1_el1) 774 AARCH64REG_READ_INLINE(dbgwvr2_el1) // Debug Watchpoint Value Register 2 775 AARCH64REG_WRITE_INLINE(dbgwvr2_el1) 776 AARCH64REG_READ_INLINE(dbgwvr3_el1) // Debug Watchpoint Value Register 3 777 AARCH64REG_WRITE_INLINE(dbgwvr3_el1) 778 AARCH64REG_READ_INLINE(dbgwvr4_el1) // Debug Watchpoint Value Register 4 779 AARCH64REG_WRITE_INLINE(dbgwvr4_el1) 780 AARCH64REG_READ_INLINE(dbgwvr5_el1) // Debug Watchpoint Value Register 5 781 AARCH64REG_WRITE_INLINE(dbgwvr5_el1) 782 AARCH64REG_READ_INLINE(dbgwvr6_el1) // Debug Watchpoint Value Register 6 783 AARCH64REG_WRITE_INLINE(dbgwvr6_el1) 784 AARCH64REG_READ_INLINE(dbgwvr7_el1) // Debug Watchpoint Value Register 7 785 AARCH64REG_WRITE_INLINE(dbgwvr7_el1) 786 AARCH64REG_READ_INLINE(dbgwvr8_el1) // Debug Watchpoint Value Register 8 787 AARCH64REG_WRITE_INLINE(dbgwvr8_el1) 788 AARCH64REG_READ_INLINE(dbgwvr9_el1) // Debug Watchpoint Value Register 9 789 AARCH64REG_WRITE_INLINE(dbgwvr9_el1) 790 AARCH64REG_READ_INLINE(dbgwvr10_el1) // Debug Watchpoint Value Register 10 791 AARCH64REG_WRITE_INLINE(dbgwvr10_el1) 792 AARCH64REG_READ_INLINE(dbgwvr11_el1) // Debug Watchpoint Value Register 11 793 AARCH64REG_WRITE_INLINE(dbgwvr11_el1) 794 AARCH64REG_READ_INLINE(dbgwvr12_el1) // Debug Watchpoint Value Register 12 795 AARCH64REG_WRITE_INLINE(dbgwvr12_el1) 796 AARCH64REG_READ_INLINE(dbgwvr13_el1) // Debug Watchpoint Value Register 13 797 AARCH64REG_WRITE_INLINE(dbgwvr13_el1) 798 AARCH64REG_READ_INLINE(dbgwvr14_el1) // Debug Watchpoint Value Register 14 799 AARCH64REG_WRITE_INLINE(dbgwvr14_el1) 800 AARCH64REG_READ_INLINE(dbgwvr15_el1) // Debug Watchpoint Value Register 15 801 AARCH64REG_WRITE_INLINE(dbgwvr15_el1) 802 803 #define DBGWVR_MASK __BITS(64,3) 804 805 806 AARCH64REG_READ_INLINE(mdscr_el1) // Monitor Debug System Control Register 807 AARCH64REG_WRITE_INLINE(mdscr_el1) 808 809 #define MDSCR_RXFULL __BIT(30) // for EDSCR.RXfull 810 #define MDSCR_TXFULL __BIT(29) // for EDSCR.TXfull 811 #define MDSCR_RXO __BIT(27) // for EDSCR.RXO 812 #define MDSCR_TXU __BIT(26) // for EDSCR.TXU 813 #define MDSCR_INTDIS __BITS(32,22) // for EDSCR.INTdis 814 #define MDSCR_TDA __BIT(21) // for EDSCR.TDA 815 #define MDSCR_MDE __BIT(15) // Monitor debug events 816 #define MDSCR_HDE __BIT(14) // for EDSCR.HDE 817 #define MDSCR_KDE __BIT(13) // Local debug enable 818 #define MDSCR_TDCC __BIT(12) // Trap Debug CommCh access 819 #define MDSCR_ERR __BIT(6) // for EDSCR.ERR 820 #define MDSCR_SS __BIT(0) // Software step 821 822 AARCH64REG_WRITE_INLINE(oslar_el1) // OS Lock Access Register 823 824 AARCH64REG_READ_INLINE(oslsr_el1) // OS Lock Status Register 825 826 /* 827 * From here on, these are PMC registers 828 */ 829 830 AARCH64REG_READ_INLINE(pmccfiltr_el0) 831 AARCH64REG_WRITE_INLINE(pmccfiltr_el0) 832 833 #define PMCCFILTR_P __BIT(31) // Don't count cycles in EL1 834 #define PMCCFILTR_U __BIT(30) // Don't count cycles in EL0 835 #define PMCCFILTR_NSK __BIT(29) // Don't count cycles in NS EL1 836 #define PMCCFILTR_NSU __BIT(28) // Don't count cycles in NS EL0 837 #define PMCCFILTR_NSH __BIT(27) // Don't count cycles in NS EL2 838 #define PMCCFILTR_M __BIT(26) // Don't count cycles in EL3 839 840 AARCH64REG_READ_INLINE(pmccntr_el0) 841 842 AARCH64REG_READ_INLINE(pmceid0_el0) 843 AARCH64REG_READ_INLINE(pmceid1_el0) 844 845 AARCH64REG_WRITE_INLINE(pmcntenclr_el0) 846 AARCH64REG_WRITE_INLINE(pmcntenset_el0) 847 848 AARCH64REG_READ_INLINE(pmcr_el0) 849 AARCH64REG_WRITE_INLINE(pmcr_el0) 850 851 #define PMCR_IMP __BITS(31,24) // Implementor code 852 #define PMCR_IDCODE __BITS(23,16) // Identification code 853 #define PMCR_N __BITS(15,11) // Number of event counters 854 #define PMCR_LC __BIT(6) // Long cycle counter enable 855 #define PMCR_DP __BIT(5) // Disable cycle counter when event 856 // counting is prohibited 857 #define PMCR_X __BIT(4) // Enable export of events 858 #define PMCR_D __BIT(3) // Clock divider 859 #define PMCR_C __BIT(2) // Cycle counter reset 860 #define PMCR_P __BIT(1) // Event counter reset 861 #define PMCR_E __BIT(0) // Enable 862 863 864 AARCH64REG_READ_INLINE(pmevcntr1_el0) 865 AARCH64REG_WRITE_INLINE(pmevcntr1_el0) 866 867 AARCH64REG_READ_INLINE(pmevtyper1_el0) 868 AARCH64REG_WRITE_INLINE(pmevtyper1_el0) 869 870 #define PMEVTYPER_P __BIT(31) // Don't count events in EL1 871 #define PMEVTYPER_U __BIT(30) // Don't count events in EL0 872 #define PMEVTYPER_NSK __BIT(29) // Don't count events in NS EL1 873 #define PMEVTYPER_NSU __BIT(28) // Don't count events in NS EL0 874 #define PMEVTYPER_NSH __BIT(27) // Count events in NS EL2 875 #define PMEVTYPER_M __BIT(26) // Don't count events in EL3 876 #define PMEVTYPER_MT __BIT(25) // Count events on all CPUs with same 877 // aff1 level 878 #define PMEVTYPER_EVTCOUNT __BITS(15,0) // Event to count 879 880 AARCH64REG_WRITE_INLINE(pmintenclr_el1) 881 AARCH64REG_WRITE_INLINE(pmintenset_el1) 882 883 AARCH64REG_WRITE_INLINE(pmovsclr_el0) 884 AARCH64REG_READ_INLINE(pmovsset_el0) 885 AARCH64REG_WRITE_INLINE(pmovsset_el0) 886 887 AARCH64REG_WRITE_INLINE(pmselr_el0) 888 889 AARCH64REG_WRITE_INLINE(pmswinc_el0) 890 891 AARCH64REG_READ_INLINE(pmuserenr_el0) 892 AARCH64REG_WRITE_INLINE(pmuserenr_el0) 893 894 AARCH64REG_READ_INLINE(pmxevcntr_el0) 895 AARCH64REG_WRITE_INLINE(pmxevcntr_el0) 896 897 AARCH64REG_READ_INLINE(pmxevtyper_el0) 898 AARCH64REG_WRITE_INLINE(pmxevtyper_el0) 899 900 /* 901 * Generic timer registers 902 */ 903 904 AARCH64REG_READ_INLINE(cntfrq_el0) 905 906 AARCH64REG_READ_INLINE(cnthctl_el2) 907 AARCH64REG_WRITE_INLINE(cnthctl_el2) 908 909 #define CNTHCTL_EVNTDIR __BIT(3) 910 #define CNTHCTL_EVNTEN __BIT(2) 911 #define CNTHCTL_EL1PCEN __BIT(1) 912 #define CNTHCTL_EL1PCTEN __BIT(0) 913 914 AARCH64REG_READ_INLINE(cntkctl_el1) 915 AARCH64REG_WRITE_INLINE(cntkctl_el1) 916 917 #define CNTKCTL_EL0PTEN __BIT(9) // EL0 access for CNTP CVAL/TVAL/CTL 918 #define CNTKCTL_PL0PTEN CNTKCTL_EL0PTEN 919 #define CNTKCTL_EL0VTEN __BIT(8) // EL0 access for CNTV CVAL/TVAL/CTL 920 #define CNTKCTL_PL0VTEN CNTKCTL_EL0VTEN 921 #define CNTKCTL_ELNTI __BITS(7,4) 922 #define CNTKCTL_EVNTDIR __BIT(3) 923 #define CNTKCTL_EVNTEN __BIT(2) 924 #define CNTKCTL_EL0VCTEN __BIT(1) // EL0 access for CNTVCT and CNTFRQ 925 #define CNTKCTL_PL0VCTEN CNTKCTL_EL0VCTEN 926 #define CNTKCTL_EL0PCTEN __BIT(0) // EL0 access for CNTPCT and CNTFRQ 927 #define CNTKCTL_PL0PCTEN CNTKCTL_EL0PCTEN 928 929 AARCH64REG_READ_INLINE(cntp_ctl_el0) 930 AARCH64REG_WRITE_INLINE(cntp_ctl_el0) 931 AARCH64REG_READ_INLINE(cntp_cval_el0) 932 AARCH64REG_WRITE_INLINE(cntp_cval_el0) 933 AARCH64REG_READ_INLINE(cntp_tval_el0) 934 AARCH64REG_WRITE_INLINE(cntp_tval_el0) 935 AARCH64REG_READ_INLINE(cntpct_el0) 936 AARCH64REG_WRITE_INLINE(cntpct_el0) 937 938 AARCH64REG_READ_INLINE(cntps_ctl_el1) 939 AARCH64REG_WRITE_INLINE(cntps_ctl_el1) 940 AARCH64REG_READ_INLINE(cntps_cval_el1) 941 AARCH64REG_WRITE_INLINE(cntps_cval_el1) 942 AARCH64REG_READ_INLINE(cntps_tval_el1) 943 AARCH64REG_WRITE_INLINE(cntps_tval_el1) 944 945 AARCH64REG_READ_INLINE(cntv_ctl_el0) 946 AARCH64REG_WRITE_INLINE(cntv_ctl_el0) 947 AARCH64REG_READ_INLINE(cntv_cval_el0) 948 AARCH64REG_WRITE_INLINE(cntv_cval_el0) 949 AARCH64REG_READ_INLINE(cntv_tval_el0) 950 AARCH64REG_WRITE_INLINE(cntv_tval_el0) 951 AARCH64REG_READ_INLINE(cntvct_el0) 952 AARCH64REG_WRITE_INLINE(cntvct_el0) 953 954 #define CNTCTL_ISTATUS __BIT(2) // Interrupt Asserted 955 #define CNTCTL_IMASK __BIT(1) // Timer Interrupt is Masked 956 #define CNTCTL_ENABLE __BIT(0) // Timer Enabled 957 958 // ID_AA64PFR0_EL1: AArch64 Processor Feature Register 0 959 #define ID_AA64PFR0_EL1_GIC __BITS(24,27) // GIC CPU IF 960 #define ID_AA64PFR0_EL1_GIC_SHIFT 24 961 #define ID_AA64PFR0_EL1_GIC_CPUIF_EN 1 962 #define ID_AA64PFR0_EL1_GIC_CPUIF_NONE 0 963 #define ID_AA64PFR0_EL1_ADVSIMD __BITS(23,20) // SIMD 964 #define ID_AA64PFR0_EL1_ADV_SIMD_IMPL 0x0 965 #define ID_AA64PFR0_EL1_ADV_SIMD_NONE 0xf 966 #define ID_AA64PFR0_EL1_FP __BITS(19,16) // FP 967 #define ID_AA64PFR0_EL1_FP_IMPL 0x0 968 #define ID_AA64PFR0_EL1_FP_NONE 0xf 969 #define ID_AA64PFR0_EL1_EL3 __BITS(15,12) // EL3 handling 970 #define ID_AA64PFR0_EL1_EL3_NONE 0 971 #define ID_AA64PFR0_EL1_EL3_64 1 972 #define ID_AA64PFR0_EL1_EL3_64_32 2 973 #define ID_AA64PFR0_EL1_EL2 __BITS(11,8) // EL2 handling 974 #define ID_AA64PFR0_EL1_EL2_NONE 0 975 #define ID_AA64PFR0_EL1_EL2_64 1 976 #define ID_AA64PFR0_EL1_EL2_64_32 2 977 #define ID_AA64PFR0_EL1_EL1 __BITS(7,4) // EL1 handling 978 #define ID_AA64PFR0_EL1_EL1_64 1 979 #define ID_AA64PFR0_EL1_EL1_64_32 2 980 #define ID_AA64PFR0_EL1_EL0 __BITS(3,0) // EL0 handling 981 #define ID_AA64PFR0_EL1_EL0_64 1 982 #define ID_AA64PFR0_EL1_EL0_64_32 2 983 984 /* 985 * GICv3 system registers 986 */ 987 AARCH64REG_READWRITE_INLINE2(icc_sre_el1, s3_0_c12_c12_5) 988 AARCH64REG_READWRITE_INLINE2(icc_ctlr_el1, s3_0_c12_c12_4) 989 AARCH64REG_READWRITE_INLINE2(icc_pmr_el1, s3_0_c4_c6_0) 990 AARCH64REG_READWRITE_INLINE2(icc_bpr0_el1, s3_0_c12_c8_3) 991 AARCH64REG_READWRITE_INLINE2(icc_bpr1_el1, s3_0_c12_c12_3) 992 AARCH64REG_READWRITE_INLINE2(icc_igrpen0_el1, s3_0_c12_c12_6) 993 AARCH64REG_READWRITE_INLINE2(icc_igrpen1_el1, s3_0_c12_c12_7) 994 AARCH64REG_READWRITE_INLINE2(icc_eoir0_el1, s3_0_c12_c8_1) 995 AARCH64REG_READWRITE_INLINE2(icc_eoir1_el1, s3_0_c12_c12_1) 996 AARCH64REG_READWRITE_INLINE2(icc_sgi1r_el1, s3_0_c12_c11_5) 997 AARCH64REG_READ_INLINE2(icc_iar1_el1, s3_0_c12_c12_0) 998 999 // ICC_SRE_EL1: Interrupt Controller System Register Enable register 1000 #define ICC_SRE_EL1_DIB __BIT(2) 1001 #define ICC_SRE_EL1_DFB __BIT(1) 1002 #define ICC_SRE_EL1_SRE __BIT(0) 1003 1004 // ICC_SRE_EL2: Interrupt Controller System Register Enable register 1005 #define ICC_SRE_EL2_EN __BIT(3) 1006 #define ICC_SRE_EL2_DIB __BIT(2) 1007 #define ICC_SRE_EL2_DFB __BIT(1) 1008 #define ICC_SRE_EL2_SRE __BIT(0) 1009 1010 // ICC_BPR[01]_EL1: Interrupt Controller Binary Point Register 0/1 1011 #define ICC_BPR_EL1_BinaryPoint __BITS(2,0) 1012 1013 // ICC_CTLR_EL1: Interrupt Controller Control Register 1014 #define ICC_CTLR_EL1_A3V __BIT(15) 1015 #define ICC_CTLR_EL1_SEIS __BIT(14) 1016 #define ICC_CTLR_EL1_IDbits __BITS(13,11) 1017 #define ICC_CTLR_EL1_PRIbits __BITS(10,8) 1018 #define ICC_CTLR_EL1_PMHE __BIT(6) 1019 #define ICC_CTLR_EL1_EOImode __BIT(1) 1020 #define ICC_CTLR_EL1_CBPR __BIT(0) 1021 1022 // ICC_IGRPEN[01]_EL1: Interrupt Controller Interrupt Group 0/1 Enable register 1023 #define ICC_IGRPEN_EL1_Enable __BIT(0) 1024 1025 // ICC_SGI[01]R_EL1: Interrupt Controller Software Generated Interrupt Group 0/1 Register 1026 #define ICC_SGIR_EL1_Aff3 __BITS(55,48) 1027 #define ICC_SGIR_EL1_IRM __BIT(40) 1028 #define ICC_SGIR_EL1_Aff2 __BITS(39,32) 1029 #define ICC_SGIR_EL1_INTID __BITS(27,24) 1030 #define ICC_SGIR_EL1_Aff1 __BITS(23,16) 1031 #define ICC_SGIR_EL1_TargetList __BITS(15,0) 1032 #define ICC_SGIR_EL1_Aff (ICC_SGIR_EL1_Aff3|ICC_SGIR_EL1_Aff2|ICC_SGIR_EL1_Aff1) 1033 1034 // ICC_IAR[01]_EL1: Interrupt Controller Interrupt Acknowledge Register 0/1 1035 #define ICC_IAR_INTID __BITS(23,0) 1036 #define ICC_IAR_INTID_SPURIOUS 1023 1037 1038 /* 1039 * GICv3 REGISTER ACCESS 1040 */ 1041 1042 #define icc_sre_read reg_icc_sre_el1_read 1043 #define icc_sre_write reg_icc_sre_el1_write 1044 #define icc_pmr_write reg_icc_pmr_el1_write 1045 #define icc_bpr0_write reg_icc_bpr0_el1_write 1046 #define icc_bpr1_write reg_icc_bpr1_el1_write 1047 #define icc_ctlr_read reg_icc_ctlr_el1_read 1048 #define icc_ctlr_write reg_icc_ctlr_el1_write 1049 #define icc_igrpen1_write reg_icc_igrpen1_el1_write 1050 #define icc_sgi1r_write reg_icc_sgi1r_el1_write 1051 #define icc_iar1_read reg_icc_iar1_el1_read 1052 #define icc_eoi1r_write reg_icc_eoir1_el1_write 1053 1054 #if defined(_KERNEL) 1055 1056 /* 1057 * CPU REGISTER ACCESS 1058 */ 1059 static __inline register_t 1060 cpu_mpidr_aff_read(void) 1061 { 1062 1063 return reg_mpidr_el1_read() & 1064 (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0); 1065 } 1066 1067 /* 1068 * GENERIC TIMER REGISTER ACCESS 1069 */ 1070 static __inline uint32_t 1071 gtmr_cntfrq_read(void) 1072 { 1073 1074 return reg_cntfrq_el0_read(); 1075 } 1076 1077 static __inline uint32_t 1078 gtmr_cntk_ctl_read(void) 1079 { 1080 1081 return reg_cntkctl_el1_read(); 1082 } 1083 1084 static __inline void 1085 gtmr_cntk_ctl_write(uint32_t val) 1086 { 1087 1088 reg_cntkctl_el1_write(val); 1089 } 1090 1091 /* 1092 * Counter-timer Virtual Count timer 1093 */ 1094 static __inline uint64_t 1095 gtmr_cntpct_read(void) 1096 { 1097 1098 return reg_cntpct_el0_read(); 1099 } 1100 1101 static __inline uint64_t 1102 gtmr_cntvct_read(void) 1103 { 1104 1105 return reg_cntvct_el0_read(); 1106 } 1107 1108 /* 1109 * Counter-timer Virtual Timer Control register 1110 */ 1111 static __inline uint32_t 1112 gtmr_cntv_ctl_read(void) 1113 { 1114 1115 return reg_cntv_ctl_el0_read(); 1116 } 1117 1118 static __inline void 1119 gtmr_cntv_ctl_write(uint32_t val) 1120 { 1121 1122 reg_cntv_ctl_el0_write(val); 1123 } 1124 1125 static __inline void 1126 gtmr_cntp_ctl_write(uint32_t val) 1127 { 1128 1129 reg_cntp_ctl_el0_write(val); 1130 } 1131 1132 /* 1133 * Counter-timer Virtual Timer TimerValue register 1134 */ 1135 static __inline uint32_t 1136 gtmr_cntv_tval_read(void) 1137 { 1138 1139 return reg_cntv_tval_el0_read(); 1140 } 1141 1142 static __inline void 1143 gtmr_cntv_tval_write(uint32_t val) 1144 { 1145 1146 reg_cntv_tval_el0_write(val); 1147 } 1148 1149 1150 /* 1151 * Counter-timer Virtual Timer CompareValue register 1152 */ 1153 static __inline uint64_t 1154 gtmr_cntv_cval_read(void) 1155 { 1156 1157 return reg_cntv_cval_el0_read(); 1158 } 1159 #endif /* _KERNEL */ 1160 1161 /* 1162 * Structure attached to machdep.cpuN.cpu_id sysctl node. 1163 * Always add new members to the end, and avoid arrays. 1164 */ 1165 struct aarch64_sysctl_cpu_id { 1166 uint64_t ac_midr; /* Main ID Register */ 1167 uint64_t ac_revidr; /* Revision ID Register */ 1168 uint64_t ac_mpidr; /* Multiprocessor Affinity Register */ 1169 1170 uint64_t ac_aa64dfr0; /* A64 Debug Feature Register 0 */ 1171 uint64_t ac_aa64dfr1; /* A64 Debug Feature Register 1 */ 1172 1173 uint64_t ac_aa64isar0; /* A64 Instruction Set Attribute Register 0 */ 1174 uint64_t ac_aa64isar1; /* A64 Instruction Set Attribute Register 1 */ 1175 1176 uint64_t ac_aa64mmfr0; /* A64 Memroy Model Feature Register 0 */ 1177 uint64_t ac_aa64mmfr1; /* A64 Memroy Model Feature Register 1 */ 1178 uint64_t ac_aa64mmfr2; /* A64 Memroy Model Feature Register 2 */ 1179 1180 uint64_t ac_aa64pfr0; /* A64 Processor Feature Register 0 */ 1181 uint64_t ac_aa64pfr1; /* A64 Processor Feature Register 1 */ 1182 1183 uint64_t ac_aa64zfr0; /* A64 SVE Feature ID Register 0 */ 1184 1185 uint32_t ac_mvfr0; /* Media and VFP Feature Register 0 */ 1186 uint32_t ac_mvfr1; /* Media and VFP Feature Register 1 */ 1187 uint32_t ac_mvfr2; /* Media and VFP Feature Register 2 */ 1188 }; 1189 1190 #endif /* _AARCH64_ARMREG_H_ */ 1191
Indexes created Thu Oct 02 10:09:58 GMT 2025